S-35770 COUNTER IC - ABLIC Inc. · COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE Rev.1.0_00 S-35770 5 Pin Functions 1. SDA (I/O for serial data) pin This is a data input

S-35770COUNTER IC

COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACEwww.ablic.com

© ABLIC Inc., 2019 Rev.1.0_00

1

The counter IC allows for counting externally input clocks. The counter of the S-35770 is a 24-bit binary-up counter. The counter data can be read via a 2-wire serial interface. Features

• External clock signal count function: Countable from 0 to 16,777,215, with output pin for counter loop flag • Low current consumption: 0.01 μA typ. (VDD = 3.0 V, Ta = +25°C, out of communication (CLKIN pin = 0 V)) • Wide range of operation voltage: 1.5 V to 5.5 V • 2-wire (I2C-bus) CPU interface • Operation temperature range: Ta = −40°C to +85°C • Lead-free (Sn 100%), halogen-free

Applications

• Various measurement equipment • Infrastructure-related meter • Amusement equipment • Life counter

Package

• TMSOP-8

COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE S-35770 Rev.1.0_00

2

Block Diagram

Counter(24-bit)

Count register(24-bit)

Free register(24-bit)

Serial interfacePower-ondetection

circuit

Internal reset signal

CLKIN

SDA

SCL

RST

N.C.

LOOP

VDD

VSS

Figure 1

COUNTER IC COUNTER IC WITH 2-WIRE (I2C-bus) INTERFACE Rev.1.0_00 S-35770

3

Product Name Structure 1. Product name

S-35770 E 01 I - K8T2 U

Product name

Environmental code U: Lead-free (Sn 100%), halogen-free

Package abbreviation and IC packing specification*1 K8T2: TMSOP-8, Tape

Operation temperature I: Ta = −40°C to +85°C

Fixed value

Fixed value

*1. Refer to the tape drawing.

2. Package

Table 1 Package Drawing Codes

Package Name Dimension Tape Reel

TMSOP-8 FM008-A-P-SD FM008-A-C-SD FM008-A-R-SD

3. Product name list

Table 2

Product Name RST_______

Pin LOOP Pin Output Form LOOP Pin Output*1 S-35770E01I-K8T2U Without pull-up resistor CMOS output "L"

*1. The output status at power-on.


4

Pin Configuration 1. TMSOP-8

765

8234

1

Top view

Figure 2

Table 3 List of Pins

Pin No. Symbol Description I/O Configuration

1 RST_______

Input pin for reset signal Input CMOS input

(without pull-up resistor)

2 NC*1 No connection − −

3 CLKIN Input pin for external clock Input CMOS input

4 VSS GND pin − −

5 LOOP Output pin for counter loop flag Output CMOS output

6 SDA I/O pin for serial data Bi-directional Nch open-drain output,

CMOS input

7 SCL Input pin for serial clock Input CMOS input

8 VDD Pin for positive power supply − −

*1. The NC pin is electrically open. Therefore, leave it open or connect it to VDD pin or VSS pin.


5

Pin Functions 1. SDA (I/O for serial data) pin

This is a data input / output pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with a clock pulse from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, the SDA pin is pulled up to VDD potential via a resistor, and is used with wired-OR connection of other device of Nch open-drain output or open collector output.

2. SCL (Input for serial clock) pin This is a clock input pin for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with this clock

3. RST_______

(Input for reset signal) pin This pin inputs the reset signal. The counter is reset when inputting "L" to the RST

_______

pin. When inputting "H" to the RST_______

pin, the count-up action of the counter is started. Besides, the RST

_______

pin has no pull-up resistor.

4. CLKIN (Input for external clock) pin This pin inputs an external clock. The counter is incremented by 1 when the CLKIN pin input changes from "L" to "H".

5. LOOP (Output for counter loop flag) pin Each time the counter loops back to 0 after reaching 16,777,215, the LOOP pin performs a toggle operation. Regarding the operation of the LOOP pin, refer to " LOOP Pin". Besides, the LOOP pin output form is CMOS output.

6. VDD (Positive power supply) pin Connect this pin with a positive power supply. Regarding the values of voltage to be applied, refer to " Recommended Operation Condition".

7. VSS pin Connect this pin to GND.


6

Equivalent Circuits of Pins

CLKIN, SCL

Figure 3 CLKIN Pin and SCL Pin

SDA

Figure 4 SDA Pin

RST_______

Figure 5 RST_______

Pin

LOOP

Figure 6 LOOP Pin


7

Absolute Maximum Ratings Table 4

Item Symbol Applied Pin Absolute Maximum Rating Unit Power supply voltage VDD − VSS − 0.3 to VSS + 6.5 V Input voltage VIN CLKIN, SDA, SCL, RST

_______ VSS − 0.3 to VSS + 6.5 V

Output voltage VOUT SDA VSS − 0.3 to VSS + 6.5 V LOOP

VSS − 0.3 to VDD + 0.3 ≤ VSS + 6.5 V Operation ambient temperature*1 Topr − −40 to +85 °C Storage temperature Tstg − −55 to +150 °C

*1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a malfunction.

Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical

damage. These values must therefore not be exceeded under any conditions. Recommended Operation Condition

Table 5 (VSS = 0 V)

Item Symbol Condition Min. Typ. Max. Unit Operation power supply voltage VDD Ta = −40°C to +85C 1.5 − 5.5 V


8

DC Electrical Characteristics Table 6

(Ta = −40°C to +85°C, VSS = 0 V) Item Symbol Applied Pin Condition Min. Typ. Max. Unit

Current consumption 1 IDD1 −

VDD = 3.0 V, Out of communication (CLKIN pin = 0 V), LOOP pin = no load

− 0.01 0.1 μA

Current consumption 2 IDD2 −

VDD = 3.0 V, fSCL = 1 MHz, During communication, LOOP pin = no load

− 170 300 μA

High level input leakage current IIZH

CLKIN, SDA, SCL, RST_______

VIN = VDD −0.5 − 0.5 μA

Low level input leakage current IIZL


VIN = VSS −0.5 − 0.5 μA

High level output leakage current IOZH SDA VOUT = VDD −0.5 − 0.5 μA

Low level output leakage current IOZL SDA VOUT = VSS −0.5 − 0.5 μA

High level input voltage VIH


− 0.7 × VDD − VSS + 5.5 V

Low level input voltage VIL


− VSS − 0.3 − 0.3 × VDD V

Low level output voltage VOL SDA IOL = 2.0 mA − − 0.4 V


9

AC Electrical Characteristics Table 7 Measurement Conditions

0.8 × VDD Input pulse voltage Output reference voltage

0.2 × VDD

0.7 × VDD

0.3 × VDD

Figure 7 Input / Output Waveform during AC Measurement

Input pulse voltage VIH = 0.8 × VDD, VIL = 0.2 × VDD

Input pulse rise / fall time 20 ns

Output reference voltage VOH = 0.7 × VDD, VOL = 0.3 × VDD

Output load 100 pF

Table 8 AC Electrical Characteristics

(Ta = −40°C to +85°C)

Item Symbol VDD = 1.5 V to 2.5 V VDD = 2.5 V to 5.5 V

Unit Min. Max. Min. Max.

SCL clock frequency fSCL 0 400 0 1000 kHz SCL clock "L" time tLOW 1.3 − 0.4 − μs SCL clock "H" time tHIGH 0.6 − 0.3 − μs SDA output delay time*1 tAA − 0.9 − 0.5 μs Start condition set-up time tSU.STA 0.6 − 0.25 − μs Start condition hold time tHD.STA 0.6 − 0.25 − μs Data input set-up time tSU.DAT 100 − 80 − ns Data input hold time tHD.DAT 0 − 0 − ns Stop condition set-up time tSU.STO 0.6 − 0.25 − μs SCL, SDA rise time tR − 0.3 − 0.3 μs SCL, SDA fall time tF − 0.3 − 0.3 μs Bus release time tBUF 1.3 − 0.5 − μs Noise suppression time tl − 50 − 50 ns CLKIN clock frequency fCLKIN 0 400 0 1000 kHz CLKIN clock "L" time tCLKIN_L 1.3 − 0.4 − μs CLKIN clock "H" time tCLKIN_H 0.6 − 0.3 − μs CLKIN rise time tCLKIN_R − 0.3 − 0.3 μs CLKIN fall time tCLKIN_F − 0.3 − 0.3 μs

*1. Since the output form of the SDA pin is Nch open-drain output, the SDA output delay time is determined by the values of the load resistance and load capacitance outside the IC. Figure 9 shows the relationship between the output load values.


10

SCL

SDA (S-35770 input)

SDA (S-35770 output)

tBUF

tR

tSU.STO tSU.DAT tHD.DAT

tAA

tHIGH tLOW

tHD.STA tSU.STA

tF

Figure 8 Bus Timing

1

3

5

7

9

11

13

15

Load capacitance [pF]

Max

imum

pul

l-up

resi

stan

ce[k

Ω]

10

fSCL = 1.0 MHz

fSCL = 400 kHz

100 1000

Figure 9 Output Load

CLKIN

tCLKIN_H tCLKIN_L tCLKIN_F tCLKIN_R

Figure 10 CLKIN Pin Clock Timing


11

External Clock Signal Count Function The S-35770 detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the counter. The counter is a 24-bit binary counter which can count from 0 to 16,777,215 (FFFFFF h). After reaching 16,777,215, the S-35770 detects the change of the CLKIN pin from "L" to "H", the counter loops back to 0. The counter value can be confirmed by reading the count register. To initialize the counter, input "L" to the RST

_______

pin or input the reset command to the free register. Regarding the count register and the reset command, refer to " Configuration of registers".

RST

CLKIN

Counter 16,777,21516,777,21410 0 0 0 12 3 1 2 3 1 2 3

The counter starts the count-up action at the rising edge of CLKIN pin.

The counter is reset by the reset command.

The counter loops back to 0.The counter does not start the count-up action at RST pin = "L".

The counter is reset at RST pin = "L".

Figure 11 Counter Operation

During communication, the S-35770 does not detect the change of the CLKIN pin from "L" to "H" and maintains the counter data. The duration of the communication is defined as the time period from the start condition to the stop condition. The count-up action of the counter is executed 1 time if the CLKIN pin is "L" when the start condition is recognized and if the CLKIN pin is "H" when the stop condition is recognized.

SDASTA STA STA STA STASTO STO STO STO STO

CLKIN

Counter 0 1 2 3 4 5 6

RST

The counter does not start the count-up action during communication.

The counter does not start the count-up action during communication.

The counter does not start the count-up action.

The counter does not start the count-up action during communication.The counter starts the count-up action 1 time when communication ends.

Figure 12 Counter Operation during Communication


12

LOOP Pin The S-35770 detects the change of the CLKIN pin from "L" to "H", and then starts the count-up action of the counter. The counter loops back to 0 after reaching 16,777,215. At this time, the LOOP pin changes from "L" to "H". To change the LOOP pin to "L", input "L" to the RST

_______

pin or input the reset command to the free register. Furthermore, if the counter loops back to 0 again after reaching 16,777,215 under the condition the LOOP pin maintains "H", the LOOP pin changes from "H" to "L". In other word, each time the counter loops back to 0 after reaching 16,777,215, the LOOP pin performs a toggle operation.

CLKIN

Counter 16,777,21516,777,21516,777,21516,777,21410 0 0 0 02 3 1 2 1 2 1 2

RST

LOOP

Figure 13 LOOP Pin Operation


13

Configuration of Registers

1. Count register

The count register is a 3-byte register that stores the counter value as binary code. The count register is read-only. Perform the read operation of the count register in 3-byte unit from CNT23 to CNT0.

Example: 3 (0000_0000_0000_0000_0000_0011) 45 (0000_0000_0000_1010_1000_1100) 19,800 (0000_0000_0100_1101_0101_1000)

CNT0 CNT1CNT2 CNT3 CNT4 CNT5 CNT6 CNT7

B7 B0

CNT8 CNT9 CNT10 CNT11 CNT12 CNT13 CNT14 CNT15

B7 B0

CNT16 CNT17 CNT18 CNT19 CNT20 CNT21 CNT22 CNT23

B7 B0 Figure 14

2. Free register

The free register is a 3-byte register that can be freely read and written by the user. The lower 3 bits, RST2 to RST0 are used as a register to input the counter reset command. The counter is reset by writing RST2 = "0", RST1 = "1", and RST0 = "0". The data of F20 to F0 are not reset when inputting the reset command; however, the data when the reset command is input are set. When only the data of F20 to F0 are rewritten without resetting the counter, write the data except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1" to the free register. Perform the write and read operation of the free register in 3-byte unit.

RST0 RST1RST2 F0 F1 F2 F3 F4

B7 B0

F5 F6 F7 F8 F9 F10 F11 F12

B7 B0

F13 F14 F15 F16 F17 F18 F19 F20

B7 B0 Figure 15


14

Serial Interface The S-35770 transmits and receives various commands via I2C-bus serial interface to read / write data.

1. Start condition

When SDA changes from "H" to "L" with SCL at "H", the S-35770 recognizes start condition and the access operation is started.

2. Stop condition

When SDA changes from "L" to "H" with SCL at "H", the S-35770 recognizes stop condition and the access operation is completed. The S-35770 enters standby mode, consequently.

tSU.STA tHD.STA tSU.STO

Start condition Stop condition

SDA

SCL

Figure 16 Start / Stop Condition

3. Data transmission and acknowledge

The data transmission is performed at every one byte after the start condition detection. Pay attention to the specification of tSU.DAT and tHD.DAT when changing SDA, and perform the operation when SCL is "L". If SDA changes when SCL is "H", the start / stop condition is recognized even during the data transmission, and the access operation will be interrupted. Whenever a one-byte data is received during data transimmion, the receiving device returns an acknowledge. For example, as shown in Figure 17, assume that the S-35770 is a receiving device, and the master device is a transmitting device. If the clock pulse at the 8th bit falls, the master device releases SDA. Consequently, the S-35770, as an acknowledge, sets SDA to "L" during the 9th bit pulse. The access operation is not performed properly when the S-35770 does not output an acknowledge.

tHD.DAT tSU.DAT

1 8 9

Acknowledge output

(Active "L")

tAA

Start Condition

SCL (S-35770 input)

SDA (Master device output)

SDA (S-35770 output)

High-Z

Release SDA High-Z

Figure 17 Acknowledge Output Timing


15

4. Data transmission format

After the start condition transmission, the 1st byte is a slave address and a command (read / write bit) that shows the transmission direction at the 2nd byte or subsequent bytes. The slave address of the S-35770 is specified to "0110010". The data can be written to the free register when read / write bit is "0", and the data of count register or the free regiister can be read when read / write bit is "1". When the data can be written to the free register, input the data from the master device in order of B7 to B0. The acknowledge ("L") is output from the S-35770 whenever a one-byte data is input. When the data of the count register or the free register can be read, the data from the S-35770 is output in order of B7 to B0 in byte unit. Input the acknowledge ("L") from the master device whenever a one-byte data is input. However, do not input the acknowledge for the last byte (NO_ACK). By this, the end of the data read is informed. After the master device receives / transmits the acknowledge for the last byte data, input the stop condition to the S-35770 to finish the access operation. When the master device inputs start condition instead of stop condition, the S-35770 becomes restart condition, and can transmit / receive the data if the master device inputs the slave address continuously.

A

: Master device input data

: S-35770 output data

Slave address

Slave address

Slave address

Data Data Data DataA A A A0 B7 B1 B7 B0 B7 B0 B7 B0 B7 B0

SP ST

A Data Data DataA A A 1 B7 B0 B7 B0 B7 B0

A Data Data Data DataA A A A0 B7 B0 B7 B0 B7 B0 B7 B0

ASlave address Data Data DataA A A 1 B7 B1 R/W B7 B0 B7 B0 B7 B0

SP ST

ST

ST

B7 B1

B7 B1

SP

A

: Start condition

: Acknowledge A A

: Stop condition ST SP

R/W

R/W

R/W

1 9 18 27 36 45

Data write format

Data read format

Restart format

SCL

SDA

SDA

SDA

Figure 18 Data Transmission Format of Serial Interface

In the time period from the start condition to the stop condition, the S-35770 does not detect the change of the CLKIN pin from "L" to "H" and maintains the counter data. Therefore, the output data of the count register does not change even if an external clock is input during a read operation of the count register. Regarding the counter operation during communication, refer to " External Clock Signal Count Function".


16

5. Read operation of count register

Transmit the start condition and slave address from the master device. The slave address of the S-35770 is specified to "0110010". The data of the count register can be read when the read / write bit is "1". The 2nd byte to the 4th byte are used as the count register. Each byte from B7 is transmitted. When the read operation of the count register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 is output from the master device, and then transmit the stop condition. The count register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of the count register. Regarding the count register, refer to " Configuration of Registers".

Disable time period of count-up action

ACK

CN

T23 C

NT22

CN

T21 C

NT20

CN

T19 C

NT18

CN

T17 C

NT16

CN

T15

CN

T13 C

NT12

CN

T11 C

NT10

CN

T9 C

NT8

CN

T7

CN

T14

CN

T6 C

NT5

CN

T4 C

NT3

CN

T2 C

NT1

CN

T0

1 189 27 36

0

Slave address (0110010)

Input NO_ACK after the 3rd byte data is transmitted.

Count register (3-byte)



START

1 1

B7

0 0 1 10

B1 R/W

ACK

ACK

NO

_ACK

STOP

B7 B0 B7 B7B0 B0

SCL

SDA

Figure 19 Read Timing of Count Register


17

6. Write operation of free register

Transmit the start condition and slave address from the master device. The slave address of the S-35770 is specified to "0110010". Next, transmit "0" to the read / write bit. Transmit the 2nd byte data. Set B7 to "1" since it is an address pointer. Set B6 to B1 to "0" or "1" since they are dummy data. Be sure to set B0 to "1" since it is a test bit. B7 in the 3rd byte to B3 in the 5th byte are used as the free register. B2 to B0 (RST2 to RST0) in the 5th byte are used as a register to input the counter reset command. The counter is reset when transmitting RST2 = "0", RST1 = "1" and RST0 = "0". When not resetting the counter, transmit the data except for the above mentioned ones, such as RST2 = "1", RST1 = "1" and RST0 = "1". Transmit the stop condition from the master device to finish the access operation. Regarding the free register, refer to " Configuration of Registers". Write operation of the free register is performed each byte, so transmit the data in 3-byte unit. Note that the S-35770 may not operate as desired if the data is not transmitted in 3-byte unit.

Dummy data*1Slave address (0110010)

Free register (3-byte)

Make sure to set B0 to "1" since it is a test bit.

: Master device input data: S-35770 output data

SCL

SDA

Set B7 as an address pointer.

F[20:13] Write timing

F[12:5] Write timing

F[4:0], RST[2:0] Write timing

0

START

1 1 0 0 1 10

B1 R/W

STOP

ACK

F20

B7 B0 B7 B7B0 B0

0 1

ACK

F19 F18 F17 F16 F15 F14 F13 AC

K

ACK

ACK

F12 F11 F10 F9 F8 F7 F6 F5

F4 F3 F2 F1 F0

RST2

RST1

RST0

B7B0

1 18 9 27 36 45

B7


*1. Set B6 to B1 to "0" or "1" since they are dummy data.

Figure 20 Write Timing of Free Register


18

7. Read operation of free register

Perform the read operation of the free register with the restart format. Regarding the restart format, refer to "4. Data transmission format".

Transmit the start condition and the slave address from the master device. The slave address of the S-35770 is specified to "0110010". Next, transmit "0" to the read / write bit. B7 in the 2nd byte is an address pointer. Set B7 to "0" when reading the free register. Next, transmit the dummy data to B6 to B1. Make sure to set B0 to "1" since it is a test bit. This processing is called "dummy write". Then transmit the start condition, the slave address and the read / write bit. If the read / write bit is set to "1", the S-35770 becomes the mode to read the free register. Consequently, the data of the free register is output from the S-35770. Each byte from B7 is transmitted. When the read operation of the free register is finished, transmit "1" (NO_ACK) to the acknowledge after B0 output from the master device, and then transmit the stop condition. The free register is a 3-byte register. "1" is read if the read operation is performed continuously after reading 3 bytes of the free register. Regarding the free register, refer to " Configuration of Registers".

Moreover, the internal address pointer is reset if recognizing the stop condition. Therefore, do not transmit the stop condition after dummy write operation. The counter data is read when reading the free register after transmission of the stop condition.

1 9 181 9 18 27 36

SCL

1

ACK

ACK

START

ACK

ACK

NO _ACK

STOP

F20F19F18F17F16F15F14F130100110

B1B7 B0B7 B0B7 B0B7

F12F11F10F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

RST2

RST1

RST0SDA

Free register (3-byte)

0

B0B7

Dummy data*1

Dummy write

Slave address(0110010)

1

ACK

START 0100110

B1R/W

0

R/W B7

Slave address(0110010)

Make sure to set B0 to "1" since it is a test bit.Input NO_ACK after the 3rd byte transmission.

Set B7 as an address pointer.

*1. Set B6 to B1 to "0" or "1" since they are dummy data.




Figure 21 Read Timing of Free Register


19

Release of SDA The RST

_______

pin of the S-35770 does not perform the reset operation of the communication interface. Therefore, the stop condition is input to reset the internal interface circuit usually. However, the S-35770 does not accept the stop condition from the master device when in the status that SDA outputs "L" (at the time of acknowledge outputting or reading). Consequently, it is necessary to finish the acknowledge output or the read operation. Figure 22 shows the SDA release method. First, input the start condition from the master device (since SDA of the S-35770 outputs "L", the S-35770 can not detect the start condition). Next, input the clocks for 1-byte data access (9 clocks) from SCL. During the time, release SDA of the master device. By this, the SDA input / output before communication interrupt is completed, and SDA of the S-35770 becomes release status. Continuously, if the stop condition is input, the internal circuit resets and the communication returns to normal status. It is strongly recommended that the SDA release method is performed at the time of system initialization after the power supply voltage of the master device rises.

1 2 8 9

SCL

SDA(S-35770 output)

"L" or High-Z "L" High-Z

"L" or High-Z

Start condition Clocks for 1-byte data access Stop condition

SDA(Master device output)

"L" SDA

Figure 22 SDA Release Method

Power-on Detection Circuit In order for the power-on detection circuit to operate normally, raise the power supply voltage of the IC from 0.2 V or lower so that it reaches 1.5 V of the operation power supply voltage minimum value within 10 ms, as shown in Figure 23.

Within 10 ms

1.5 V (Operation power supply voltage min.)

0 V*1 0.2 V or lower

*1. 0 V means that there is no potential difference between the VDD pin and the VSS pin of the S-35770.

Figure 23 How to Raise the Power Supply Voltage


20

Example of Application Circuit

VIN VOUT

VSS

VRVDD

VSS

SCLSDARST

S-35770VCC

VSS

VCC

CPULOOP

CLKIN

S-1xxx 1 kΩ

1 kΩ

10 k

Ω

External clock

Figure 24

Caution 1. Start communication under stable condition after turning on the system power supply. 2. The above connection diagrams do not guarantee operation. Set the constants after performing

sufficient evaluation using the actual application.


21

Precautions

• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit.

• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.


22

Characteristics (Typical Data) 1. Current consumption 1 vs. Power supply voltage characteristics 2. Current consumption 2 vs. SCL frequency characteristics

Ta = +25°C Ta = +25°C

60

1.0

0.8

0.6

0.4

0.2

420

IDD

1[μ

A]

VDD [V] 1500

0

600

10005000

IDD

2[μ

A]

SCL frequency [kHz]

300200100

400500 VDD = 5.0 V

VDD = 3.0 V

3. Current consumption 1 vs. Temperature characteristics 4. Current consumption 1 vs. CLKIN frequency characteristics

−40 −25 0 25 50 75 85Ta [°C]

0

1.0

0.8

0.6

0.4

0.2

IDD

1[μ

A]

VDD = 3.0 V

VDD = 5.0 V

1500

0

90

10005000

IDD

1[μ

A]

CLKIN frequency [kHz]

8070605040302010

VDD = 5.0 V

VDD = 3.0 V

5. Low level output current vs. Output voltage characteristics 6. High level output current vs. VDD − VOUT characteristics

LOOP pin, SDA pin, Ta = +25°C

LOOP pin, Ta = +25°C

60

70

420

IOL [

mA]

VOUT [V]

605040302010

VDD = 5.0 V

VDD = 3.0 V

6

−25

0

420

IOH

[mA]

VDD − VOUT [V]

−5

−10

−15

−20

VDD = 3.0 V

VDD = 5.0 V

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Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and

application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.

2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein.

3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein.

4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges.

5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use.

6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures.

7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes.

8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products.

9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility.

10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use.

11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc.

12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information

described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc.

14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative.

15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling.

2.4-2019.07

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