S12 XE Course Notes - pudn.comread.pudn.com/downloads120/doc/project/511545/S12XE_Training.pdf · CPX CPY DAA DBEQ DBNE DEC DECA DECB DECW DECX DECY DES DEX DEY EDIV EDIVS EMACS EMAXD

TM

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

Gao Lei

Senior Application EngineerAuto Lab, Freescale

Dec 13th - 2007

S12XE Course Notes

TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 1

Agenda

AM

S12XE / XGATE Training

• S12XE Briefing• S12X Programming Model• Addressing Model• Instruction Set briefing• Memory Map Controller• Memory Protection Unit• External Bus Interface• Interrupt• Flash & Emulated EEPROM• XGATE

PM

S12XE Training Labs

• Lab1: Application Partitioning• Lab2: Scalable event handling• Lab3: XGATE Interrupt Pre-Emption• Lab4: Using semaphores• Lab5: Memory Protection Unit• Lab6: Emulated EEPROM (option)

Test

TM


S12XE Briefing


A Continuum of Excellence

6800

1974

6801

1979

68HC11

1984

68HC12

S12

S12XD

2000 20041995

8MHz16bit + BDM++ opcodes32k Flash, 1k RAM,768 EEPROM

25MHz256k Flash12k RAM4k EEPROM

40MHz++ opcodesInt controllerRefined pagingXGateDBG module512k Flash32k RAM4k EEPROM

S12XE

50MHzXGATE3ECC1M FlashMPU4k EEEATD++

2006

Per

form

ance


Automotive MCU Cores

PowerPC MPC5200(MobileGT)

PowerPC MPC5500

Powertrain ElectronicsEngine Control, Transmission Control

TelematicsNavigationHigh Performance DIS

Central Body ElectronicsBody Control ModulesGatewaysInstrument Clusters

General Body ElectronicsDoor modules, Lighting, Steering column, sunroofOccupant Detection, Keyless Entry, TPMS

S08HC08

Chassis / safetyCollision Avoidance, Vehicle Dynamics

App

licat

ion

/ Per

form

ance

S12(X)


CPU CISC Programming modelVery large instruction set(280+ unique instructions)

ABA

ABX

ABY

ADCA

ADCB

ADDA

ADDB

ADDD

ADDX

ADDY

ADED

ADEX

ADEY

ANDA

ANDB

ANDCC

ANDX

ANDY

ASL

ASLA

ASLB

ASLD

ASLW

ASLX

ASLY

ASR

ASR

ASRB

ASW

ASRX

ASRY

BCC

BCLR

BCS

BEQ

BGE

BGND

BGT

BHI

BHS

BITA

BITB

BITX

BITY

BLE

BLO

BLS

BLT

BMI

BNE

BPL

BRA

BRCLR

BRN

BRSET

BSET

BSR

BTAS

BVC

BVS

CALL

CBA

CLC

CLR

CLRA

CLRB

CLRW

CLRX

CLRY

CLV

CMPA

CMPB

COM

COMA

COMB

COMW

COMX

COMY

CPD

CPED

CPES

CPEX

CPEY

CPS

CPX

CPY

DAA

DBEQ

DBNE

DEC

DECA

DECB

DECW

DECX

DECY

DES

DEX

DEY

EDIV

EDIVS

EMACS

EMAXD

EMAXM

EMIND

EMINM

EMUL

EMULS

EORA

EORB

EORX

EORY

ETBL

EXG

FDIV

GLDAA

GLDAB

GLDD

GLDS

GLDX

GLDY

GSTAA

GSTAB

GSTD

GSTS

GSTX

GSTY

IBEQ

IBNE

IDIV

IDIVS

INC

INCA

INCB

INCW

INCX

INCY

INS

INX

INY

JMP

JSR

LBCC

LBCS

LBEQ

LBGE

LBGT

LBHI

LBHS

LBLE

LBLO

LBLS

LBLT

LBMI

LBNE

LBPL

LBRA

LBRN

LBVC

LBVS

LDAA

LDAB

LDD

LDS

LDX

LDY

LEAS

LEAX

LEAY

LSL

LSLA

LSLB

LSLD

LSLW

LSLX

LSLY

LSR

LSRA

LSRB

LSRD

LSRW

LSRX

LSRY

MAXA

MAXM

MEM

MINA

MINM

MOVB

MOVW

MUL

NEG

NEGA

NEGB

NEGW

NEGX

NEGY

NOP

ORAA

ORAB

ORCC

ORX

ORY

PSHA

PSHB

PSHC

PSHCW

PSHD

PSHX

PSHY

PULA

PULB

PULC

PULCW

PULD

PULX

PULY

REV

REVW

ROL

ROLA

ROLB

ROLW

ROLX

ROLY

ROR

RORA

RORB

RORW

RORX

RORY

RTC

RTI

RTS

SBA

SBCA

SBCB

SBED

SBEX

SBEY

SEC

SEI

SEV

SEX

STAA

STAB

STD

STOP

STS

STX

STY

SUBA

SUBB

SUBD

SUBX

SUBY

SWI

SYS

TAB

TAP

TBA

TBEQ

TBL

TBNE

TFR

TPA

TRAP

TST

TSTA

TSTB

TSTW

TSTX

TSTY

TSX

TSY

TXS

TYS

WAI

WAV

XGDX

XGDY


S12XE Enhancements

� 50MHz CPU Bus Speed

� 100MHz XGate peripheral coprocessor

� Extended CPU instruction set

� Programmable eight level interrupt controller

� Enhanced Memory Management Controller

� New eight channel Periodic Interrupt Timer

� Non-multiplexed 8MB expanded memory bus

� New low-power RC trigger (API) and fast recovery from STOP modes

� Decimal prescaler for Real Time Interrupt module

� Improved SCI featuring hardware bit manipulation for LIN

� Enhanced trigger source options for Analog to Digital Converters

� Amplitude controlled Pierce oscillator (or Full Swing Pierce)

� XGATE Version 3

TM


S12XXXX Programming Model

(CPU)


AccDAccDAccD

S12X – Programmer’s Model

AccAAccAAccA AccBAccBAccB

IXIXIX

IYIYIY

SPSPSP

PCPCPC

CCRCCRCCR

} 2 8-bit Accumulators (A & B)or 16-bit Accumulator (D)

000

000

000

000

000

000

000

151515

151515

151515

151515

151515

151515

777000777

Index Registers (X & Y)

Stack Pointer

Program Counter

Condition Code Register(now 16-bits)


S12XE CPU– Condition Code Register

Updated Condition Code Register

IPL2 IPL1 IPL0

8910

RSVD RSVD RSVD

111213

U RSVD

1415

S

7

X

6

H

5

I

4

N

3

Z

2

V

1

C

0

CCRL = CCR (No change)CCRH = extension to existing CCR

CCRH:CCRL

D = A:B

X

Y

PC

HCS12X = 10 Bytes HCS12 = 9 Bytes

Offset from Stack pointer for Interrupt stack frame differs by 1 from HCS12

Interrupt Stack Frame Comparison

CCR

D = A:B

X

Y

PC

C: Carry/BorrowV: OverflowZ: ZeroN: NegativeI: I-Interrupt MaskH: Half Carry (for BCD)X: X-Interrupt MaskS: STOP Disable


User state• Software cannot set or clear system interrupt enables (X, I), stop

enable (S) or change interrupt priority (IPL[0..2])• Software cannot execute WAI or STOP op-codes• No opcode can change the user state bit (RTI, PULC, EXG etc.)

Once the U-bit is set the only way to unset it is to raise an interrupt or reset

User state Restriction

TM


Addressing ModesAddressing Modes

(CPU)(CPU)


Addressing Modes

INHERENT

IMMEDIATE

EXTENDED

DIRECT

INDEXED

INDEXED 5, 9 & 16 BIT OFFSET

INDEXED 16-BIT INDIRECT ([IDX2])

INDEXED AUTO PRE/POST DEC/INC

INDEXED ACCUMULATOR OFFSET

INDEXED D OFFSET-INDIRECT ([D,IDX])

PC RELATIVE


Indexed - Pre/Post Decrement/Increment

X2000

Y5 6 7 8

5 67 8

MOVW 2 ,X+ ,2,Y+

BEFORE

2002

AFTER

Y

X

3000 3002

AFTER

Other Examples:

MOVW 8,X+, 8,-Y

MOVW 2,X+ ,4,+Y

STAA 1,-SP

STAA 4,SP+

TM


Instruction SetInstruction Set

(CPU)(CPU)


INSTRUCTION SET

Data Handling

Arithmetic

Logic

Data Test

Branch

Jump & Subroutine Calls


EXTENDED MULTIPLY AND ACCUMULATE(EMACS)

OPERATION: (M : M ) * (M : M ) + M ~ M+3) M ~ M+3(X) (X+1) (Y) (Y+1)

X Y

EXAMPLE:

EMACS $1000 (* 32-BIT RESULT *)

15 0 15 0


CONDITION CODE REGISTER INSTRUCTIONS

FUNCTION MNEMONIC OPERATION

CLEAR CARRYCLEAR INTERRUPT MASKCLEAR OVERFLOWSET CARRYSET INTERRUPT MASKSET OVERFLOWACCUMULATOR A CCRCCR ACCUMULATOR A

CLCCLICLVSECSEISEVTAPTPA

0 C0 I0 V1 C1 I1 VA CCRCCR A

OR CONDITION CODE ORCC CCR + OPERAND

AND CONDITION CODE ANDCC CCR ^ OPERAND


CPU

S12X Instruction Set

Enhancements


Strengthen 16bit capability

New 16-Bit Read-Modify-Write Instructions• complementing the 8 Bit counterparts using same addressing

modes• INCW,DECW,NEGW,LSRW,ROLW,RORW,ASRW,ASLW,CLRW

Compiler advantages:• Orthogonal handling of 8 and 16-Bit data types• Condition code reflect the 16-Bit result avoiding additional tests


CPU12X – X, Y Accumulators

Logical and arithmetic instructions for X, Y registers• Complementing instructions available on D accumulator• NEG, COM, ROR, ROL, LSL, LSR, ASR • BIT, OR, AND, EOR, CLR, TST• ADD, ADC, SUB, SBC

X, Y can also act as 16Bit Accumulators.• All instructions working with 8-Bit Accumulators A or B will work with X, and

Y.• New instructions: add, ade, sub, sbe, cpe, neg, clr, tst, com, asr, lsr, lsl, rol,

ror, and, bit, eor, orCompiler advantages:

� More accumulators reduce bottleneck of D=(A:B) accumulator� 16Bit data easier to handle� Condition code reflect the 16-Bit result avoiding additional tests� 32Bit support, most compilers treat X:D or Y:D as a 32 Bit

concatenated accumulator� zero and carry flag new forwarding scheme allowing easy 32 bit

arithmetic instructions followed by conditional branches

TM


Memory Mapping Controller


MMC Memory Map Overview

The S12X family features a global memory space of 8MB

• Included in this space are all on-chip and off-chip resources

� peripheral registers, RAM, EEPROM, Flash, and expanded peripherals

2k Register

1k EEPROM

8k RAM

16kunpagedFLASH

16kPPAGEFLASH

16kunpagedFLASHVectors

4k RAM

1k EEPROM

4MByte FlashAccessible via

PPAGE

Fixed page

~1MRAM rsv’d

8k RAM

24k RAM

252KEEPROM

rsv’d

1K EEPROM

3K EEPROM

2k Register

Depending onPin out

Extern ~3MB

The memory space visible to the core CPU is called the local map

The 16-bit core CPU has access to all of the global resources

• Access to the global space is built in to the MCU via dedicated opcodes and paging registers

Global Map

Local Map


MMC Global 8MB Map

• The global map describes the memory space that contains all on-chip and off-chip resources

• The S12X global map consists of up to

� 2k of register space� 256k of EEPROM� ~1M of RAM� 4M of Flash� ~3M of external expansion

• Memory Paging� Global resources are paged into the

local map as required

$7F_FFFF

$00_0000

$10_0000

$14_0000

$00_0800


PPAGE

Fixed page

~1MRAM rsv’d

8k RAM

24k RAM

252kEEPROM rsv’d

1k EEPROM3k EEPROM

2k Register

Depending onPin out

Extern ~3MB$40_0000

Bluefin1 12K

$0F_7FFF$0F_8000

$0F_DFFF$0F_E000


MMC Local 64k Map

$0000

$0800

$1000

$4000

$8000

$C000

$FFFF

$2000

2k Register

1k EEPROM

8k RAM

16kunpagedFLASH

16kPPAGEFLASH

16kunpagedFLASH

Vectors

4k RAM

1k EEPROM$0C00

4K RAM4K RAM

4K RAM4K RAM

1k EEPROM1k EEPROM

1k EEPROM1k EEPROM

S12X Memory Map

Registers, RAM, EEPROM and Flash cannot be moved.No INITRG, INITRM or INITEE registers

There are fixed and paged areas of EEPROM, RAM and Flash

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

16kPPAGEFLASH

Page 0

Page 1

Page $FFPage $FE 256 pages x 16K = 4MB


MMC Local Map Paging Mechanism

2k Register1k EEPROM

$0000

4k RAM

$0800

$1000

16kunpagedFLASH

$4000

16kPPAGEFLASH

16kunpagedFLASH

$8000

$C000

Vectors$FFFF

64K Local Space

4k RPAGE

16kPPAGE

1k EPAGE

64k GPAGE

8MByte Global Space


PPAGE

Fixed pages$7F_FFFF

$00_0000

$10_0000

~1MRAM rsv’d

8k RAM24k RAM

252kEEPROM rsv’d

1k EEPROM3k EEPROM

2k Register

$14_0000

$00_0800

Depending onPin out

Extern ~3MB$40_0000

8k RAM$2000

1k EEPROM$0C00


MMC Local Map Paging Example 1

2k Register

1k EEPROM

$0000

8k RAM

$0800

$1000

16kunpagedFLASH

$4000

16kPPAGEFLASH

16kunpagedFLASH

$8000

$C000

Vectors$FFFF

64K Local Space

64k GPAGE

8MByte Global Space

$10_0000

~1MRAM rsv’d

8k RAM

252kEEPROM rsv’d

1k EEPROM$14_0000

$00_0800

4k RAM$2000

1k EEPROM$0C00

4k RAM4k RAM4k RAM4k RAM4k RAM4k RAM

1k EEPROM1k EEPROM1k EEPROM

OROR(RPAGE)(RPAGE)

FIXEDFIXED


MMC Local Map Paging Example 2

2k Register

1k EEPROM

$0000

8k RAM

$0800

$1000

16kunpagedFLASH

$4000

16kPPAGEFLASH

16kunpagedFLASH

$8000

$C000

Vectors$FFFF

64K Local Space 8MByte Global Space

$10_0000

~1MRAM rsv’d

8k RAM

252kEEPROM rsv’d

1k EEPROM$14_0000

$00_0800

4k RAM$2000

1k EEPROM$0C00

4k RAM4k RAM4k RAM4k RAM4k RAM4k RAM

1k EEPROM1k EEPROM1k EEPROM

OROR(EPAGE)(EPAGE)

FIXEDFIXED

Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005

28

16k Flash

Local Map Flash Paging

8MByte Global Space

$7E0000

16k Flash $7FFFFF

$780000

16k Flash16k Flash16k Flash

64k Local Space$0000

2k Register

1k unpagedEEPROM

8k unpagedRAM

4k paged RAM

1k paged EE

16k unpagedFLASH

16k pagedFLASH

16k unpagedFLASH

$1000

$4000

$8000

$C000

$FFFF

16k Flash16k Flash16k Flash16k Flash

128k Flashin 16k pages



OROR(PPAGE)(PPAGE)

FIXEDFIXED

$7C0000

$7A0000

Logical Address = $E08000(PPAGE = $E0)


MMC Direct Addressing Mode support

2K Register

1K EEPROM

$0000

8K RAM

$0800

$1000

16KunpagedFLASH

$4000

16KPPAGEFLASH

16KunpagedFLASH

$8000

$C000

Vectors$FFFF

4K RAM$2000

1K EEPROM$0C00

On S12X the direct page is not fixed at $0000

• Programmable in the DIRECT register

• Write once• Can be placed at any

256byte boundary in memory

• Defaults to $0000

DIRECTDP15 DP8

DIRECT provides the upper 8 bits of every direct addressing mode instruction


MMC Global Page

The GPAGE register provides access to 64k pages anywhere in global memory

• Independent of local paging• Writable at any time• Can be placed on any 64k

boundary• Supported by new CPU

opcodes• Defaults to $00

GPAGE=0

GPAGE value provides top 7 bits of base of 64k page

GPAGE=$7F

GPAGE=$14

8MByte Global


PPAGE

Fixed pages$7F_FFFF

$00_0000

$10_0000

~1MRAM rsv’d

8k RAM24k RAM

252kEEPROM rsv’d

1k EEPROM3k EEPROM

2k Register

$14_0000

$00_0800

Depending onPin out

Extern ~3MB$40_0000


MMC Global Page Support

• S12X has a complete set of Load & Store instructions to allow the 7 bit global address register to form a 23 bit global address

• All Load and Store instruction have companion GxxxxGLDAA,GLDAB,GLDD,GLDX,GLDY,GLDS,GSTAA,GSTAB,GSTD,GSTX,GSTY,GSTS

� With same addressing modes as today.� If such an instruction is executed the address is concatenated from the new 7-Bit

GPAGE register + standard 16Bit address� 23Bit address = {7-Bit GPAGE, 16 Bit address}

• Example: � GPAGE = $20, then GLDX $1234 reads from address $20_1234

GPAGE[6:0] AB[15:0]

GAB[22:0]


MMC Local Map Summary

The core controls the contents of the local map by using paging registers

• There are page registers for the RAM, EEPROM and Flash• This is in addition to fixed segments of RAM, EEPROM and Flash

The core can also access any location in the global map via the global paging mechanism

• This is independent from the local map contents• It is supported by dedicated core instructions• It adds an extra degree of freedom in using global resources

TM


Memory Protection Unit


Memory Protection Unit

The Memory Protection Unit allows users to protect memory-mapped resources from undesired access

The MPU supports multiple bus masters in the MCU• CPU, XGATE, 1 other in future, e.g. Flexray module

The MPU is always active and specifies memory ranges:• Where access is allowed and the type of access• For each master

CPU includes additional integrated supervisor state• Allowing access to system resources• Additional bit in CCR controls current state


MPU - Functionality

The MPU consists of a set of eight Protection DescriptorsEach descriptor defines a master, a memory range and access privileges

• There are three possible masters including the CPU which has two MPU states

• The memory range is defined by 23-bit global memory and has a resolution of 8 bytes

• Access privileges control ability to write to memory and to execute code from memory in four combinations

Each descriptor may be enabled individuallyDescriptors can be configured dynamically

• Typically by CPU in supervisor state during task switching


MPU - Descriptor (1)

Master select details• Four masters possible (two assigned to CPU)• The descriptor will allow access for the specified master(s)• Additional bit disables protection for CPU in supervisor state

LowerAddressHigherAddress

23

Address low [22:3]

7

WP NEX

019

Address high [22:3]

XGATE2

Other master (not used on 9S12XE100)3

CPU in user state1

CPU in supervisor state0

Bus Master SelectedMSTR

0 0

MSTR0

MSTR1

MSTR2

MSTR3



Access configuration is defined by two bits in each descriptor• No Execute (NEX) and Write Protect (WP)• Combination gives four access configurations


Address low [22:3]

WP NEX Address high [22:3]

1

0

1

0

NEX

Flash Code RegionRead, execute1

Flash data regionRead1

Stack and data regionsRead, write0

Executing code from RAMRead, write, execute

0

Example of useAccessWP

0 0

23 7 019MSTR

0MSTR

1MSTR

2MSTR

3



Address range• Full global address range $000000..$7FFFFF• Granularity: 8 bytes• Using global address allows

� Consistency across all masters� Inclusion of peripherals and memories on expanded bus

• Defines permitted accessIf low address is set higher than the high address then the descriptor is disabled


Address low [22:3]

WP NEX Address high [22:3]0 0

23 7 019MSTR

0MSTR

1MSTR

2MSTR

3


MPU – CPU State

The CPU includes enhancements to support MPU operation• Two new states of operation: Supervisor and User• The current state is stored in CCR for correct interrupt return• Automatically switches to Supervisor state on interrupts• New OS call opcode: SYS => similar to SWI non-maskable int

These enhancements simplify task switching and driver calls• Supervisor state is selected at reset to allow system initialisation• Change from Supervisor to User state is under software control

� Software kernel controls privileges in system• Change from User to Supervisor state by any interrupt

� Typically using the SYS interrupt� All CPU interrupt handlers run in Supervisor state

• System calls through non-maskable SYS interrupt opcode� Allow system handlers to run in Supervisor mode


MPU – CPU Additional State Permissions

The CPU provides additional permissions differences between Userand Supervisor state

• In addition to the descriptors provided by the MPU

Supervisor state:• While the Access Error Flag bit is set the CPU can still access the

peripheral memory space� This implicit range definition prevents the CPU being unable to service the

access violation if no descriptor is configuredUser state

• Software cannot set or clear system interrupt enables (X, I), stop enable (S) or change interrupt priority (IPL[0..2])

• Software cannot execute WAI or STOP op-codes• No opcode can change the user state bit (RTI, PULC, EXG etc.)• U-bit restricts the CPU operation even if the MPU is not in use!


MPU – Changes to the CPU

New U = User State Bit• 1 = User State, 0 = Supervisor State (reset condition)

Location of PPAGE changed to simplify software creation• Moved from $0030 to $0015 ($0015 was reserved) • Implicit descriptor for paging registers region 0x0010 – 0x0017

� Only applies for the CPU� XGATE and other masters are always blocked

• Porting code and using tools will involve trivial change


MPU in action


MPU – Violation Notification

The MPU detects violations and sends interrupts to CPU• Access violation interrupts are not maskable• Independent interrupt for each master

CPU violation conditions are captured for recovery or debug• Address of violation and condition that was violated

Other master violations are routed to CPU via that master• For XGATE this uses the software error interrupt

RSVD RSVD SVSF

012

NEXF RSVD RSVD

345

AEF WPF

67MPUFLG

Access error flag

Write violation

Execute violation

CPU was in supervisor

state


MPU – Shared Descriptors

Multiple masters may share a descriptor• In this case the access privileges will be the same for all masters

If different privileges are required then there are two approaches possible

• Configure multiple descriptors for the same address range• Create overlapping descriptors so that each master has appropriate

access


23

Address low [22:3]

7

WP NEX

019

Address high [22:3]0 0

Master select [0:3]


MPU – Overlapping Descriptors

IF a protection descriptor memory range overlaps another AND the same bus master is defined THEN the restrictions for the overlappedmemory range are accumulated.For example

• PD0: CPU User; $40_0000-$41_BFFF; read only, execute• PD1: CPU User; $40_8000-$41_FFFF; read/write, no execute• Sum: CPU User; $40_8000-$41_BFFF; read only, no execute

100_0000_0000_0000_0000_01 0 100_0001_1011_1111_1111_10 0

0 1 0 0

100_0000_1000_0000_0000_00 1 100_0001_1111_1111_1111_10 0

0 1 0 0

100_0000_10001000_0000_0000_01 1 100_0001_10111011_1111_1111_10 0

0 1 0 0

PD0

PD1

Overlap


Note

Some bus masters perform pre-fetches past the current instruction. This could cause a violation if the next instruction is beyond the descriptor range even if the instruction is never executed.

Always allow sufficient memory in a descriptor range to account for this.


MPU – Initial Configuration

The MPU is always enabledAt reset the configuration is set such that all accesses by all masters are allowed.

• Descriptor 0 applies to all masters and all memory for all accessCPU is in Supervisor state

• Full access to all op-codes and CCR bits• Supervisor state is not monitored• Gives control of privileges to kernel/initialization code


MPU – Protection Descriptor Usage

Typical uses of PDs� Task Stack� Task Variables� Global Variables� Task Code� Library Code� Task Constants (EEE)� Global Constants (Flash)� XGATE code area

Lower Address

Higher Address

Attributes

PDPD

PDPD

PDPD

PDPD

TM


External Bus Interface


External Bus Interface

DATA[15:0]

RE

WE

ECLK

LSTRB

S12XS12X

•XADDR – Expansion Bus up to 8 Mega Byte address spac e •AD[15:0] - Address/Data Bus

• ECLK – Bus Freq divided by 1, 2, 3, 4 or off.• ECKX2 = Bus Freq *2

• LSTRB - Low byte strobe signal -> used to enable data on the low byte of the addre ss bus

• RE- Read = 0• WE- Write = 0

-> used to determine the data bus direction

XADDR[6:0]

ADDR[15:0]

EWAIT

ECLKX2


Expanded bus

The new expanded bus was driven by design considerations and limitations of S12 approach

• S12 bus had fixed access times for peripherals� No way for peripheral to control access time needed

• Multiplexed bus is not suitable for 40MHz bus speed� Would need < 10ns access memory

• S12 requires glue logic for most peripherals� E.g. 2ns address hold time needs to be extended

• New interface only available in 144pin package


Expanded Bus – Overview 1 of 3

• Provides glueless interface to asynchronous RAMs with >=1 waitcycles• Interfaces easily to e.g graphics controllers requiring a free running clock

and an EWAITb input• Free running ECLK divide by /1, /2, /3, /4 or off.• Three chip selects for

� Program Memory 4MByte - Internal Flash ($40_0000 - $7F_FFFF)� Data Space 2MByte ($20_0000 - $3F_FFFF)� Data or program space 16K visible in 64K Space($4000 - $7FFF)

Port D

D[7

:0]

Bi-directional Data Bus

Port C

D[1

5:8]

Port B

A[7

:0]

Port A

A[1

5:8]

Port K[6:0]

A[2

2:16

]

Address Bus (8Mbyte Space)W

E

RE

LDS

UD

S

CS

0

CS

1

Control Signals

CS

2

EC

LK

EW

AIT

Note: CS2-0, UDS, LDS, RE, WE and EWAIT are active low signals


Expanded Bus Timing Diagram 2 of 3

25ns = 40MHz

Write Data

WE

Data

• Required Tacc with one wait state 25ns @ 40MHz • Configurable 2,3 or 4 wait states

• EWAIT input can be enabled and hold the CPU ad infinitum• RE pulse asserted ½ bus cycles after assertion of CS• WE pulse asserted ½ bus cycle after and de-asserted ½ bus cycle before CS

Address

Data

CSx,UDS, LDS

Read Data

4a2a 2b 4b 2c 4c 2dInternalClock

Address

RE


Application

S12XDP512

HCS12X Expanded Bus 3 of 3

• Glueless interface to standard asynchronous memories

16-BitExternal Memory

Port ABK

Port CD

Port J

Port E

Flash

Address

D/Q

CS

UDS

LDSREWE

TM


Interrupt


Interrupt Controller Overview

Provides 7 interrupt Levels + 1 for disabledEach interrupt source has a dedicated control register that

• Indicates priority level• Directs interrupt to either CPU or XGATE• Out of reset configures all interrupts to level 1 and directs them to the

CPUProvides movable vector table

• Allows vectors to be placed in any 256 byte page


Interrupt Module Architecture (CPU view)

Cro

ss b

ar s

witc

h

Up

to 1

17 In

terr

upt R

eque

sts

Inte

rrup

t Vec

tor

Bas

e R

egis

ter

16

8

8

VectorAddress

Lower Address Bits

Upper Address Bits

Priority Decoder

7

Priority Decoder

2

Priority Decoder

1

Disabled

TopLevel Decoder

Winnerof the

Winners


Interrupt Controller Operation

Interrupt controller determines interrupt priority for both the CPU and XGATE

• The pending interrupt with the highest priority is the next taken• The CPU has the option of allowing nested interrupts if the interrupt

mask bit is cleared (CLI)� Only higher priority interrupts will be taken� If more than one higher priority interrupt is pending then the one with the

highest priority will be taken• If level is set to 0 then interrupt is always ignored

� Stays pending until priority is modified

The CPU records the current interrupt processing level• In the high byte of the CCR (newly added)• Level is stacked with the standard interrupt frame


Interrupt Controller Example

XXX

0XX

30X

0XX

0XX

0XX

XXX

0 3 7 3 2 1 0

Resume 3

7 interrupts 3

2 higher than pending 1

RTI

0

234

1

567

Pro

cess

ing

Leve

l

RTIRTI

* IPL[2:0] is stored on the stack with the new high byte of the CCR

IPL*


Configuring the Interrupt Controller

Each interrupt source is configured individuallyTo save space in the memory map interrupt configuration is done 8 sources at a time by switching in the relevant page of registers

RQST| | | | |ILVLRQST| | | | |ILVLRQST| | | | |ILVLRQST| | | | |ILVL

RQST| | | | |ILVL

RQST| | | | |ILVLRQST| | | | |ILVLRQST| | | | |ILVL

InterruptConfiguration

register

Choose interrupt configuration by selecting appropriate page of registers


Interrupt Controller – Compatibility

All interrupt requests are set to priority 1 out of reset and have the same relative priority as today.

Incompatibilities• Removed HPRIO register

� Functionality completely encompassed by the new module• Not possible to interrupt at the same level

� On S12 any interrupt can occur once the I flag is cleared; on S12X only interrupts at least one level higher can occur

� This means that the default setting is not 100% compatible with S12• Bus timing can cause one additional cycle latency


Interrupt Controller – Hints & Tips

IVBR (Interrupt Vector Base Register)• Consider using this to select a different vector table if multiple modes

exist� E.g. if an SCI is used with a different protocol in a debug mode then consider

selecting a new vector table that points to a different vector when in this mode.

Interrupt levels• The interrupt configurations are writable at any time, use this to manage

interrupt servicing� E.g. if a low level interrupt is never being serviced. Consider raising the level

dynamically or switching it to be handled by XGATE.� Interrupt sources can be blocked by setting the priority level to 0.

TM


S12XE Flash and Emulated EEPRROM


Flash Technology Module (FTM) Overview

On the S12XE Flash and EEPROM control is supported by a single Flash Technology Module (FTM)The FTM contains five independent blocks

• Four P-Flash blocks (Program flash) intended for program storage• One D-Flash (Data flash) block intended primarily for NVM data storage

and for Emulated EEPROM (EEE) storageThe S12XE has a dedicated memory controller to perform all flashand automated EEE operations The EEE appears to the user as a region of non-volatile RAMBoth P-Flash & D-Flash have Error Correction Coding (ECC)Margin Read verify is provided to allow detection of marginal programming of data in the production flow


FTM Software Interfaces

The on-chip programmable cores can access the FTM in three distinct ways

• Reading memory contents and status� Reading code and constant data from the P-Flash and D-Flash � ECC error flags� Memory status flags

• Programming and erasing flash� Using Common Command Object (CCOB) commands

• EEE sub-system� User data is read and written to a buffer RAM� Error flags� Status of NVM writes and FTM activity


Implementation of ECC

P-Flash • Implemented as 64-bit data + 8-bit ECC syndrome• Each 8-bit syndrome is associated with 4 words of flash (a phrase)• Phrases are mapped to 4-word aligned boundaries• Must always be programmed 4 words at a time (8-bytes) to allow the 8-

bit syndrome to be generated from the 64-bits of data

D-Flash • Implemented as 16-bit data + 6-bit ECC syndrome• Must be always be programmed as words (2-bytes) to allow the 6-bit

syndrome to be generated• Words are mapped to 2-byte aligned boundaries• Byte writes to EEE generate a word write to the D-Flash


ECC capabilities

The ECC can• Resolve (repair) single bit errors• Detect double bit errors

ECC is checked on each read of the D-Flash or P-Flash arrays and on each program operationEEE records in D-Flash are ECC qualified

• Reads of the EEE buffer RAM are not ECC qualifiedThe FTM configuration bytes all reside in the same P-Flash phrase (0x7FFF08’G) and must be programmed at the same time

• The EEE Protection byte• the P-Flash Protection byte• the Flash Option Register (COP configuration)• and the Flash Security byte


Programming and erasing flash

All P-Flash and D-Flash programming and erasing operations are performed by:

• Writing command information (data and global addresses)• To a set of 6 banked word registers called the Common Command

Object (CCOB)• Clearing the CCIF flag in the to launch the command

This is different to the S12 where the data is written at the appropriate flash addressOn completion the CCIF flag is reset by the FTM and the error and status flags in the FSTAT register indicate if the memory access was successfulThe flash commands use the S12X global address format.

• On the 9S12XEP100 the P-Flash occupies a linear address range from 0x70FFFF’G to 0x7FFFFF’G


CCOB Command Format

The Common Command Object (CCOB) parameters are banked to save space in the memory map

• They are indexed using the CCOBIX register

Not all commands require all six parametersThe CCOBIX register must point to the last valid parameter when it is launchedSome commands return data from the FTM in the CCOB

FFCOB

FCCOBIX

000

001

010

011

100

101

Word2

Word1

Word3

Word4

Word5

Word6


CCOB Command Example

This example shows a Program P-Flash command• The first word includes the command byte and the upper byte of the

global address• The second word contains the lower 16-bits of the flash address• The following four words contain the data to program starting at the

defined flash address


Loading data to program multiple blocks

The Load Data Field command allows users to speed up programming of multiple P-flash blocks by writing the data for additional P-Flash blocks on the same programming command

• Allows the FTM to optimise its programming sequenceThe command format is the same as the Program P-Flash command, however the data is temporarily stored

• The actual write to the flash is executed by launching a Program P-Flash command on the last block in the sequence

The same 256KByte relative phrase address must be used for blocks being writtenThis differs from the S12 ability to program blocks in parallel and does not offer equivalent speed improvements


Loading data to program multiple blocks

Data for any number of blocks can be written in any sequenceExample sequence

• Load Data Field 0x70_0010’G with dataA, dataB, dataC, dataD (load a phrase)

• Load Data Field 0x74_0010’G with dataE, dataF, dataG, dataH (load another phrase)

• Load Data Field 0x78_0010’G with dataI, dataJ, dataK, dataL(load another phrase)

• Program P-Flash 0x7C_0010’G with dataM, dataN, dataO, dataP(program all phrases)

This approach provides the largest benefit at lower bus frequencies. The above flow can provide 10%- 50% improvement over 4 separate Program P-Flash operations


Emulated EEPROM


Emulated EEPROM

Emulated EEPROM provides a hardware replacement for the typical software EEPROM driver

• Provides dedicated RAM buffer� Initialised at reset� User sees a Virtual NVRAM

• Automated programming of NVM when buffer contents change• Higher write/erase performance and endurance possible due to large

dedicated D-flash• ECC provided by hardware

The D-flash block is fully or partly available to the user if requiredUser can track number of EEE programming operations still

outstanding


D-Flash(e.g. 16kx22)

Memory Controller

Tag-RAM(e.g. 128x16)TAG Counter

128 x 256 bytes.

SystemBus

Buffer-RAM(e.g. 2kx16)

Hardware EEE

PROGRAM:• A write to EEE sets an

associated tag and increments a Tag counter

• The FTM clears tag and decrements Tag Counter and then stores the data.

• When Tag Counter = 0 and MGBUSY = 0 all programming is complete

READ:• ‘Read-While-Write’ supported• During a reset the NVM data

is copied back to the RAM


EEE Concept – user view

Write to EEE

Read EEE immediatelyand at any time

EEE

(subject to EEEprotection)


EEE Concept – MCU process

Write to EEE

EEE StateMachine

EEE

D-Flash

Tag store

Tag counter


EEE Concept – MCU process

Write to EEE

EEE StateMachine

EEE

D-Flash

Tag store

Tag counter


Controlling EEE

The D-Flash / buffer RAM can be partitioned for use as a combination of flash and EEE

• EEE size from 0 to 4096 bytes in 256 byte steps.

• EEE requires a minimum of 12 sectors

The minimum ratio of EEE NVM to EEE RAM is 8 flash sectorsfor each 256 byte RAM region

• Higher ratios offer improved cycling

D-Flash128 sectors of 256 bytes.

Buffer-RAM

Up to 16 regions of 256 bytes.

EEE RAM

UserD-Flash

EEE NVM

User RAM

0x13_FFFF ‘G

0x13_F000 ‘G

0x10_0000 ‘G

0x10_7FFF ‘G


Configuring EEE

Enable DF is a run once command used to partition EEE / D-FlashIt takes 2 parameters

• ERPART = Number of 256 byte regions of EEE-RAM

• DFPART = Number of 256-byte D-Flash sectors for user flash

For EEE use • (128 – DFPART)/ERPART >=

8DFPART /ERPART are stored in the D-Flash configuration cells

D-Flash128 sectors of 256 bytes.

Buffer-RAM

Up to 16 regions of 256 bytes.

EEE RAM

EEE NVM

User RAM

0x13_FFFF ‘G

0x13_F000 ‘G

0x10_0000 ‘G

0x10_7FFF ‘G

UserD-Flash


Note:Enable DF is not an application command!

It is only available in special modes and should be run during initial device

programmingIt partitions and low level formats the EEE

sub-system to an erased value of 0xFF. For production devices it should be run one time

only to define the size of the device EEE


Controlling EEE

Enable EE and Disable EE commands start and pause the EEE• Disable EE does not affect the TAG RAM or counter state

Writes to the buffer RAM continue to set TAGs and increment the TAG counterWhen re-enabled pending data in the buffer RAM is written to the D-FlashThe Cancel EE command halts the EEE system, clears the TAG counter and the TAG RAM

• Be careful!


EEE On Reset

Once an EEE partition has been created, on subsequent resets, the FTM automatically copies data from the designated EEE NVM to theEE RAMAs with all FTM commands the CCIF flag is held low to indicate that the memory controller is busy

• Once the transfer is complete CCIF will go high and any access errors are reported in the FSTAT and FERSTAT registers.

If the CPU accesses the EEE RAM before the the data copy from the EEE NVM has completed the CPU will be halted until it has completed

• (on first silicon this is true for the whole buffer RAM)Following reset, before writing the EEE, the CPU must configure the FTM clock divider (FCLKDIV register)

• If not configured the EEE Access Error Interrupt Flag will be set and the data will not be transferred to the EE NVM


Example EEE application flow

First time only, run the Enable DF command to allocate and format the EEE (FDIVCLK must be initialised)

On subsequent Resets, the EEE data is automatically transferred from the designated EEE NVM to EEE RAM.

• Once the transfer is complete the CCIF flag will go highBefore accessing the EEE RAM configure the FTM clock divider in

the FCLKDIV registerFollowing the FCLKDIV write, data in the EEE RAM can be accessedWrites increment the TAG counter but the data will not be backed up

to the D-Flash until the Enable EE command is runOnce Enable EE is executed any pending data in the EEE will be

backed up to the D-Flash, as will any further data changes


Other EEE points

If EEE is not required • The default is for the buffer RAM and the D-Flash to be available for use

in the application with no EEE allocated. • Best practice is to run Enable DF with ERPART = 0 and DFPART = 128 • The EEE commands should not be used in the application

Note – the ERPART and DFPART values are not memory mapped and are required in addition to the S-record when programming the device.

TM


XGATE Architecture


What is XGATE?

XGATE can be• Peripheral Co-processor• Programmable DMA Controller• Alternative algorithm execution unit• Configurable watchdog system• Real-time interrupt handler• Virtual peripheral controller• OS Task scheduler• Power efficient alternative controller

CCR (N,V,C,Z)CCR (N,V,C,Z) 001515

PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515

R1 = BaseR1 = Base 001515

R0=0R0=0 001515

interrupt void TimerChannel3(){

volatile tU16 timeout = 0x40;Timer.tc[3].word += 0x3000;while (timeout >0){

timeout--;PTH.byte = 2;

}}


What is XGATE?




}}


PCPC 001515

R7R7 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515

R1 = Variable BaseR1 = Variable Base 001515

R0=0R0=0 001515


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515

Event driven

16-bitRISC Engine


What is XGATE?




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


PCPC 001515

R7R7 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


What is XGATE?




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


PCPC 001515

R7R7 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


0000 f440 LDL R4,#640002 f200 LDL R2,#PART_0_7(Timer)0004 aa00 ORH R2,#PART_8_15(Timer)0006 4b56 LDW R3,(R2,#22)0008 eb30 ADDH R3,#48000a 5b56 STW R3,(R2,#22)000c f202 LDL R2,#2000e f300 LDL R3,#PART_0_7(PTH)0010 ab00 ORH R3,#PART_8_15(PTH)0012 3c02 BRA L180014 c401 SUBL R4,#10016 5260 STB R2,(R3,#0)0018 L18: 0018 1880 CMP R4,R0001a 25fc BNE CCR, , L14001c 0200 RTS

What is XGATE?




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


PCPC 001515

R7R7 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515





}}

What is XGATE?




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


PCPC 001515

R7R7 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


Event Driven?

The individual events which trigger execution of XGATE code are provided by the interrupt controller.

• Peripheral hardware or software interrupt sources can be assigned to the XGATE

• or the CPU• individually• dynamically• with a given priority




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


Event Sourcing

Per

iphe

ral

Mod

ules

ServiceRequests

InterruptRequests In

terr

upt

Prio

rity

Dec

oder

XGATEModule

XG

AT

E R

eque

stP

riorit

y D

ecod

er

CPUInterrupt


Event Sourcing

Per

iphe

ral

Mod

ules

ServiceRequests


terr

upt

Prio

rity

Dec

oder

XGATEModule

XG

AT

E R

eque

stP

riorit

y D

ecod

er

CPUInterrupt


XGate – Service Request Overview

Per

iphe

ral

Mod

ules

ServiceRequests

ILVL2 ILVL1 ILVL0


terr

upt

Prio

rity

Dec

oder

XGateModule

XG

ate

Req

uest

Prio

rity

Dec

oder

CPU_INT

RQST = 0

RQST = 1

RQST


A possible system approach

Per

iphe

ral

Mod

ules

ServiceRequests


terr

upt

Prio

rity

Dec

oder

CPUInterrupt

XGATEModule

XG

AT

E R

eque

stP

riorit

y D

ecod

er


Address

Address

XGate interrupt request routing

Interruptsource

(SCI, SPI,...)

Core

XGate

INT controller...

...

XGate VCT

......

ADDRESS

DATA

PC

R1

…...

.

XGate ???.cxgate:voidISRn(*data){

...}

The interrupt event generated by the peripheral gets translated by the interrupt controller and through the XGate interrupt vector table into the action of a thread execution by the XGate.

...

ISRx

ISRy

CPU12 VCT

ADDRESS

DATA PC

R1

???.cxgate:voidISRn+1(*data){

...}

PC

PC


Scheduling event handling (XGATE V2)

XGATE V2 can handle a single event at a time• Thread execution is not interruptible

� There is no inherent stack support

Pending events wait until the XGATE is free• Waiting events will be taken in order of their priority• This determines the latency of the thread


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515

P5P3P1

XGATE runningP1 thread

P6

(Higher numbers have higher priority)



XGATE V2 can handle a single event at a time• Thread execution is not interruptible

� There is no inherent stack support

Pending events wait until the XGATE is free• Waiting events will be taken in order of their priority• This determines the latency of the thread

When XGATE is idle it will respond to an event in a round 100ns

P3XGATE running

c. 100ns


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515



XGATE V3 can handle a higher priority interrupt• Interrupt priority 4-7 can interrupt lower priorities

Once the higher priority is complete the lower prio rity thread resumes

P5XGATE running P5

thread


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515




XGATE

XGATE V3• RAM protection moved from XGATE to MPU• The XGATE core registers are duplicated• Higher priority interrupt swaps to second register set• Swap takes 2 cycles• Ideal for short fast threads e.g. SPI• R7 is automatically loaded with the appropriate stack base address to avoid stack data

corruption (stack base registers must be initialized after reset)


XGATE

XGATE V3• RAM protection moved from XGATE to MPU• The XGATE core registers are duplicated• Higher priority interrupt swaps to second register set• Swap takes 2 cycles• Ideal for short fast threads e.g. SPI• R7 is automatically loaded with the appropriate stack base address to avoid stack data

corruption (stack base registers must be initialized after reset)


XGATE and Memory

The XGATE can address 64k of memoryThe XGATE memory map includes

• 32k of RAM• 2k of peripheral register space• 30k of flash

64k

2k Registers

32k RAM

30k Flash


XGATE and Memory



For embedded MCUs a typical configuration would be to place the program code in flash

2k Registers

32k RAM




}}

30k Flash30k Flash


XGATE and Memory



For embedded MCUs a typical configuration would be to place the program code in flash

This is NOT the optimum solution for XGATEXGATE code is best placed in RAM

2k Registers




}}

32k RAM32k RAM

30k Flash


Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2005

Sharing Memory

CCRCCRPCPCSPSPIYIYIXIX

AccDAccDAccAAccA AccBAccB

CCR (N,V,C,Z)CCR (N,V,C,Z)

PCPCR7R7R6R6R5R5R4R4R3R3R2R2

R1 = Variable BaseR1 = Variable BaseR0=0R0=0

FlashFlashCPUCPU EEPROMEEPROM

RAMRAM

XGATEXGATE

PeripheralsPeripheralstt

pp

00 11 22 33

pp


Sharing Resources

In most applications the XGATE and the CPU must com municate with each other

• Interrupts are used to pass control messages• Data and status must be passed in a controlled manner

� Usually via message buffers in RAM�� Coherency issues can arise if writing and reading i s not coordinCoherency issues can arise if writing and reading i s not coordin atedated

XGATE provides eight hardware semaphores• User software decides on interpretation of semaphores

m m m m m m m m 1 0 1 1 0 0 0 1

Semaphores indicate the availability of shared resource

Semaphore masks allow atomic write access


XGATE – Hardware Semaphores

do{

xgate.xgsem = SETSEM_A(4); /* try to allocate */} while (xgate.xgsem & GETSEM_A(4)); /* Semaphore 4 of 0 .. 7 *//* MUTEX region */

xgate.xgsem = RELEASE_SEM_A(4); /* release semaphore */

00

01

CPU Writ

e

“1_1

”

10

XGATE SSEM

CPU Write “1_0”

XGATECSEM


XGATE – Summary of opcodes available

CSEM, SSEM, NOP, RTS, SIF, BRKOthers

BFEXT, BFINS, BFINSI, BFINSX, BFFOBit stuffing and extraction

BCC, BHS, BHI, BNE, BPL, BVC, BGE, BGT, BCS, BLO, BLS, BEQ, BMI, BVS, BLT, BLE, BRA, JAL

Branch and jump

LSL, LSR, ROL, ROR, CSL, CSRShift & rotate

AND, OR, XNOR, ANDH, ANDL, BITH, BITL, ORH, ORL, XNORH, XNORL, CMPL, CPC, CPCH, NEG, PAR, TST

Logical

ADD, ADC, SUB, SBC, ADDL, ADDH, SUBL, SUBH, SEX

Arithmetic

LDB, LDW, STB, STW, MOV, TFRLoad and store


XGate Instruction set overview

• Operates at 100MHz = 10ns cycle time� 1 cycle for all register – register instructions� 2 cycles for load and store instructions� 2 cycles for branches, if taken, 1 cycle if not

• Fixed 16 Bit Instruction length optimised for � Data movement and logic� Simple fast implementation

• Instructions� Logical (AND, BIT, OR, XNOR)� Multi-bit shifts (LSL, LSR, ROL, ROR)� Bit operations (BFEXT,BFINS, BFFO)� Arithmetic (ADD, SUB)R7R7R7 000151515

R6R6R6 000151515

R5R5R5 000151515

R4R4R4 000151515

R3R3R3 000151515

R2R2R2 000151515

R1 = Variable BaseR1 = Variable BaseR1 = Variable Base 000151515

R0=0000R0=0000R0=0000 000151515

PCPCPC 000151515

CCR (N,V,C,Z)CCR (N,V,C,Z)CCR (N,V,C,Z) 000151515


XGate – Special instructions

BFFO – Bit Field find first one• Useful for priority encoders

PAR parity of a word (calculates # of 1’s in Rd)• Useful for many CRC calculations

N Z V C

SIF – Set Interrupt FlagNOP – For whatever reason each machine needs oneBRK – Software Breakpoint

• halts the XGate for debugging purposes

0 0Z = 1, if Rd = 0C = 1, if # of 1’s in Rd is odd


XGate – Instruction Set Bit-Field

Bit Field Instructions are very useful to extract “signals” from messages or to insert into messages.Format: Rd, Rs1, Rs2

• BFEXT = Bit Field Extract• BFINS = Insert Bit Field, works exactly opposite to BFEXT

� Allows Bit field clear if source is R0• BFINSI = Insert inverted Bit Field

� Allows Bit set if source is R0• BFINSX = Insert XNOR Bit Field,

� allows Bit field toggling if source is R0

7 015 8

w w w w o o oo

offsetw-1

Rs2 = 0x27


XGate interrupt request routing

Interruptsource

(SCI, SPI,...)

Core

XGate

INT controller

......

XGate INTtable

......

ADDRESS

DATA

PC

R1

...

XGate ???.cxgate:voidisr(*data){

...}

The interrupt controller directs the interrupt request either to the core or to the XGate. The new priority scheme allows flexible prioritization of interrupts.The behaviour is typically configured statically during application start-up, but can be also changed during run-time based on load and other parameters.


XGate interrupts – where is what in a project?

Interruptsource

(SCI, SPI,...)

Core

XGate

INT controller

......

XGate INTtable

......

ADDRESS

DATA

PC

R1

...

XGate ???.cxgate:voidisr(*data){

...}

xgate_vectors.cxgate:xgate_vector XGateVectorTable[] = {

...{isr, &isr_data},...

}

The XGate interrupt vector table contains two 16-bit entries per interrupt source (address of the service routine and a 16-bit value passed to the routine in register R1).The 16-bit value from the table is treated as a parameter of the interrupt service routine on C code level.


XGate – Concerns about Code in RAM

Configurable RAM protection schemeXGate detects many errors like

• Code or vector fetches outside allowed memory space• Code or vector fetches from peripheral space• Illegal opcode• Illegal misaligned word accesses

Halts and flags those errors to the CoreXGate can run a checksum on its own code spaceCore can run consistency checks between Flash and RAM code

space.


CAN Mailbox System

Creating a virtual CAN mailbox using XGATE

RxBuffer

RAMRAM

Interrupt

Move messageMove message

Interrupt

msCAN module


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515



CAN

message

XGATEXGATE

CPUCPU

Retrieve message


CAN Mailbox system

All drivers written in C

Performance of XGATE code at 40MHz clock• CAN transmit

� Code size 138bytes� Execution time 1.5µs

• CAN receive� Code size 130bytes� Execution time (first mailbox matches) 1.3µs� Execution time (no mailbox matches) 3.5µs




}}


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515


S12X/XGATE的编程实例的编程实例的编程实例的编程实例1：：：：串口通信程序串口通信程序串口通信程序串口通信程序

中断控制器的配置中断控制器的配置中断控制器的配置中断控制器的配置

01101011SCI0中断向量：0xD6

00001011

00000000

00000000

00000000

00000000

00000000

00000000

00000000

10000001

…

SPI0

SCI0

SCI1

…

中断请求配置地址

XGATE INT: RQST=1

INT LEVEL: ILVL=001

#define ROUTE_INTERRUPT(vec_adr, cfdata) \INT_CFADDR= (vec_adr) & 0xF0; \INT_CFDATA_ARR[((vec_adr) & 0x0F) >> 1]= (cfdata)

… …#define SCI0_VEC 0xD6 /* vector address= $xxD6 */… …ROUTE_INTERRUPT(SCI0_VEC, 0x81); /* RQST=1 and PRIO=1 */

中断请求配置数据

TM


Virtual Peripherals


Virtual peripheral

The meaning of a virtual peripheral in this context is…

A function not existing in hardware that is created in software running on 1 CPU and perceived by the other CPU

as a hardware peripheral.“无中生有无中生有无中生有无中生有”

Or…

A function not existing in hardware that encapsulates a hardware peripheral enhancing the functionality by software in 1 CPU,

perceived by the second CPU as a hardware peripheral.“增值包装增值包装增值包装增值包装”


Virtual peripheral examples

Software peripherals example.• TFT display driver• Gateway• Soft PWM or complex timing generation.• Soft UART or proprietary serial protocol driver

Encapsulated hardware peripherals, example• LIN master driver• Mailbox CAN


Software peripheral TFT display controller

Image Image DataData

Frame Frame BufferBuffer

Scene Scene descriptordescriptor

FLASHFLASH

CLUTCLUT

RAMRAM

S12XCPUS12XCPU XGATEXGATE GP

IOG

PIO

16 bit RGB

VSYNC/HSYNC

CLK

S12X family MCUS12X family MCU


CAN Mailbox System

Creating a virtual CAN mailbox using XGATE

RxBuffer

RAMRAM

Interrupt

Move messageMove message

Interrupt

msCAN module


PCPC 001515

R6R6 001515

R6R6 001515

R5R5 001515

R4R4 001515

R3R3 001515

R2R2 001515


R0=0R0=0 001515



CAN

message

XGATEXGATE

CPUCPU

Retrieve message


Documents

S12 XE Course Notes - pudn.comread.pudn.com/downloads120/doc/project/511545/S12XE_Training.pdf · CPX CPY DAA DBEQ DBNE DEC DECA DECB DECW DECX DECY DES DEX DEY EDIV EDIVS EMACS EMAXD