S6, iNEMISession: Modeling & Simulation in Electronics Packagingthor.inemi.org/webdownload/2019/IMPACT/S06-4_elec_anal... · 2019. 11. 8. · S6, iNEMISession: Modeling & Simulation

S6, iNEMI Session: Modeling & Simulation in Electronics PackagingTOPIC: SYSTEM-LEVEL POSTLAYOUT ELECTRICAL ANALYSIS FOR HDAP REPORTER: Dusan Petranovic

AFFILIATION: Mentor, a Siemens Business

Email: [email protected]

Paper Code: TW001-1Date: Wed, Oct 23, 2019

Taipei, October 2019

mailto:[email protected]

OUTLINE1 INTRODUCTION2 EDA CHALLENGES IN DESIGN, MODELING AND PEX

- 3DIC configurations and components - EDA challenges in design, modeling and parasitic extraction

3 MENTOR’s PHYSICAL VERIFICATION FLOW- Heterogeneous Assembly Verification- Verification Flow: XSI, 3DSTTACK and PEX

4 PARASITIC EXTRACTION SOLUTIONS - TSV and Back Side Metal Layers Extraction- TSV Couplings – Analog and Digital Flow- Extraction Solutions for Various Configurations- Mentor Interface PEX Flow- Static Timing Analysis Flow for HDAP

5 INDUCTIVE COUPLING ANALYSIS

6 CONCLUSIONS Taipei, October 2019

EDA CHALLENGES IN DESIGN, MODELING AND PEX

• 3D Configurations and Components• EDA Challenges in Design and Modeling• EDA Challenges in Parasitic Extraction


2.5D/ 3D Configurations and Components


Interposer

3D 2.5D FOWLP

TSVs- on chip- on interposer

Back sidemetal stack

Interface:- micro bumps, pillars- direct Cu bonding

dies, interposers, package

Die 1 Die 2

Mold

FOWLP

Die 1 Die 3 Die 3Die 2Die 1

Die 2

EDA Challenges in Modeling and Design of 3D Stacks• Modeling

– Different phenomena: electrical, thermal, mechanical;– Interaction modeling– Tradeoff between needed accuracy and model complexity and flow integration– Consistency between different levels of abstraction

• Design & Verification– Design exploration/optimization tools, managing interactions and controlling parametric yield– Cross-domain integration

• ICs, Interposer, Package , Board

– Work on resolving issues related to multiple disconnected tools with no standard methodology/flow to synchronize and transfer design data between design disciplines and abstraction levels


IC

PackagePCB

Time to Market

Effo

rt

EDA Challenges in 3D Stack Parasitic Extraction

• Parasitic Extraction– What to extract – What interactions are important

– Intra- die• TSVs• TSV - to -TSV• TSV - to - RDL• TSV- to –Device ?

– Inter-die• F2F and F2B bonded dies

(WoW, DoW)• FOWLP

(Die to Package)– What level of accuracy is needed ? Taipei, October 2019

TSV

Devices

Back Metal

Front Metal

Substrate

Error might be significant if dies interactionsare not taken into account

Error if TSV to RDL not taken into account

F2F bonded dies

TSVTSV

TSV couplings have to be extractedespecially in Interposer

MENTOR VERIFICATION FLOW

• Heterogeneous Assembly Verification• Verification Flow: XSI, 3DSTTACK and PEX


Heterogeneous Assembly VerificationCalibre 3DSTACK & Xpedition Substrate Integrator

Source SystemNet list

Assembly Description

Files

Xpedition® Substrate Integrator

Heterogeneous system assembly and visualization

Import source design content to define system assembly and automatically

generate decks to run Calibre 3DSTACK

IndividualDie Data

Interposer Data

PackageData

DRC/LVS of completepackage assembly

Calibre® 3DSTACK

Final assembly sign-offand verification


Verification Flow for Post-layout Electrical AnalysisXSI, 3DSTACK and PEX

Physical Verification

§ Verify micro-bumps physical alignment

§ Verify proper logical and physical connectivity

§ Generate system level netlist

Parasitic Extraction§ Extract parasitics of the dies (front and back side metal stacks)

§ Extract the die interfaces/interactions (F2F, F2B)

§ Insert provided TSV circuit into integrated parasitics/TSV netlists

§ Extract Interposer TSV to TSV couplings Taipei, October 2019

Die 1

Die n

Package

Source Netlist

Layout Assembly

Netlist Formats Conversion

Checking

Calibre 3DSTACK

Assembly GDS

Results

Assembly Source/layout

Netlist

Designer Supplied OSAT Supplied

Die Description

PackageDescription

StackingDescription

AssemblyChecks

Xpedition® Substrate Integrator

Heterogeneous planning, prototyping & optimization

Automatic generationof system netlist

Automatic generationof 3DSTACK files

PARASITIC EXTRACTION SOLUTIONS

• TSV and Back Side Metal Layers Extraction• TSV Couplings – Analog and Digital Flow• Extraction Solutions for Various Configurations• Mentor Interface PEX Flow• Multi-Component Static Timing Analysis Flow


TSV and Back Side Metal Layers Extraction


• TSV circuit insertion and Back side metal extraction

• Output– Compete netlist generated, with TSV sub-circuit inserted and back side

metal stack parasitics extracted

• TSV to TSV Couplings

• Output – The couplings between the TSVs inserted in the netlist

Csub

Rsub

R1C C

M1

MBMB

M1

R1

R2 R2

CeffM1

MB

M1

MB

Description of TSV and the back side metal in MIPT

tsv = TSV {start_layer = MBstop_layer = M1radius = 1.23639}substarate = psub {zbottom = -50ztop = -0.7resistivity = 10180eps = 11.9dielectric = ILD {diel_type = planareps = 3.9Thickness = 0.127conductor = MB {thickness = 0.85min_width = 0.36min_spacing = 0.36extra_width = 0.08………….

.subckt TSV top botR1 top mid 5555R2 mid bot 5555C mid sub 7777.ends

Csub and Rsub tables provided, as a function of TSV spacing

Ceff table, as a function of spacing and frequency

xACT measures the distance between the TSVs

Analog Digital

0 / sub

M1

MBR2

R1 C

top

mid

bot

TSV

Devices

Back Metal

Front Metal

Substrate

R1180 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:58 5555 $X=542.5 $Y=582.5 $X2=542.5 + $Y2=589.0R1153 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:67 5555 $w=1.4e-05 $layer=metal1 + $X=542.5 $Y=582.5 $X2=542.5 $Y2=589.0Cc_1481 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:96 7777f $X=542.5 $Y=582.5

Long TSV extraction

• In some 3DIC configurations TSV goes from the back side metal to upper metal layers

• Going through the substrate and metal stack• Need to

– Insert provided TSV circuit– Extract TSV to metal stack couplings– Netlist the couplings at TSV top and/or bottom


2R+1C model

TSVextract

netlist

TSV Couplings – Analog Flow

• In order to extract couplings (i.e. to read the Rsub and Csub values from a provided tables), the following statement has to be used: PEX 3DIC COUPLING TSV ANALOG MAXDISTANCE 300

table = Csub { property = tsv_capacitancetable_type = Cdim_type = drawnvalue_type = absolutespacing = { 68 78 88 98 108 118 128 138 148 158 168 178 188 198 208 218 228 238 }value = { 41.60 36.24 31.88 28.32 25.43 23.07 21.15 19.58 18.30 17.26 16.42 15.73 15.17

14.71 14.34 14.03 13.79 13.58}

table = Rsub {property = tsv_resistancetable_type = Rdim_type = drawnvalue_type = absolutespacing = { 68 78 88 98 108 118 128 138 148 158 168 178 188 198 208 218 228 238 }value = { 1220.00 1307.06 1393.66 1478.54 1560.48 1638.34 1711.18 1778.29 1839.21

1893.75 1941.96 1984.08 2020.49 2051.69 2078.20 2100.57 2119.34 2135.00}

Csub

Rsub

R1C

C

M1

MBMB

M1

R1

R2R2

R1153 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:67 5555 $w=1.4e-05 $layer=metal1R1180 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:58 5555 $X=542.5 $Y=582.5 $X2=542.5Cc_1481 TEST_SI_DIE1[14]:52 TEST_SI_DIE1[14]:96 7777f $X=542.5 $Y=582.5Cc_2104 TEST_SI_DIE1[8]:107 TEST_SI_DIE1[4]:117 16.42f $X=182.5 $Y=764.875Rc_1483 TEST_SI_DIE1[14]:96 TEST_SI_DIE1[18]:111 1941.96

Calibre xACT measures the TSV-to-TSVdistances and reads the tables for Rc and Cc


TSV Couplings – Digital Flowtable = tsv_capacitance_eff {

property = tsv_capacitancetable_type = Cdim_type = drawnvalue_type = absolutefrequency = { 5.0000000E+07 7.3684210E+07 9.7368420E+07 1.2105263E+08

1.4473684E+08 1.6842105E+08 1.9210526E+08 2.1578947E+08 2.3947368E+08 2.6315789E+08 2.8684211E+08 3.1052632E+08 3.3421053E+08 3.5789474E+08 3.8157895E+08 4.0526316E+08 4.2894737E+08 4.5263158E+08 4.7631579E+08 5.0000000E+08 }

spacing = { 68 78 88 98 108 118 128 138 148 158 168 178 188 198 208 218 228 238 }

value = {2609.53 2435.61 2284.25 2153.07 2039.92 1943.05 1860.26 1790.07 1730.79 1680.89 1639.17 1604.38 1575.48 1551.52 1531.74 1515.4 1502.03 1490.98 ,1770.89 1652.99 1550.14 1461.11 1384.41 1318.58 1262.47 1214.76 1174.53 1140.72 1112.35 1088.74 1069.13 1052.87 1039.44 1028.36 1019.28 1011.79

In order to extract couplings (i.e. Ceff values from a provided table), the following statement has to be used:

PEX 3DIC COUPLING TSV DIGITAL 7.3684210+07 MAXDISTANCE 500FREQUENCY

CeffM1

MB

M1

MB

*CAP………………..23 *31:88 *31:22 7777

24 *31:22 *30:17 1.11235e+0625 *31:22 *33:20 1.01179e+0626 *31:22 *34:24 1.01179e+06


Extraction Solutions for Various Configurations• Fan Out Wafer Level Processing (FOWLP)

– Combination of Calibre xACT and Hyperlinx• Calibre xACT for the Dies• HyperLinx for the package like layout• Calibre xACT used for interface extraction

• Wafer on Wafer stacking (F2F and F2B)– Die Back side parasitic and the TSV circuit insertion– TSV to interconnect couplings in “long TSVs” – Interposer TSV circuit replacement and TSV-to-TSV coupling– Die to die couplings Face-to-Face (F2F) and

Face-to-Back (F2B)– Support both GDS and LEF/DEF flows


die1 die2

F2F

F2B

TSV

die 3

die 1

die 2 TSV

Interposer

Die Interaction Extraction§ Two methodologies:

• “in-context” extractions• separate interface extraction

“in-context extraction” “separate Interface extraction”


gnd

gnd

die_2

die_1

gnd

PV

PVPL PLinterface

This approach extracts the interface, the coupling between the dies, as well as an impact of the dies on each other’s intra-die parasitics.

Not as accurate as “in-context” extraction but more convenient - if the SPEFs of the dies already available- extracts only the interface with annotated GDS, not the entire die

F2F

F2B

TSV

die3

die1

die2 TSV

Avoiding double-counting of the parasitics


Ignore same die layer couplings in interface extraction Pad_Die1

Mtop_Die2

Mtop_ Die1

Pad_Die2

PEX IGNORE CAPACITANCPEX IGNORE CAPACITANCE ALL SUBSTRATE Mtop_Die1 Mtop_Die1 Pad_Die1 Pad_Die1PEX IGNORE CAPACITANCPEX IGNORE CAPACITANCE ALL SUBSTRATE Mtop_Die2 Mtop_Die2 Pad_Die2 Pad_Die2

The top layers of the dies are extracted in individual die extraction as well as in the interface extractionNeed to avoid double counting of the capacitances

Chip on Wafer and Chip on Chip


TDV

Interconnect

Die3

Die2Die1

Routing has 45 deg segmentsRCLK extraction needed

Need to extract TDVs and Interconnect that connects the dies

Extract interconnect approximating Die1 and Die3 with the ground plates

Mentor Interface PEX FlowExamples: FOWLP and WoW (F2F and F2B bonded dies)

RUN 3DSTACK..

. .

. .. .

. .. .“Step 1”

RUN xACT ..“Step 2”

• For this flow, 3DSTACK calls “xcalibrate” under the hood– “xcalibrate” license is required


Component-nMIPT

Component-2MIPT

Component-1MIPT

Component-nDB

Component-2DB

Component-1DB

3DSTACK Deck MIPT/IRCXLayer Names

Interface -1AGDS

Interface -2AGDS

Mini LVS Deck-1 Mini LVS Deck-2

xACT SVRFstatements-1

xACT SVRFstatements-2

Interface- 1 RC rules

Interface- 2 RC rules

Interface- 1 SPEF

Interface- 2 SPEF

Interface- n SPEF

Mentor STA Flow for Multi-DieExample: FOWLP Extraction


Mentor STA Flow for Multi-DieExample: W2W Extraction

Parasitics of the Interface (couplings between dies)Ignore Die Same Layer Couplings

Annotated GDS of the Interface

Rules for Interface Extraction

MIPT of the dies, with Interface Info

LEFDEF of the diesOr GDS of the Dies

(with Interface)

SimulationDigital (PT,…)

Analog (Spice…)

Interface Netlist SPEF, SPICE,…

Needed LVS statements“mini LVS”

Generated by XSI Dies 1 Verilog

Die 2 Verilog


Calibre 3DSTACK Calibre xACT

xCalibrateRules for the Dies Extraction

Verilog of the Interface (VB)

TopVerilog

Dies Netlist SPEF, SPICE,…

TSMC 3DIC Reference Flows - Qualified• InFO Ref. Flow 2.0, Qualified

– Combination of Calibre xACT and Hyperlinx• Calibre xACT for the Dies and interface extraction• HyperLinx for the InFO

• CoWoS Ref. Flow 2.0, Qualified– Extracted by Calibre xACT– Focus on back-end metal – TSV circuit insertion and table based TSV coupling

• WoW Ref. Flow 1.0, Qualified– Extracted by Calibre xACT– Interdie coupling (F2F and F2B) – TSV circuit insertion for on die TSV

• InFO-mS Ref. Flow 1.0, Qualified– Extracted by Calibre xACT– Die-InFO couplings

• SoIC Ref. Flow 1.0, Qualified– Multi-Ground support– TSV to metal stack couplings– RCL extraction for non-Manhattan layout

• InFO_LSI , Flow 1.0 Qualified– RLCK extraction of nonManhatan LSI layout– SI analysis with selected net extraction


die1 die2

INDUCTIVE COULING ANALYSIS

• Coupling noise analysis


Inductive Coupling Analysis• Most discussions/solutions are related to components capacitive coupling• How about inductive coupling? • Magnetic coupling is long range and there is a strong possibility that there would be some impact of the

components on each other • Induced inductive noise is proportional to a product of mutual inductance and change of current

Induced voltage (cross-talk) –

• If current is high and changes fast, di/dt is high, there is a chance for inductive noise to be significant even for modest M.

• Performed some analysis for FOWLP technology


dtdiMv =

• PP35 and PP42 are on the AP layer (die) and PP6, PP46, PP34 on the RDL1Coupling noise analysis


PP35

PP42

PP46

PP6

PP34

RDL1RDL1&AP AP

Green wires/mesh is GND

die FO-routing

die1 die2

• PP35 as victim, all other 4 nets as aggressor• No inductive coupling;

Capacitive Coupling Noise (With RDL1 layer, RC)

Peak noise:3mV


• PP35 as victim, all other 4 nets as aggressor, 2GHz random input

Total Coupling Noise (With RDL1 layer, RCLK)

Peak noise:94mV


• PP35 as victim, only PP42 as aggressor, No other signals (RDL --PP6,P46,P34)

Coupling Noise (Without InFO)

Peak noise:19mV


CONCLUSIONS• 3D stacking is reality

– Lot of recent activities – Various configurations, strategies and business models

• Parasitic Extraction is Important– Accurate extraction is needed for realistic simulation of the designed circuit– System level netlisting and simulation

• Mentor has comprehensive 2.5D/3D IC PV and PEX solution – 3DSTACK for LVL and LVS and system level netlist– Intra-die (TSVs, TSV-to-TSV, TSV-to-RDL) – Inter-die (micro-bumps, Interfaces, coupling parasitics)– Component interaction modeling

• Collaborative partnerships are crucial – Design House – EDA – Foundry/OSAT - Academia– Early cooperation eliminates redundant efforts and improves TTM– Results in timely, differentiating solutions


The EndThank you!IMPACT 2019

Oct 23 (Wed) – 25 (Fri)Taipei Nangang Exhibition Hall


Documents

S6, iNEMISession: Modeling & Simulation in Electronics Packagingthor.inemi.org/webdownload/2019/IMPACT/S06-4_elec_anal... · 2019. 11. 8. · S6, iNEMISession: Modeling & Simulation