Sandip Tiwari [email protected]/files/nanoelectronics... · 2009. 2. 11. · C High Abstraction (HDL) 10-6 Device Boltzmann Compact ASX, Spice, … Lumped

(Silicon) Nanoelectronics:(Silicon) Nanoelectronics:From Devices to Systems

Sandip Tiwari [email protected]

A discussion of electronics and some of its devices and circuits with h i l ff t i th t t f li ti demphasis on nanoscale effects in the context of applications and

systems

Short Course, NanoSingapore, 2006

Introduction

Background on electronics and CMOS devices

Nanoscale in Silicon

Nanoscale in Other Materials

Nanoscale Devices

Circuits and Systemsy

Systems, Hierarchy and Architecture

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 2

Electronics

109

P3P4

Itanium 2Madison

108

7

286386486DX Pentium

P2

P3107

106

105

Avg. increase4004

8086

28610

104

103

Moore's Law - Transistors per Chip

g

of 57%/year10

102

10

F d ti f t illi d ll i f ti i d t ll f t & h ft

Intel µP1

1950 1960 1970 1980 1990 2000 2010

10


Foundation of a trillion dollar information industry: smaller area, faster & cheaper year after year: Moore’s LawLemma: An industry that works hard and spends billions at putting itself out of business

Electronics

100 PhysicalBehavioral

Structural

ContinuumHi h Ab t ti (HDL)

10-3

Chip Floor Planning

PlacementTiming

C

High Abstraction (HDL)

10-6

DeviceBoltzmann

CompactASX, Spice, …

Lumped

CongestionRouting

VerificationTemperature

PSca

le (

s)

10-9HydrodynamicDrift-DiffusionMonte CarloAtomistic

InterconnectNoise

PowerElectromagnetic

Tim

e S

10-12 QuantumMaster Eq.NEG


10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 1 101 102 103

10-15

Length Scale (m)

What makes an electronic systemLogic

L i ti L i i t f i (d i b i t f )Logic execution, Logic interfacing (drivers, bus, interface, …)

Memory

Cache, Data, Code, Storage, …(dynamic and non-volatile, … fast and slow)and slow)

Communication

On and off chip to other chips, boards, …

InterfacesInterfaces

Display, touch, sound, keyboard, sensors, other input/output

Hierarchical system design


Bulk Transistor

We want:

High on current Ion

Low off current Ioff

Rapid control between pthe two states

ideal is 0 mV

practical is 60+ mV for a d d h idecade change in current

Reproducible

Low sensitivity toLow sensitivity to variations

Low energy


Electron Transport in FET

Sourcce

Gate

SiliconSubstrate

Drrain


Transistor

(A)

Charge confinement (doping)Mobility and effective velocity

VDS (V)

I D

ResistancesDoping and conductivity

g I D

(A)

(A)

Mobility

Charge confinement

VGS (V)

Log

I D Charge confinementGate control

VT

(V)

Charge confinement (doping and body)Gate control


Log Lg (nm)

V

Scaling

Voltage V/αOxide tox/αWi Width W/

Device Density

~α2

Wire Width W/αGate Width W/αDiffusion Xj/α

Speed ~αPower/Ckt 1/α2

Power 1


Substrate doping

αNA

Power Density

1

Nanoscale

IBM T K d


Scaling doesn’t quite work below 100+ nmIBM T. Kuroda

Power


F. Pollack, Intel


T. Sakurai

Power

Source: B. YuSource: IBM

Passive power increasing at rapid rate due to gate and inter-junction leakage


Dielectrics and junctions with increasing tunneling

SOI MOSFET

⎥⎦⎤

⎢⎣⎡ −−= 2

2

1)( DDThGoxD nVVVV

L

WCI μCurrent:

⎦⎣2

21 )( ThGL

WoxnDSat VVCI −= μSaturation Current:

)10(lnq

kTnS =

WC2

Subthreshold Swing:

L

W

nI

C

I

g

D

ox

D

m μ2=Transconductance:


n: body factor that emphasizes the strength of gate to channel coupling

Body Factor: Strength of Gate to Channel Coupling

CoxGate

Cox

CJCSi

CSi

CBo

Source Drain

CJ CJ CJCBox

Bulk: n ~ 1.5 Fully Depleted: n ~ 1.1

Body factor for different designs – partially depleted, body contacted, dual gates, … varies, but all lead to reduction, g , ,

Reduced junction capacitances with SOI

Judicious SOI design leveraging these two important consequences of insulator underneath permit reduced power for


consequences of insulator underneath permit reduced power for similar speeds (reduced voltage, ..)

SOI: Characteristics

10-6

10-5

10-4

10-3

/µm

)

Vds

= 0.1 V

Vds

= 1.8 V

200

250

300

A/µ

m)

Dashed line: fully-depletedSolid line: partially-depleted

1

0 7

10-10

10-9

10-8

10-7

Dra

in c

urre

nt (

A/

NMOSFETDrawn length: 0.25 µm

80 mV/decade

68 mV/decade

100

150

200

Dra

in c

urre

nt (

µA

Vgs

- Vt ( V)

0.4

0.7

Kink effect

10-13

10-12

10-11

-0.5 0 0.5 1 1.5 2Gate-to-source voltage (V)

Dashed line: fully-depleted Tsi

= 35 nm

Solid line: partially-depleted Tsi

= 100 nm

0

50

0 0.5 1 1.5 2

D

Drain-to-source voltage (V)

0.1

Bias, time and frequency dependence from floating body + bipolar activation via generated chargeg g

Weaker in fully depleted

Design techniques exist for time dependence

Heating effects from poor thermal conductivity (κ)

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 16Source: O. Faynot

Heating effects from poor thermal conductivity (κ)

SOI: Characteristics

Floating body and bipolar activation via generated chargeBias-dependent effectsTime-dependent effectsTime-dependent effectsFrequency-dependent effectsFully depleted structures have smaller effects

Frequency dependence is a bigger problem


q y p gg p

Heating effects from poor thermal conductivity (κ)Source: O. Faynot and Y C Tseng

Interconnects: 2D

obab

ility

Pro

LocalFringing & Coupling

Capacitances

0 5

Capacitances

Technology scaling occurs with increasing average interconnect length and routing density and increased interconnect aspect ratio

Wire Length (unit of die-size)0.5

Global

Interconnects grow linearly with cells in ordered arrays (memories, e.g.)

Interconnects grow as the square of the elements in random logic

Local (intra-block) wires scale with block size, but global (inter-block) i d t Gl b l i i d i i b ff b i i l


wires do not. Global wiring and increasing buffers become an increasingly problem

Throughput & Power Dissipation in Buffers

Driver Receiver

Source: Deodhar et al.180 nm technology

Use of repeaters means more power, and absence means increased delays with global delays more dominant


In 65 nm high speed designs, the # of buffers is ~850KMore area, power and congestion

Clock Span

Increasing fclk and speedReduced logic span


Reduced logic span

Higher electromagnetic coupling: capacitive coupling inductive bounce

Source: Saraswat

Power Dissipation in Small Dimensions & Temperature

105 W/cm2 => 100 C with package at 50 C at 0.18 μm dimensionArea in which this dissipation occurs critical to temperature

Li t l IEEE EDL (2002)Liu et al., IEEE EDL (2002)

110

120

130 3D: 5μm SOI: 200nm BOX 3D: 1μm under driver

and 5μm elsewhere Bulk CMOS

130

140

150

160

80

90

100

110

mpe

ratu

re (

oC

)

90

100

110

120

mpe

ratu

re (

oC

)

50

60

70

80

Tem

50

60

70

80

90

Tem


103 104 105

50

Power density (W/cm2)

10050

50 500

Driver pitch (μm)

Energy determines density forEnergy determines density for electronic nanosystems


Consequences of Improving Electrostatics

Higher body doping Lower carrier mobility

Higher junction capacitance

Higher junction leakage

Thinner gate dielectric Higher leakageg g g

Shallower junctions Higher resistance


Statics and Dynamics

Electrostatics

Gate ControlGate dielectrics, work-functions, …

SubstratesSharp halo’s and improved junctions

Thin silicon bodies

ThresholdWork functions, doping, new geometries

Electrodynamics

TransportStrained materials (Si, SiGe, …), new orientations, new materialsStrained materials (Si, SiGe, …), new orientations, new materials (Nanotubes, Ge, III-V, …)

ParasiticsNew contact materials, raised source-drain structures, etc.


New contact materials, raised source drain structures, etc.

Non-Classical CMOS (Single Gate)

Transport enhancement Substrate Enhancement:Thin Body

Source/Drain Enhancement

Strained Si, Ge, SiGe, SiCGe, …on b lk Si & SOI

Fully depleted SOI with sub-10 nm body or ultra thin channel

Low barrier Schottky source/drain or non-overlapped


bulk Si & SOI or ultra-thin channel and buried oxide

overlapped extensions

Source: ITRS

Non-Classical CMOS (Multi-Gate)

Tied Gates

Ch l

Vertical transistor

Channels on multiple surfaces

Channels on id ll Independent gatesd i

gate

side-walls Independent gatessource drain

Channels on planar surfaces

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 26Source: ITRS

Planar Transistors

Bulk Silicon on Insulators: Various Forms

Scaling limited Scaling limited Enhanced scaling limits if

Enhanced scaling limits if

Enhanced by Si/SiGe channels

But improved performance that can be enhanced by

thin silicon and low parasitics feasible

thin silicon, two gates and low parasitics feasible


enhanced by bulk-like approaches

feasible

Strain by Orientation


Yang et al. (2003)

Transport Improvement by Orientations

Bond (110) onto (100) Si – oxide basedbasedUse epitaxy of 100 with oxide isolation for (110)


Yang et al. (IBM)

Strain

Reduced average conductivity mass

Reduced inter-valley scattering

Higher effective bilit


mobility

Takagi (2003)

Strained Si

Strained Si on SiGe

Mobility Enhancements with Silicon(strained) on Insulator


K. Rim (IBM)Oxidized Si

Strain


Source: Intel

Strain by Process

Uniaxial Strain


Thompson et al. (2004)

High k (Permittivity)

HfO2/SiON

HfO2 has x104 less leakage than equivalent SiO2

But large interface state issues


Gousev et al. (IBM)

But, large interface state issues

Combinations

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 35Rim (IBM)

To date, mobility degradion with high permittivity materials is substantial

Work Functions

NMOSAl: 4.13eV

Dual Metal

Ev

n+ poly SiGe n+ poly Si 4.05

eV

5.17

eV

4.61

eV

Ec

Al: 4.13eVTa: 4.19eVMo: 4.45eVTi: 4.14eVHf: 3.9eV

Single Metal

MidgapW: 4.52eVn+ poly SiGe

p+ poly SiGe

n poly Si c Hf: 3.9eVTaN: 4.05eVNb: 4.15eV

W: 4.52eVRu: 4.68eVCo: 4.45eVCr: 4.5eVPd: 4.9eVp+ poly SiGe

p+ poly Si Ev PMOSRuO2: 4.9eVIr: 5.35eV

Pd: 4.9eVWNx: 4.6eVTiN: 4.7eVTiSi2: 4.5eVNiSi: 4.9eV

Pt: 5.65eVWN: 5.0eVMo2N: 5.33eVTaN: 5.43eVNi 2 V

NiSi: 4.9eV


Ni: 5.2eV

Niwa IEDM (2000)

FinFet


Thin Si


Majkusiak (1998)

Adaptive Transistors

GateSiO2 SiO2

rce

n

Si Channel

GateSiO2 SiO2

Source DrainSi Channel

Back Gate

Sou

r

Dra

i

Back Gate

SiO2

SiO2Si Substrate


Lin et al. (2005)

Dual Function: Logic and Memory

Charged floating back gate

1E 6

1E-5 Memory windowg

1E-9

1E-8

1E-7

1E-6

A/μ

m)

window with varying back potential/

increasing

floating back gate

1E-12

1E-11

1E-10

1E 9

ID(VBG=-2.000) => Probe lifted ID(VBG=-1.500) => Probe lifted ID(VBG=-1.000) => Probe liftedID(VBG 0 500) P b lift d

I DS (

A

VDS

=1 V

potential/charge

back gate bias-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

1E-13

ID(VBG=-0.500) => Probe lifted ID(VBG=0.000) => Probe lifted

VFG

(V)

Multi-function structure – provides memory, tunable transistor function, and configurable switch

Memory window with x106 change in current/resistance

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 40Avci and Tiwari, El. Letters (2004)

Transport in Thin Silicon

5 8 nm

Front Gate

Front Oxide

Universal Mobility

5.3 nm

7 0 nm

5.8 nmFront Oxide

Silicon

Back Oxide

FG

BG+++

---

Si Channel

7.0 nm

Back Gate

Back Oxide

Back InvertedFront Accumulated

C a e

Si

F

SiSiBSiFBF

FBBBGFBFFGoxBoxFoxBFfronteff

Q

tCCCCCC

VVVVCCCQE

ε2

1.

)(+⎟⎟

⎠

⎞⎜⎜⎝

⎛++

+−−+=−

VBG Increasing

Ch di t ib t d

-3.0 V < VBG < 3.0 V Good electron transport still maintained in thin silicon

SiSiSioxBSioxFoxBoxF tCCCCCC ε2⎠⎝ ++


Charge distributed across silicon

A. Kumar, et al. (2005)

maintained in thin silicon

Thin Si

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 42Uchida et al., IEDM (2004)

Nanoscale in SiliconNanoscale in Silicon


Quantum Effects

QuantizationQuantumS itiQuantization Superposition

Uncertainty Principle

W ti l d lit

Tunneling


Wave particle dualityInversion Layer

Nanoscale Classical Picture

Achieving quantum confinementQuantum wells (2D)

Q t i (1D)Quantum wires (1D)

Quantum dots (0D)

S(E

)

n(E) n(E) n(E)

DO

S

E

n(E)

E

n(E)

E

n(E)

EE E E E

3-D 2-D 1-D 0-D


Confinement & Degeneracy

Degeneracy capacitance is non-geometrical

does not scale with layerdoes not scale with layer thicknesses.

Constant in 2-D (single subband occupancy)

L i Si b f llLarge in n-Si because of valley degeneracy and large effective

C2D = 4 π nν e2 m/ h


Solomon & Laux, IEDM 2001

Limits

Classical (semi-) physics has sufficed to date

Behavior changes when electron-wavelength approaches device di idimensions

Few-electrons per device questions

quantization perpendicular to transport with confinement-energy penalties in threshold voltage control and transportpenalties in threshold voltage control and transport.

wave function penetration in transport direction introduces tunneling leakage in off-state

( )∫ dα2e pconflicting requirements between low mass for transport vs. tunneling.

Statistics of small numbers of impurities limit reproducibility of

( )∫− dxα2exp

Statistics of small numbers of impurities limit reproducibility of small devices

Timing fluctuations, even though above the threshold electron individuality is lost


individuality is lost

Related to timing, energy and power limits

Nanoscale: Power and Performance

Suppose we could make devices at a 10 nm x 20 nm minimum dimension with a cell size of 50 nm x 60 nm (3.3 x 1010 cm-2)

A d li it th d it t 100 W/ 2 d 1 VAnd, suppose we limit the power density to 100 W/cm2 and 1 V supply

If all elements were continuously switching the average power per device is 3.33 nW/device at 6 nA/device, or 1 electron transiting every 27 ps (TOO SLOW)

Present digital design handles this by partitioning functions and allocating power according to speed desired: clocks high and cache low

Needs multiple threshold voltages and a variety of circuits

Temperature of 100 C (50 C package) in an isolated small element implies current of <0.5 μA


An Electron in a Semiconductor

Unhindered movement of a single electron is μA’s of current

However, to observe it, requires constraints (barriers, e.g.) and the current drops – typically nA

A 10 nm x 10 nm x 10 nm cube of silicon has ~50 available states in ~1 eV of energy range

Variance of an ensemble of n that follows Poisson distribution is n/1

Mean free path of a hot electron is 5-40 nm


Discreteness


Frank et al. (2000)

Quantum Dots – Single Electron Effects


Charging Effects

Charging of a small particle with an extra electron requires an

S De

an extra electron requires an energy: EC = e2/2CΣ

A small particle (~10 nm) in a

G

p ( )dielectric (SiO2, e.g.) has CΣ=2 aF, EC = 40 meV ~150 C

Observations by Neugebauer andObservations by Neugebauer and Webb (1962), Zeller and Giaver (1969) and Lambe and Jaklevic (1969)


Fulton and Dolan (1987)

Coulomb Blockade and Staircase

Blockade: no current flow until an electron can charge the particle

ergy

SymmetricCoulombOscillations

BarrierS D

El.

En

e

z I

VGS

G

Staircase: When particle charged by > 1 electron

GS

1 el.

2 el.

Blockade Staircase

I


VDS

Impedance, Currents and Size Effects

For a clear observation of Coulomb blockadeSystem energy change much larger than eigenstate width (which is related to lifetime of state/tunnel escape rate)related to lifetime of state/tunnel escape rate)requires RT>> h/2πe2 or 4.1 kΩIn real structures, R is typically GΩ

⇒ Poor Gains (Power and Voltage) and Impedance mismatch⇒ Time constants (RC) of ns and currents of nA

Size has significant effect through charging energyEc ~1/C and ΔEc/Ec ~ΔL/L

Size has significant effect through subband energySub-band Energies: ΔE0~1/L2 and ΔE0 ~2 ΔL/L


Single Electron Transistor

n = 0

Vt

e/CΣ

n = 1n = -1

Vg gateQ0 = CgVg

-0.5 e+0.5 e

1/(C1+C0) 1/C2

C0

Vg gate

0.1

0.2source drain

islandC1 C2

-0.1

0.0

V(V

)

V

-15 -10 -5 0 5 10 15-0.2

Vg (V)

V

Yu Pashkin et al (2002)


Yu. Pashkin et al. (2002)Requires atomic fab accuracy for room temperature

Low currents, but allows larger variety of materials

Nanoscale: Classical Charge Effect

If C = 1 aF, e2/2C = 160 meVC = 1 aF is a 18 nm metal particle in free space or ~4 nm in oxideSingle electron charging occurs with blockade regions (Coulomb Blockade)Single electron charging occurs with blockade regions (Coulomb Blockade)

Control OxideNano-Crystal Quantum DotQuantum Dot

Tunnel Oxide

Channel Surface


Tiwari et al. APL (1996) Muralidhar et al., IEDM (2003)

Makes low power memories possible

Magic Numbers

MetalsUsually close-packed lattices

FCC: Ag, Al, Au, Co, Cu, Ph, Pt, Rh, …gEach atom has 12 nearest neighbors13 atoms is the smallest nanoparticle of FCCLayering can lead to the next particle in the same shape Thirteen atom shape

• 55 atomsThese are structural magic numbers

For n layers, number of atoms in FCC nanoparticle is

nanoparticle in FCC

is

Number on surface is

Diameter is


14 sided; dekataessarahedron6 square and 8 equilateral faces

Magic Numbers & Properties

N = 1,13, 55, 147, 309, 561, … for FCCMinimum volume, maximum density of ~spherical shape in close packing~spherical shape in close packing

Minimum energy involves interactions of valence electrons and averaged molecular potentialp

Clusters with filled closed shells are stable and can differ from FCC arrangement but are close to these

bnumbers

I idi l t lti


M. Yu et al., PRL, 85 3560(2000)

Iridium nanoclusters -melting

J. P. Borel et al., Surface Sci. 106 (1981)

Diamond Lattice Nanoparticle

n Size na

(nm)

# Atoms # Surface Atoms

% Atoms on Surface(nm)

2 1.13 94 48 51.1

3 1.70 279 108 38.7

4 2.26 620 192 31.0

5 2.83 1165 300 25.8

6 3.39 1962 432 22.0

10 5.65 8630 1200 13.9

15 8.48 2.84x104 2700 9.5


Stability from short defect propagation distancesHigher surface percentage

Nanoscale in Other MaterialsNanoscale in Other Materials


Nanotubes

High carrier mobilityBallistic transport (<1-10µm)

10 000 2/V ( 10 )>10,000 cm2/V.s (>10µm )

High current carrying capabilitiesJ=109 A/cm2 (Most metal fails at <106 A/cm2)

Nearly-ideal surface (!)Wider choice of dielectrics

All atoms on surfacePotential for sensors

Can be direct bandgapPotential for optical devicesp

Diameter determines semiconducting (2/3) vs metallic tubes (1/3), and placement


Bucky-Balls and Nanotubes

C60


Carbon Nanotubes

Good transport

But, poor control ofof

Placement

Thickness

Chiralityy


Nanotube Band Structure and Mobility

E

⊥k

k||

0gapE

Quantized ⊥k

⊥k semiconducting nDk ππ 2=⊥

sourcedrain1.0

Vacuum

L

sourceVacuum

(e2 /h)e2

/h)

gateG

G (

e


-10 0 100.0 Reported max. mobilities:

1,000 - 100,000 cm2/V.sVg (V)

Diameter Dependence

0.10

)source

drain

0.05

G(4

e2/h

)

L

gate

10

0.00

G)

d = 1.5 nm

gate

5

10

cm2 /

V-s

d = 3.4 nm

10 5 0 5 10

0μ(1

03


-10 -5 0 5 10

Vg (V) G increases with d

Diameter Dependence

15

20

V-s

)Gmax versus d

5

10

μ (1

03cm

2/V

0.2

m/k

Ω)

versus d

0 1 2 3 40

μ

d (nm)

0.1

<1/

ρ> (

μm μpeak versus d

0 1 2 3 4 50.0

d (nm)

<

10

V-s

)

( ) LRR KK /50300 −=ρ

G ~ d μ ~ d2

μ (1

03cm

2/V

d2 Ref


Gmax d, μpeak d

1 2 3 4 51

μ

d (nm)

d2 Ref.

Zhou et al.

Temperature Scaling

0.20

54K

93K

T=

50

60

)

0.15

h)

293K238K195K

144K

93K

40

RO

N (

kΩ

0.10

G (

4e2/h 293K

0 100 200 30030

T (K)120

0.05

80

120

m2 /V

-S)

-10 -5 0 5

0.00

Vg (V)0

40

μ (1

03 cmShort Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 67

0.004 0.008 0.0120

1/T (1/K)Gmax ~ 1/T, μpeak ~ 1/T

Model – Acoustic Phonons

⎟⎠⎞

⎜⎝⎛=

∂∂=

dkEm

1

3

222

2* hh

Effective mass:

E

⎠⎝∂∂ dvkE 3 022

T1

E

Same as Metallic NT

dveleG

d

Tατ

02

02

10

44⇒

=−

K

Band Structure

TLhLhG

α00

max ==⇒

T

dev

m

epeak

200 48.0

*32.0

ατμ

h==

+Acoustic Phonon

Scattering


ScatteringG. Pennington et al., Phys. Rev. B 68, 045426 (2003)V. Perebeinos et al., Phys. Rev. Lett. 94, 086802 (2005)

Molecules

Small, and digitized size, shape and functionality forgiving tolerance, and can perform specific electrical and mechanical functions and can be self assembledmechanical functions, and can be self-assembled

But, Based on stochastic processes

Fragility of organic structures

Charge states depend on current flow

• Stability dependent on charge/oxidation state and temperature

Molecules are difficult to access

I t f i diffi ltInterfacing difficult

Proximity of contacts broaden levels and induces gap states

Line shapes do not have a sharp cut-off


Molecular Transistors


Single Electron Molecular Transistors

J. Park et al. (2002)


Single Electron Latching Switch

0.3

Cc/C = 2C0/C = 1

Vinj-ne

single-electron trap

0.1

0.2

(e/R

C)

C0/C 1Q1 = -0.425eQ2 = -0.2ekBT/(e2/C) = 0.001

n = 1

e

VS VD

C0 Cc

0.0

Cur

ren

t

n = 0

single-electron transistor

-0.1 0.0 0.1 0.2 0.3-0.1

Voltage (e/C)

( )

I-V curve within the “Orthodox” theory


Low-temperature prototype (trapping time > 12 hrs)P. Dresselhaus et al. (1994)

Nanoscale DevicesNanoscale Devices


NanoCrystal Floating-Gate Memory

Gate

nano-lcrystals

SiliconSource Drain

Control Oxide

Nano-Crystal Floating Gate

Injection Oxide

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 74Tiwari et al. IEDM (1995)

Channel Surface

Storage in Quantized Medium (Silicon)

5 nm box of Silicon

QD

Sili

Ec

Gate

Silicon


Charging and Erasure

Quantum dot5-10 nm length scale

eeee

Electrostatic energy change upon addition of an electron

eeeeee

Hamiltonian for the system:

Inversion layer1-2 nm thick

e

where

with n identifying the indices of the ladder in the inversion layer

and

with m identifying the indices of the ladder in the quantum dot

Equation of motion for the density matrix:


Gain Cell

Thin oxide 5 nm oxide

From IEDM’99 From IEDM’03


Nanocrystal Memories

4Mb Array in a 6V 90 nm process


4Mb Array in a 6V 90 nm processMuralidhar et al., 2003 IEDM

RTS: Nano-Crystal MemorySingle-Electron Events

Fast and slow processes – surface states; and correlated processes1.5p

1 5

1.0

1.0

1.5

I DD (

a.u.

)

70 71 72

1.0

1.50 50 100 150 200

63 64 65

0.5

Time (sec)


Δt = 1 msecRTS Amplitude ~ 14%

Nano-Crystal Memory: Switching Events

Capture statistics Emission statistics

60

70

80

τ = 590 msecs

60

70

= 37 6 msec

FastEvents

20

30

40

50

τemission

= 590 msec

No.

Tra

nsiti

ons

20

30

40

50 τcapture

= 37.6 msec

No.

Tra

nsiti

ons

0 1 2 3 4 5 6 7 80

10

20

Steps Duration (sec)0 100 200 300 400

0

10

20

Steps Duration (msec)p ( )

8

10

12

τcapture

= 13.9 sec

ns

12

14

16

18

τemission

= 3.2 sec

ons

SlowEvents

2

4

6

No

. T

rans

itio

4

6

8

10

No

. T

ran

sitio


0 10 20 30 40 50 60 700

2

Steps Duration (sec)

0 5 10 15 200

2

Steps Duration (sec)

Scaled Front-Side SONOS Memories

7

10-6 L = 46 nm, W = 33 nm

Use of higher defect density to counter statistical effects

10-9

10-8

10-7

(A)

ONO stack = 2 / 6 / 12 nm

1 5

1.6

)

10-12

10-11

10-10

I DD

(

ΔV = 2.7 V

1 2

1.3

1.4

1.5

WriteE

Vo

ltag

e (

V)

-2 0 2 4 610-13

VG(V)

0.9

1.0

1.1

1.2 Erase

Thr

esho

ld

Poly-silicon Gate

oxidenitride100 101 102 103 104 105

0.8

0.9

Write/Erase CyclingNitrideGate

Source


10 nmsiliconKim et al., IEEE SNW (2003)

10 nm

Drain

SONOS Memories

10-8

10-6

10-8

10-6 A Constant Window

75

10-12

10-10

I D(A

)

10-12

10-10

I D(A

)

W/L W/L

75 electrons

-2 0 2 4 610-14

VG(V)

-2 0 2 4 610-14

VG(V)

W/L33nm/46nm

W/L62nm/60nm

10-8

10-6

10-8

10-6

10-12

10-10

I D(A

)

10-12

10-10

I D(A

)

W/L W/L


-2 0 2 4 610-14

VG(V)

-2 0 2 4 610-14

VG(V)

75nm/100nm 90nm/100nm

Kim et al., IEEE SNW (2003)

Memory Using Defects on Back


Defects on the Back

10-6

S 70 V/d d

VD = 1 V

10-8

10

S = 70 mV/decade

tSi = 20 nm12

10-10

I DD

, I G

(A

)

Ultra-thin Si on ONO layer

1 0 0 5 0 0 0 5 1 010-14

10-12

ONO t k 2 / 6 / 13 L 50 W 100

-1.0 -0.5 0.0 0.5 1.0VG (V)


ONO stack = 2 / 6 / 13 nm; L = 50 nm, W = 100 nm

Single Electrons in Output Characteristics

10-7VD = 100, 200 mV

10VG – VT = 0, 0.1, …0.5 V

10-9

10-8

10

6

8

10

10-11

10-10

I DD

(A

)

4

6

I DD

(nA

)

-1.0 -0.5 0.0 0.5 1.010-13

10-12

0 50 100 150 2000

2

VG (V)

Oxide/Nitride/Oxide : 8 / 15 / 40 nm; tSi = 50 nm

VDD (mV)


Si

Silva et al., IEEE SOI Conf. (2003)

Back-Gated Devices

GateSiO2 SiO2

rce

n

Si Channel

GateSiO2 SiO2

Source DrainSi Channel

Back Gate

Sou

r

Dra

i

Back Gate

SiO2

SiO2Si Substrate

Li l (2005)


Lin et al. (2005)

Floating Gate Overlap and Coupling

L 45nm Si channel 15nm Injection O ide 6nm ControlOverlap

Leff=45nm, Si channel=15nm, Injection Oxide=6nm, Control Oxide=9nm, Back plane thickness=20nm

Write Conditions: VD=-4V, VS=-8V, Vsub=0V

Overlap is referenced to the front/read gate edge.


Kumar et al., IEEE Trans. Nanotechnology (2002)

Power: Switching and Standby

L = 90 nm with 2 nm front oxide, 5 nm back

id 25 Si d

1E-10

e (

W)

ITRS Low Operating Power

oxide, 25 nm Si, and using 21 stage ring oscillator

1E 13

1E-12

1E-11

Po

wer

/sta

ge

Devices provide tuning of standby2 5

3.0Back-Gated MOSFETfJ

)

5 10 15 20 251E-14

1E-13

Sta

nd

by

P

ITRS Low Standby Power

tuning of standby power and switching performance with good noise margin

1.0

1.5

2.0

2.5 VBG

= -0.5 V to 0.5 V

VDD

=0.8

VDD

=1.2

VDD

=1.5

per

sw

itch

(f

ITRS bulk

5 10 15 20 250.0

0.5

En

erg

y p

Delay (ps)


Charging Times (Leff ~ 45 nm)

Electron kinetic energy distribution for different drain biases along the channel

Charging/Programming time in μs for a threshold change of ~1 VSize scales limited by front-gate electrostatics and λ, i.e., 10’s of nm


Dual Function: Logic and Memory

Charged floating back gate

1E 6

1E-5 Memory windowg

1E-9

1E-8

1E-7

1E-6

A/μ

m)

window with varying back potential/

increasing

floating back gate

1E-12

1E-11

1E-10

1E 9

ID(VBG=-2.000) => Probe lifted ID(VBG=-1.500) => Probe lifted ID(VBG=-1.000) => Probe liftedID(VBG 0 500) P b lift d

I DS (

A

VDS

=1 V

potential/charge

back gate bias-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

1E-13

ID(VBG=-0.500) => Probe lifted ID(VBG=0.000) => Probe lifted

VFG

(V)

Multi-function structure – provides memory, tunable transistor function, and configurable switch

Memory window with x106 change in current/resistance

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 90Avci and Tiwari, El. Letters (2004)

Carbon Nanotube Field-Effect Transistor

Carbon Nanotube

dt ~ 1.8 nm

CNT

Ti Ti

Insulator

Back Gate

10-nm SiO2

200 nm

Ti Ti

101

Subthreshold Characteristics Output Characteristics

10-2

10-1

100

μA] Vds =

0 9 V

10

8

6μA]

Vgs = 0.4 to -1.6 VStep -0.4V

10-4

10-3

10

Id [ -0.9 V

-0.7 V -0.5 V -0.3 V -0.1 V

4

2

I d [

μ


10-5

-2 -1 0 1 2

Vgs[V]

0-1.2 -0.8 -0.4 0.0

Vds [V]

Nanotube FETs

PRL 87, 256805 (2001)

1D (ultra-thin body) channel

Ballistic transport (at low Vds)

Vgs < 0 CB

PRL 89, 106801 (2002)APL 83, 2435 (2003)

Switching can be dominated by the contact Schottky barriersScreening length

Barrier width ~ oxide thickness tox (on-state)

h+

sourcedrain

EF VB

Vds < 0

101

ox tλ ~ t d

Ambipolar behavior

Vgs > 0

CBEFe-

10-2

10-1

100

10

[μA

]

Vds =

Vds < 0

VB

CB

10-5

10-4

10-3

10

Id -0.9 V

-0.7 V -0.5 V -0.3 V source

drain


CB: conduction bandVB: valence band

10-2 -1 0 1 2

Vgs[V]

Gate oxide: 10-nm SiO2

Contact metal: Ti

Performance Factors

CB

Nanotube diameter dt (bandgap Eg ~ 1/dt)

Contact Metal (Ti, Pd, Au, Al, etc.)

EF VBφB

Gate Dielectric Thickness tox

Dielectric constant κMetal CNT

CB: conduction bandVB: valence bandφB : Schottky barrier height

Φ ∝ exp(-x/λ)λ ~ (toxdt/κ)0.5


Appenzeller et al, PRL 89, 126801 (2002)

kT/q ln10 (60 mV/dec)

Gate Structure Engineering

Vgs < 0 Goal: Obtain a unipolar CNFET

Approach: Reduce the gate field impacth+

Approach: Reduce the gate field impact

at the drain electrode to suppress

carrier injection sourcedrain

EF

Vgs > 0

e-

Calculated Id vs. Vgs

EF

reduced e-

injectionsource

drain

EF

Insulator -1 -0.5 0 0.5 1.0

B k t (V)


Back GateBack gate (V)

Appl. Phys. Lett. 83, 5038 (2003)

Performance

I s Si gate oltage V

Drain current Id vs. Al gate voltage Vg-Al

10-1

10-2

10-1

Id vs. Si gate voltage Vg-

Si

-4

10-3

10-2

0A

)

S~63 mV/dec

10-4

10-3

10

d (

μA)

S~100 mV/dec10-6

10-5

104

I d (

μA

10-7

10-6

10-5

I

Vds = -0.5 V

S 100 mV/dec

10-8

10-7

-1.2 -0.8 -0.4 0.0

V (V)

Vgs-Si = -2.5 V

10-2.0 -1.5 -1.0 -0.5 0.0

Vg-Si (V)

Contact Switching

Vg-Al (V)

Bulk Switching


Contact SwitchingTheoretical limit: S ~ 60 mV/dec

IBM

Performance

S bth h ld Ch t i ti O t t Ch t i ti

2

100 1.0

0 8Vgs-Si = -2 VV Al = 0 to 1 8 V

Subthreshold Characteristics Output Characteristics

10-4

10-2

I d (

μA) Vds =

-0.7 V -0.5 V

0 3 V

0.8

0.6

0.4urre

nt (

μA)

Vgs-Al = 0 to -1.8 VStep -0.3 V

Off State

10-8

10-6

1 2 0 8 0 4 0 0

-0.3 V -0.1 V

Vgs-Si = -4 V

0.2

0.0

C

-1 0-0 8-0 6-0 4-0 20 0-1.2 -0.8 -0.4 0.0Vgs-Al (V)

p-type CNFET

-1.0-0.8-0.6-0.4-0.20.0

Vds [V]


p yp

Little Vds dependence

Chemical Doping

Device StructureTo achieve a p/i/p or n/i/n use chemical doping profile

Advantages -

Without the use of the Si back gategate

Required for high-frequency operations

Approach -

Use patterned HSQ (Hydrogen SilsesQuioxane) to protect the middle of the nanotube from being doped


Appenzeller et al.

Band to Band Tunneling in Nanotubes

The semiconductor is one-dimensional

The body of the semiconductor is ultra-thin

Transport in the semiconductor is ballistic

The effective masses of electrons and holes are small

The effective masses of electrons and holes are similar

The semiconductor has a direct band gap


Molecule as Filter

VB

VG=0BGG VVV

2

)1( ηη −+=

V =0 3V 2VG=0.3V

VG=1.0 V

Molecular state spectrum shifts with gate potentialSymmetric molecule with unity peak resonant transmissionState spectrum fixed relative to centralState spectrum fixed relative to central molecular potential.Electrochemical potentials represented by source & drain (n or p) Fermi levelsState occupancy is 0 above VP, 1 below VN d ½ b VN d VP

VBVN and ½ between VN and VPCharge in filled state = # of electrons in orbital represented by that stateCentral Potential given by electrostatic coupling to S D and G potentials and

VA = 0 VB

VB


coupling to S, D and G potentials and increased by Qsc/CΣ

Polarization by fixed diel. permittivity.

B

Lang, Solomon, Kagan, FME & APS Mar. Mtg. (2005)

Molecules and Self-Assembly

If molecule mimics MOSFET

For gate field to penetrate molecular channel

Dielectric thickness to be comparable to the molecular length

Intimacy between molecule gate dielectric

Molecule sufficiently long and chemically functionalized and the y g ygate dielectric is sufficiently thick to limit tunneling between source and drain electrodes and to ensure an “OFF” state of the device and between source-gate

If self-assembly used as a technique for fabricationLow energy scales of assembly process (~ eV)

Higher defect rate with consequences for larger scale


Is current sufficient

Circuits and SystemsCircuits and Systems


Stability and Signal Recovery

Analog: open & closed loop/feedbackRegenerative effects and signal stability issues

DigitalSignal restoration using gain

Z2

Vin

VoutK

Vin

VoutK

= KV

Vin

VoutK

Z1

= KVin 1

1

2

1

2 11

1

−

⎥⎦

⎤⎢⎣

⎡⎟⎟⎠

⎞⎜⎜⎝

⎛++−=Z

Z

KZ

Z

V

V

in

out

Feedback between input and output (Z2, e.g.) leads to a larger input load because the 180ο phase shift during amplification1

2

+=K

ZZin


amplification

At the input C appears as (K+1)C (Miller effect )1+K

Devices and Circuits

Digital CMOS design:

Only two circuit forms matter

(maybe three)

Static CMOS, and Dynamic CMOS

These forms employed because:

They are not highly demanding of devicesThey are not highly demanding of devices

because of power gain

So they work with transistors

Robust, especially static circuitsCLK


Leakage in Dynamic Circuits in 3D/SOI

1.2

dynor_soi_tran2_fail (m7 width=0.4u)

Width=0.4 μm

0.8

1.0

ge

(V

)

A out

0 2

0.4

0.6

A B outm2#body

Vol

tag

In Leakage currentdue to PBE

B

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.2 m2#body m3#body

SOI

Parasitic bipolar (floating body) and leakage effect on noise margin

When width of m7 pull-up is 0.4 um, the circuit fails under the PBE test!

Because of PBE, an SOI-based dynamic OR circuit has a reduced noise

Time (ns)


Because of PBE, an SOI based dynamic OR circuit has a reduced noise margin, compared to bulk CMOS

C.C. Liu TCAS II (2005)

3D: Dynamic Circuits

1.2

dynor_msb1_tran2 (m7 width=0.4u)

Width=0.4 μm

0.8

1.0

ge (

V)

I

A out

0 2

0.4

0.6

A B out

Vol

tagIn

B

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.2

3D design:

Logic transistors: BULK

Time (ns)3D design:

Pre-charge, Evaluation: SOILogic: Bulk

Switching the logic transistors to bulk allows PBE to be avoided and


circuit failure is eliminated!


Pass Transistor Logic: LEAP

94 4

94.6

1 84

1.86

1.88

LEAP-Delay and body voltage for falling input

94.0

94.2

94.4

1.78

1.80

1.82

1.84

lay

(ps)

Delay

ltag

e (

V) Body voltageIn1

In2 outy

93 4

93.6

93.8

1.72

1.74

1.76De

Bod

y vo

Pass transistors: SOI

0 20 40 60 80 10093.2

93.4

1.68

1.70

Time (ns)3D is much faster than bulk.

Pass transistors: SOI

Hysteresis for falling input transition varies only about 1 ps over 100 cycles (steady state after 20 cycles)

Delay constant after body voltage reaches steady state, which varies with device design (effects of generation vs recombination currents)


device design (effects of generation vs. recombination currents)


Analog Mixed SOI-Bulk Design

Cascode Current-Cell: 60

=SOI, =bulk 40

)

SN S

VBiasM0

M1 SN S

VBiasM0

M1

3-D design

20

I OU

T (

μA)

VDD

=3.3 V, VGS|M1

=2.5 V

SOI:V

Bias=0.75 V

0 1 2 3 4 5

0

Bias

VBias

=1.0 V

VBias

=1.25 V

3-D: V

Bias=0.75 V

Kink-free analog operation requires remapping of biasing

0 1 2 3 4 5

VOUT

(V)


Source: C. C. Liu

NT Mixer/Transistor

S)

a)3

4

ssgg

VVVV

GI )2/|(| +Δ

∂∂

=FET transistor:

Gd

c(μ

S

1

2

2)(4

1 acs

gmix V

V

GI

∂∂

=Mixing signal for ac applied to source:

a)

GateCatalyst Pad

ImixVg

200

150

A)

0

10 μm

Drain

Source

AlternateDrain

Pad

100 μm

* 10050

100

I mix

(nA

)

I mo

del

(nA

b)

b)50 Ω

Bias Tee

Signal

Gate

SiO2

SiO2

Drain

NT

Source -3 -2 -1 0

0 0

Vg (V)


VsdGenerator

HR-Si

2 g ( )

f = 10 MHz

NT Mixer/Transistor up to 50 GHz

100

-1.2 V

Mixing signal versus frequency Setup

10

100

-0.3 V

-0.5 V-0.7 V1.2 V

mix

(nA

) Device

τsetup = RC

50

60

3

4

G

Device-li it d

1

100

0

100

200

0

5

10

10 MHz

50 GHz

I m

Time constant of rolloff versus Vg

20

30

40

50

2

3G

τ (p

s)

τ G (

μS)

limited

0.1 1 10

0.1 -3 -2 -1 0-100

Frequency (GHz)

-2.0 -1.5 -1.0 -0.50

10

20

0

1

τ( )

τ

G

Setup-limitedHigh freq. roll off caused by setup,not device (except near turnoff)


Vg (V)NT FET mixer operates up to 50 GHz

Rosenblatt et al. , APL (2005)

Classical vs. Quantum Computing

Classical bit: 1 (On) and 0 (Off)Stable pointer states of the computer hardware

Q t bit Q bit ( iti f t t t )Quantum bit: Qubit (superposition of two states)

Every two level system can serve as qubit

For any digital computer, its set of computational states is some set of mutually distinguishable abstract states

The specific computational state that is in use at a given time represents the specific digital data currently being processed within the machine

I t ti th t ti l t t i t l i tIn quantum computing the computational state is not always a pointer state


Quantum Entanglement


Classical versus Quantum Bit


Quantum Computing?

Non-pointer-state computingIf feasible, potentially exponentially more time-efficient than any possible classical computing scheme at solving some problems:p g g p

Factoring, traveling salesman, discrete logarithms, related problems

Simulating quantum physical systems accurately

• This was the original motivation for quantum computing research

Harnesses these quantum effects on a large and complex scaleComputational states that are not just pointer states, but also, coherent superpositions of pointer states.

States having non zero amplitude in many pointer states at the sameStates having non-zero amplitude in many pointer states at the same time! “Quantum parallelism”

Entanglement (quantum correlations)

Between the states of different subsystems

Unitary (thus reversible) evolution through time

Interference (reinforcement and cancellation)

Between convergent trajectories in pointer-state space


Gates without Superposition

All classical input-consuming reversible gates can be represented as unitary transformations!

e g input consuming NOT gate (inverter)e.g., input-consuming NOT gate (inverter)

in outin out

in out0 11 0

010

⎤⎡ 10 10 =N100 ⎟

⎠⎞⎜

⎝⎛≡ 01:

10

⎥⎦⎤

⎢⎣⎡≡ 01

10:N 01 =N101 ⎟

⎠⎞⎜

⎝⎛≡

⎠⎝

10:


1⎠⎝1

Controlled-NOT

CNOT (input-consuming XOR) gate

A B A’ B’A A’

B B’ = A⊕B

A A’

B

A B A’ B’0 0 0 00 1 0 1

B B’ = A⊕BBB’ = A⊕B 1 0 1 1

1 1 1 0

11100100

00

11100100

⎥⎤

⎢⎡ 0001 Example:

10

01

⎥⎥⎥

⎢⎢⎢≡ 1000

0010:X 1110 =XA B A B


11⎥⎦⎢⎣ 0100

Toffoli Gate (CCNOT)

A B C A’ B’ C’0 0 0 0 0 00 0 1 0 0 1

AB

A’=AB’=B A A’

0 0 1 0 0 10 1 0 0 1 00 1 1 0 1 1

C

B’B

1 0 0 1 0 01 0 1 1 0 11 1 0 1 1 0

(XOR)C C’ = C⊕AB C C’

111110 101100 011010 001000

⎤⎡ 1 1 1 1 1 1

010

001

000

⎥⎥⎥⎤

⎢⎢⎢⎡

00001000000001000000001000000001

N h t h if

101

100

011

⎥⎥⎥⎥

⎢⎢⎢⎢≡

10000000001000000001000000001000:X Now, what happens if

the unitary matrix elements are not always 0 or 1?


111

110⎥⎥⎦⎢

⎢⎣ 01000000

10000000y

The Square Root of NOT

If input is either basis state (0 or 1) you get a state that appears random when measured…

0 (50%) 0 (50%)N1/20 0 (50%)

1 (50%)N1/21 0 (50%)

1 (50%)

But if you feed the output back into another N1/2 without measuring it, you get the inverse of the original value!

“How is thatpossible?”

N1/20 0 (50%)

1 (50%)N1/2 1

1 (50%)

N1/20 0 (50%)N1/2 0


N1 (50%)

N

NOT1/2: Unitary Implementation

0

1 0⎤⎡ −+ 11 ii 100

⎥⎥⎥⎤

⎢⎢⎢⎡

+−≡11

22:ii

ii

N ( ) NN =⎥⎦

⎤⎢⎣

⎡=

1

010

01

102

1⎥⎦

⎢⎣ 22

⎤⎡

100112

11 ii

i

NN−

++

=⎥⎥⎤

⎢⎢⎡ +

=⎥⎤

⎢⎡= 100

222

20 ii

NN +=⎥⎥

⎦⎢⎢

⎣−=⎥⎦

⎤⎢⎣⎡=

P b ½ P b ½


2 ⎦⎣ Prob. ½ Prob. ½

Optical Implementation of N1/2

Beam splitters (semi-silvered mirrors) form superpositions of reflected and transmitted photon states

“1”

“1” “1”

“1” “0”

“0” “0”laser


“1”

SET Probing Qbit

Box: 700x50x15 nm; 108 electrons2/2C 11 30 3e2/2C = 117 μV, T = 30 mK, kT = 3 μV

Initialize by preparing pure state |0> away from resonanceApply fast voltage pulse Δt to gate (non-adiabatic) to create degenerate charge state at resonant condition (|0> and |1> are now superposed


g (| |Sample measurement of |1> by tunneling probeRepeat by sweeping Δt in pico-seconds Nakamura

Quantum Computing Requirements

DiVicenzo’s check list:Identifiable qubits and their scalability

I iti li ti dInitialization procedure

Preparation of ground state of the whole system

Low decoherence

L d h ti t tiLong decoherence time versus gate time

Quantum gating – ability to realize a universal gate through control of system Hamiltonian

Controlled evolutionControlled evolution

Reliable readout

Q bit C li t i hb dQubit Coupling: nearest neighbor versus common mode

Engineering Correction Code (ECC): to address decoherence –redundant qubit register and majority voting


Systems Hierarchy and ArchitectureSystems, Hierarchy and Architecture


Molecular Memories?

Memory by using switching behavior in a crosspoint configuration

Logic by diode logic with open and diode cross-points and i t (!)resistors (!)

10

molecular switch

nt (

mA

)

0

5

10

Cur

ren

10

-5

0

Voltage (V)

-10

-2.0 -1.0 0.0 1.0

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 123HP

Molecular: 2 terminals or 3 terminals?

Customized combinatorial logic scales polynomiallywith function size (~N2).A l i l ti ll ith f ti iArray logic scales exponentially with function size(~22N)Array peripherals scale in proportion to function size


UCLA, CalTech, HP

Molecular Latching Switches

O OR RR

perylenediimide group as a single-electron trap island

N

O

N

OO

N C

R O

R = hexyl (C6H13-)

OPE bridges as tunnel junctions

non-conducting support group

R

NN

O

O

O

O

R

R

N

R

C

R

R

N

R

R

C

O O

j

naphthalenediimide groupas a single-electron transistor island

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 125A. Mayr (2003)

CMOL

metallici i

self-assembledmolecular devices

interfacepin

interface pins

nanowiringlevels

CMOSstack(only a few metal layers

shown)

CMOL combines: - (relatively sparse but highly functional) CMOS subsystem

MOSFETSi wafer


CMOL combines: (relatively sparse, but highly functional) CMOS subsystem- very dense nanowire crossbar, and- a molecular-scale device at each nanowire crosspointLikharev (2003)

CMOL

2rFnano

Tilt α = sin-1(Fnano/βFCMOS)

selectednanodevice

selected word

nanowire

α

CMOScell 1

pin 2

selected bitnanowire interface

pin 1interface CMOS

ll 2

2βFCMOS

pin 2cell 2

2F

pin 2’

2Fnano

αpin 1

Nanodevice addressed Each and every nanodevice


via two CMOS cellsy

may be addressed!Likharev (2003)

CMOL FPGA

CMOS inverters + nanodevice latches for (re)configuration

(a)2βFCMOS 2βF ×2(r 1)

(b)

(a)2βFCMOS 2βFCMOS×2(r - 1) αCMOSrow 1

VDD

inputnanowire

CMOSinverter

CMOSrow 2

output nanowireCMOS

column 2CMOS

column 1

AA F

(c)

CMOL FPGA fabric

B

A

FF

A B nanodevices

B

RO

N


CMOL FPGA fabric F

CMOS inverter

passtransistor

RpassCwire

Likharev (2005)

3D: Packaged & Integrated

Packaged IntegratedS. K. Kim (2005)A. Matsuzawa (2005)

Level 4

Level 3

Level 2

Level 1SiO

SiO2

Evolutionary and relatively well-characterized technology Addresses interconnect gap near

Si

SiO2

SiO2

Addresses interconnect gap near-termEnables above IC processing and high quality passivesUses known good dies

A major change and still in development If effective, makes possible large changes densities, integration, cost,


gAllows high density interposers

g , g , ,power, performance and footprint

Samsung: 3 Layer SRAM

25 f2

All process temperatures <650 C after bulk device fabricationafter bulk device fabrication

Plasma oxidation for gate oxide

Single Co silicidation of all transistors

Ultra-compact


p

Source: S. M. Jung et al. (Samsung)

Graphics Processor

High Performance Application

P=189 WR 0 26 C/W

Critical path2-D 3-D

RSUBS=0.26 C/W TMAX=100 C Frequency=1/delay(delay: Logic, wire, setup

d l )

Critical path

delays) YW=YB=95%

Footprint [mm2]

Clock frequency [GHz]

# of circuit layers

Normalized cost

Maximum temp. [oC]

Normalized delay

Normalized wire length

Footprint [mm2]

Clock frequency [GHz]

# of circuit layers

Normalized cost

Maximum temp. [oC]

Normalized delay

Normalized wire length

65.1

47.8

183

1.45

1.67

0.989

3

4

1

1131.610.5930.410No temp. constraint

3-D

2-D 75.01.001.001.00

1.46 94.20.6820.634Balanced 65.1

47.8

183

1.45

1.67

0.989

3

4

1

1131.610.5930.410No temp. constraint

3-D

2-D 75.01.001.001.00

1.46 94.20.6820.634Balanced

Short Course, NanoSingapore, 2006 Sandip Tiwari; Cornell University 131Source: C. C. Liu & Tiwari, ISCAS-200563.6

77.6

1.39

1.66

3

33 D

1.43

1.74

95.9

89.8

0.7100.599Cost-oriented

0.5960.521Delay-oriented

63.6

77.6

1.39

1.66

3

33 D

1.43

1.74

95.9

89.8

0.7100.599Cost-oriented

0.5960.521Delay-oriented

3-D Microprocessors

Goal of improving logic-memory interactions and to compensate logic and memory performance divergencelogic and memory performance divergence

Current designs exceedingly complex (-> power^ ) focused on

Superscalar (> 1 inst/cycle), out-of-order execution, instruction-level parallelism, hiding memory latency, …p , g y y,

3-D in μP: High density, low latency, large bandwidth

1−10 μm separationVertical connections throughout the design areathroughout the design area


Latency and Bandwidth

2-D: Connections on the peripheryLong global connections

CPUg g

CPU to off-chip main memory with latency and missesMemory

3-D: Connections across the area

Connections short + vertical

Suitable for high-bandwidth and vector

Memory

goperations

No pin cost, large block access of data

CPU

The following example uses a baseline 2-D processor core representative of

Latency: Important for random access (servers, e.g.), single coreBandwidth: Multiple cores, multi-threads, graphics


The following example uses a baseline 2 D processor core representative of current technology3 GHz CPU, 750 MHz memory, 64 KB L1I, 64 KB L1D, 1 MB L2

Expanding L2 Cache

Floating-point programs

120

140

)

Perfect L2

SPEC2000 Integer programs

60

Standard DRAM Standard DRAM +

t f t h

Perfect L2

80

100

O hi DRAM

eedu

p ov

erpr

oces

sor

(%)

40

eedu

p ov

erpr

oces

sor

(%) stream prefetch

On-chip DRAM + stream prefetch

20

40

60On-chip DRAMw/ 1 MB L2

Ave

rage

sp

base

line

2-D

p

Standard DRAM

20On-chip DRAMw/ 1 MB L2

Ave

rage

spe

base

line

2-D

p

2 MB 4 MB 8 MB 16 MB 32 MB 64 MB0

20b

L2 cache size

Standard DRAM Standard DRAM + stream prefetch On-chip DRAM + stream prefetch

2 MB 4 MB 8 MB 16 MB 32 MB 64 MB0

b

L2 cache size

Performance peaks at 8 MB for integer programs with standard DRAM Example of trade-off between fitting the working data (4-16 MB for integer programs) into the cache (better performance) and increased access latency for larger caches (worse performance)

f f


Larger working data of floating-point programs continue to improve with cache size despite cache hit latency with large cache size

C. C. Liu .. Tiwari., IEEE D&T Mag. (2005)

L2/L3 Cache Sizing with Stream Prefetching

Floating-point programs

120

140

On-chip DRAM +

%)

Perfect L2

80

100

pstream prefetch

Standard DRAM +stream prefetch

edup

ove

rro

cess

or (

%

60

80

On-chip DRAM w/ 1 MB L2 (no L3)

vera

ge s

peel

ine

2-D

pr

20

40Av

base L2 = 1 MB

L2 = 2 MB L2 = 4 MB L2 = 8 MB

Standard DRAM

Performance within 8-10% of perfect L2Large speedups achievable with small L2/L3 cache because of significant reduction in main

2 MB 4 MB 8 MB 16 MB 32 MB 64 MBL3 cache size


Large speedups achievable with small L2/L3 cache because of significant reduction in main memory latencyHierarchy critical to performance

C. C. Liu .. Tiwari., IEEE D&T Mag. (2005)

Complexity

Rent’s Rule: Terminal count is related to number of gates (at all hierarchical levels)

T NT = t Np

(0<p<1; t is number of terminals per logic block)

p=1 is un-optimized placement

Number of interconnections among a group of sub components at any levelNumber of interconnections among a group of sub-components at any level is proportional to the total terminal count of all the sub-components

With placement optimization (p<1), only a fraction of logic blocks accessible

This accessibility defines how much of the circuitry do iterative testing y y gprocedures access and test for usefulness

If logic blocks defective: Naccessible ~ ((1-dLOGIC)N)p

If wiring defective, the number of testable logic blocks: g , g

Naccessible ~ (1-dLOGIC) Np

a considerably more serious problem


Configurability: Defects and Testing

Suppose, we work with 105 logic blocks, each employing 1000 device elements

What does it mean that one can work with chips that are 90% functional (or that 10% of logic blocks are faulty)

If the probability of failure is p for each element, probability of a logic block b i f i l i (1 )1000being functional is (1-p)1000

Rate of connectivity is non-linearly related to defects, and affects congestion, power, ….

Probability of 90% yield in logic blocks implies 1 in 104 device level faults


y % y g p

We still need extremely high reproducibility and yield

Observability in Presence of Defects

Testing of N modules in a defect-free system

Percentage of modules tested/testable in presence

of interconnect defects

Usable logic blocks of a chip reduces rapidly with interconnect defects


g p p ysince their correctness can not be tested.Testability is cumbersome. Kumar, DFT (2004)

Interconnect Defect Penalty


Kumar, DFT (2004)

Complexity Driven by Connectivity

Minimum length scale (gate) 18 nm (printed 10 nm)

ITRS view of 2018

Maximum length scale (chip) 18 mm (i.e. x106 of minimum length)

# of devices 14 x 109 (Could even be x10-100)

# of nodes 4096

Node length 0 275 mmNode length 0.275 mm

# of transistors/node 3.4x106

Global RC delay 618 ps/mm

Vertical separation 27 5 umVertical separation 27.5 um

FI3, FO3 NAND 2.8 ps

Clock Cycle 45 ps with logic depth of 16

Ch l idth 256 f 2D t kChannel widths 256 for 2D network

512/n for n-dimensional


Network-on-Chip

600

2-D

2-D

Message length=2048 bitsN=4096 nodes

Message length=64 bitsN=4096 nodes

400

500

2-D

wir

e d

ela

ys)

2-D 3-D symmetric 3-D asymmetric

300

2-D

wir

e de

lays

) 2-D 3-D symmetric 3-D asymmetric

2-D 2-D

200

300

(Num

ber

of u

nit 2

200

(Num

ber

of

unit

2

3 D

2 3 4 5 6 7 8 9 10 11 12100

200

Late

ncy

(

Dimension (n)

2 3 4 5 6 7 8 9 10 11 12

100

Late

ncy

Dimension (n)

3-D 3-D

Network on chip connected to system on chipData hopping between modules

kn number of nodes where k is radix and n dimension of the network2 D 3 D l d d i i h d f k /2 k /3

( )


2-D to 3-D leads to decrease in periphery nodes from kn/2 to kn/3

Large performance gain from increase in interconnectivityC. C. Liu and S. Tiwari (unpublished)

Conclusion

Nanoelectronics will certainly be evolutionary, and may be revolutionary

Complex applications (beyond sensing ) require a systematicComplex applications (beyond sensing, …) require a systematic, robust and reproducible framework that requires a number of properties across scales


Documents

Sandip Tiwari [email protected]/files/nanoelectronics... · 2009. 2. 11. · C High Abstraction (HDL) 10-6 Device Boltzmann Compact ASX, Spice, … Lumped