Scalable Front-End Digital Signal Processing for a Phased Array Radar Demonstrator

F. Winterstein, G. Sessler, M. Montagna, M. Mendijur, G. Dauron, PM. Besso

International Radar Symposium 2012

Warsaw, 24 May 2012

Background of the SSA activity

Context

• ESA Space Situational Awareness

(SSA) initiative

Objective of the SSA initiative

• Support of the European

independent utilisation of

and access to space

3 segments

• Space weather events

• Near-Earth Objects:

Potential asteroid impact hazards

• Space Surveillance and Tracking:

Objects orbiting the Earth

Impact on Hubble solar panel

Source: http://www.esa.int/ssa

Managed by ESA and contracted to Industry

SSA Radar Element

~ large

objects

Phased array

radar

demonstrator

Radar to catalogue

objects in low-Earth

orbit

~5-10cm objects

at 800 km altitude

System

Detection

design goal

Mini-Radar

demonstrator

ESA internal development

Independent experimental system

in support of SSA Radar Element

Not designed for space surveillance

but for nearby objects

2010 - 2012 2013 - 2020 Timeframe

Outline of presentation

Space surveillance for ESA’s SSA preparatory programme

Mini-Radar system architecture

FPGA signal processing architecture

Synthesis results

System tests

Summary and outlook

Mini-Radar System Architecture

16 fully parallel TX/RX chains

RF signalsHigh-power

RF signals 1616

Analog

Front-end

16-Patch

Antenna

Array

16-Patch

Antenna

Array

Analog

Front-end

and

Phase

Shifters

TX RX

IF signals

RF signalsHigh-power

RF signals

Low-power

RF signals

16

16

16

16

Analog

Front-end

16-Patch

Antenna

Array

16-Patch

Antenna

Array

Analog

Front-end

and

Phase

Shifters

Syn

ch

ron

iza

tio

n / C

on

tro

l

Beam

samples

Digitized IF

samples

1

16

N

FPGA

A/D

Converter

Arbitrary

Waveform

Generator

Divider

Host

Computer

Mini-Radar System Architecture

TX RX

Waveform flexibility:

CW or pulsed LFM

Large-scale phased array

radar:

• Distributed processing

nodes

• Computational burden for

a single node?

Scope of this work:

• Estimation of

computational complexity

wrt. FPGA utilization

Outline of presentation

Space surveillance for ESA’s SSA preparatory programme

Mini-Radar system architecture

FPGA signal processing architecture

Synthesis results

System tests

Summary and outlook

FPGA Signal Processing Architecture

Simultaneous sampling

of 16 RX channels

Digital down-conversion

to complex baseband

Low-pass filtering, high-

pass filtering, integration

FFT processing (CW) /

Pulse compression (LFM)

Channel equalization /

Digital beamforming

Transfer to host PC

FPGA Implementation:

Hardware-folding 4-to-1

to save FPGA resources

DC

I/Q-Demodulation

A/D 2

Filtering

CIC, Integrator, FIR

Beamforming

Channel Equalization, (u/v)-to-weight Transformation, Formation of N Beams

A/D 1 A/D 16

Doppler Process /

Pulse Compress

FFT, Weighting, IFFT

Direct Memory Access Interface

Detection and Post-Processing

20

0 M

Hz

Do

ma

in

DC

I/Q-Demodulation

DC

I/Q-Demodulation

Filtering

CIC, Integrator, FIR

Doppler Process /

Pulse Compress

FFT, Weighting, IFFT

Doppler Process /

Pulse Compress

FFT, Weighting, IFFT

Filtering

CIC, Integrator, FIR

N

N

FPGA

Host Computer

50

MH

z

Do

ma

in

Input Synchronization

, , ,

, , ,

, , ,

,

,

FPGA Output – Data Cube

CW

LFM

Outline of presentation

Space surveillance for ESA’s SSA preparatory programme

Mini-Radar system architecture

FPGA signal processing architecture

Synthesis results

System tests

Summary and outlook

Scaling number of RX channels and bandwidth

0 4 8 12 16 20 24 28 320

20

40

60

80

100

Parallel RX channels

Re

so

urc

e u

tiliz

atio

n (

%)

CW, 97.7 kHz bandwidth, 256 beams

REG

LUT

BRAM

DSP

0 4 8 12 16 20 24 28 320

20

40

60

80

100

Parallel RX channels

Re

so

urc

e u

tiliz

atio

n (

%)

LFM, 6.4 MHz bandwidth, 256 beams

REG

LUT

BRAM

DSP

0 0.1 0.2 0.3 0.40

20

40

60

80

100

Bandwidth (MHz)

Re

so

urc

e u

tiliz

atio

n (

%)

CW, 16 channels, 256 beams

REG

LUT

BRAM

DSP

0 4 8 12 16 20 240

20

40

60

80

100

Bandwidth (MHz)

Re

so

urc

e u

tiliz

atio

n (

%)

LFM, 16 channels, 256 beams

REG

LUT

BRAM

DSP

Outline of presentation

Space surveillance for ESA’s SSA preparatory programme

Mini-Radar system architecture

FPGA signal processing architecture

Synthesis results

System tests

Summary and outlook

Radar Measurements

Time (s)

An

gle

of a

rriv

al (d

eg

)

Beam-former output for scan in azimuth

0 5 10 15 20-80

-60

-40

-20

0

20

40

60

80

Time (s)

An

gle

of a

rriv

al (d

eg

)

Beam-former output for scan in elevation

0 5 10 15 20-80

-60

-40

-20

0

20

40

60

80

RX TX

Close mono-static setup

CW radar end-to-end test

• Direction finding

• Doppler

Radar Measurements

RX TX

Close mono-static setup

CW radar end-to-end test

• Direction finding

• Doppler

Time (s)

Ra

dia

l ve

locity (

km

/h)

0 5 10 15 20-20

-10

0

10

20

Outline of presentation

Space surveillance for ESA’s SSA preparatory programme

Mini-Radar system architecture

FPGA signal processing architecture

Synthesis results

System tests

Summary and outlook

Summary and Outlook

Mini-Radar to serve as an experimental reference system

Full radar development from scratch

Flexible FPGA signal processing implementation

• Waveform flexibility

• Scalable in number of channels, bandwidth, number of beams,

and processing throughput

Estimation of computational complexity of the receiver signal

processor in terms of FPGA resource consumption

System tests to validate the Mini-Radar system

Future activities:

• Further signal processing techniques (such as pulse-to-

pulse-processing)

Thank you for your attention!

Annex

Comparison GOPS – DSP Slices

Down-converter Filtering Doppler Processing Beam-former Others 0

10

20

30

40

50

60

Dis

trib

ution (

%)

GOPS

DSP resources utilization

Processing Gain Measurements

CW

LFM

A/D out DC CIC Integr. FIR FFT Beamf.0

20

40

60

80

100

SN

R (

dB

)

CW application processing gain

Theoretical value

Measured value

A/D out DC FIR Pulse com. Beamf.0

20

40

60

80

100

SN

R (

dB

)

LFM application processing gain

Theoretical value

Measured value

59 dB

43 dB

Mini-Radar link budget

System properties Transmit power 40.0 dBm

Required SNR 20.0 dB

Target properties Target RCS (metallic sphere with 0.5m radius) -1.1 dBm²

Antenna properties Transmit antenna gain (phased array antenna) 16.0 dBi

Receive antenna gain (single element) 6.0 dBi

Receiver noise Receiver noise temperature at 1st LNA input (290K physical temperature)

170.4 K

Analog front-end noise bandwidth 8.8 MHz

System losses Receiver cable and additional losses (due to implementation imperfections)

2.6 dB

CW Operation

Receiver processing gain 59 dB

Required signal power at 1st LNA input -145.7 dBm

Reference range 9063 m

LFM Operation

Receiver processing gain 43 dB

Required signal power at 1st LNA input -130.3 dBm

Reference range 3742 m

Scaling throughput

40 50 60 70 80 90 1000

5

10

15

20

25

FPGA DSP slice utilization (%)

Exe

cu

tio

n tim

e (

ms)

40 50 60 70 80 90 1000

5

10

15

20

25

FPGA DSP slice utilization (%)

Exe

cu

tio

n tim

e (

ms)

15.7 GOPS

46.7 GOPS

16 RX channels, 6.4 MHz bandwidth (LFM), 256 beams

7.4 ms

Frequency choice & licence for Mini-Radar

Measurement of interferers within radar band to find a good frequency for the Mini-Radar

Frequency licence for Mini-Radar: 1300-1320 MHz

Mini-Radar system design: Receiver

Receiver block diagram

Analogue

Front-end

16-Patch

Antenna

Array

Configuration

FPGAHOST

Computer

A/D

ConverterBeam samples /

Channel samples

Digitised IF

samples

IF signalsRF signals

Mini-Radar system design: Receiver

Receiver block diagram

Analogue

Front-end

16-Patch

Antenna

Array

Configuration

FPGAHOST

Computer

A/D

ConverterBeam samples /

Channel samples

Digitised IF

samples

IF signalsRF signals

Mixer IF FilterRF Filter IF AmplifierRF Amplifier

From

antenna

To A/D

converter

AmplifierSignal Generator 16-Way-Splitter

Chain 1

Chain n

Chain 16

RF Cable IF Cable

LO Cables

IF: 20 MHz

Single receiver chain

Mini-Radar system design: Receiver

Receiver block diagram

Analogue

Front-end

16-Patch

Antenna

Array

Configuration

FPGAHOST

Computer

A/D

ConverterBeam samples /

Channel samples

Digitised IF

samples

IF signalsRF signals

Mini-Radar system design: Receiver

Receiver block diagram

Analogue

Front-end

16-Patch

Antenna

Array

Configuration

FPGAHOST

Computer

A/D

ConverterBeam samples /

Channel samples

Digitised IF

samples

IF signalsRF signals

Mini-Radar system design: Transmitter

Arbitrary waveform generator

Transmitter design (signal generator)

R&S

Signal

Generator

16-Patch

Antenna

ArrayHigh-power

RF signals

Low-power

RF signals

Phase

Shifter /

Power

Amplifier

TX control

from Receiver

Div

ide

r 16 16

16 parallel modules

Digitally-controlled phase shifter (360˚, 6 bit)

Power amplifier (1 Watt output, 30 dB gain)

Output low-pass filter

Design and manufacturing by external supplier

Transmitter design (phase shifter / power amplifier)

RF FilterRF Amplifier

RF

input

To

antenna

Chain 1

Chain 2

Chain 16

Phase Shifter

φ

Latch

6

Becker Nachrichtentechnik GmbH

Mini-Radar system design: Transmitter

R&S

Signal

Generator

16-Patch

Antenna

ArrayHigh-power

RF signals

Low-power

RF signals

Phase

Shifter /

Power

Amplifier

TX control

from Receiver

Div

ide

r 16 16

Transmitter design (antenna)

Mini-Radar system design: Transmitter

16 element patch antenna array

Dual polarization (horizontal + vertical)

Same design as receive antenna

R&S

Signal

Generator

16-Patch

Antenna

ArrayHigh-power

RF signals

Low-power

RF signals

Phase

Shifter /

Power

Amplifier

TX control

from Receiver

Div

ide

r 16 16

Antenna design

Link budget

RX/TX front-

end hardware

Radar

waveformsBeamforming

System

calibration

Detection

algorithms

Orbit

determination

Space debris

cataloguing

Frequency

choice /

allocation

Range /

Velocity / Angle

estimation

Signal

processing

Antenna design

Link budget

RX/TX front-

end hardware

Radar

waveformsBeamforming

System

calibration

Detection

algorithms

Orbit

determination

Space debris

cataloguing

Frequency

choice /

allocation

Range /

Velocity / Angle

estimation

Signal

processing

Covered by Mini-Radar project

Mini-Radar project

Mini-Radar project

Develop a small-scale radar demonstrator

Support industrial SSA radar developments

Build up internal experience

SSA radar system building blocks

Mini-Radar direction finding

Measurement setup: Direction finding

ReceiverTrans-mitter

15°30°

45°

0° -15°-30°-45°

radar target

Radar measurement setup:

Phased array receiver

Determine direction of reflected signal via beam-forming

MTI filter for clutter suppression

-> Validate receiver beam-forming

-40 -20 0 20 40-40

-20

0

20

40

Actual angle [deg]

Angle

[deg]

-40 -20 0 20 40-40

-20

0

20

40

Actual angle [deg]

Angle

[deg]

Actual angle [deg]

Angle

[deg]

-40 -20 0 20 40-40

-20

0

20

40

Mini-Radar beam-forming measurements

Receiver beam-forming: Beam-forming angle versus angle of actual signal direction.

Red: high signal power Blue: low signal power Black line: expected maximum value

-40 -20 0 20 40

-30

-20

-10

0

Angle [deg]

Beam

pow

er

[dB

]

-40 -20 0 20 40

-30

-20

-10

0

Angle [deg]

Beam

pow

er

[dB

]

Cut at -20°

Cut at 0°

Radar Measurements

Close mono-static setup

CW radar end-to-end test

• Direction finding

• Doppler TX RX

20 deg

10

de

gTime (s)

An

gle

of a

rriv

al (d

eg

)

Beam-former output for scan in azimuth

0 1 2 3-80

-60

-40

-20

0

20

40

60

80

Time (s)

An

gle

of a

rriv

al (d

eg

)

Beam-former output for scan in elevation

0 1 2 3-80

-60

-40

-20

0

20

40

60

80

Radar Measurements

Close mono-static setup

CW radar end-to-end test

• Direction finding

• Doppler TX RX

20 deg

10

de

gTime (s)

Ra

dia

l ve

locity (

km

/h)

0 1 2 3-50

-25

0

25

50