Scaling of MOSFETs and Short Channel Effects

8/10/2019 Scaling of MOSFETs and Short Channel Effects

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MOSFET Scaling and

Small Geometry Effects


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Design of high-density chips require a packingdensity as high as possible.

Transistors fabricated should have sizes assmallas possible.

The systematic reduction in the dimensions ofdevices is referred to as MOSFET scaling.

It causes change in MOSFET operationalcharacteristics.

There are physical limitationsto the extent

of scaling.


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Geometric ratios found in larger devices are usuallypreserved.

It results in total area reduction Hence gives increased overall functional density of

the chip.

Full Scaling: Constant field scaling

Constant voltage scaling

Scaling factor S>1

Scaled device dimensions = larger device dimensionsdivided by S


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Reduction of min feature size for a typicalCMOS gate array process:

Year 1985 1987 1989 1991 1993 1995 1997 1999

Feature 2.5 1.7 1.2 1.0 0.8 0.5 0.35 0.25Size (m)

S ranges from 1.2 to 1.5 for every successive generations.


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Full Scaling :

*Aims at preserving the magnitude of internalelectric fieldsin the MOSFET.

*For this, all potentials must be scaled by samescaling factor.

*Affects the threshold voltage.

*So, the charge densities must be increased inthe same proportion.


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The influence of full scaling on

C-V characteristics of MOSFET:(Assumed that mobility is not affected significantly by scaling)


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Significant power reduction is most attractivefeature of full scaling.

However power density per unit area remainsunchanged.


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Constant voltage scaling:

*Peripheral and interfacing circuitry may require certain voltagelevels and hence full scaling is not advisable.

*Constant voltage scaling is preferred here.*All dimensions of MOSFET are scaled. However, the power supply

voltage and the terminal voltages remain unchanged.

*To preserve the charge-field relations, doping densities must beincreased.


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How Doping Densities are Scaled?


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Short Channel Effects

Short Channel Device:Channel length Depletion region thickness

OR

Effective channel length Source / Drain junction Depth

Attributes:

1. Limitations imposed on electron driftcharacteristics in the channel2. Modification of threshold voltage due to the

shortening of channel length


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Following are major short channel effects:

1. Velocity Saturation2. Surface Scattering3. Hot Electrons4. Drain Induced Barrier Lowering (DIBL) &

Subthreshold Conductance

5. Gate Oxide Leakage6. Gate Induced Drain Leakage (GIDL)7. Lower Transconductance8. Stress Induced Leakage Current (SILC)

9. Channel Length Modulation10. Impact Ionization


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VELOCITY SATURATION

At low Ey, the electron drift velocity vd in the channel varieslinearly with the electric field intensity.

However, as Ey increases above 104 V/cm, the drift velocity

tends to increase slowly, and approaches a saturation value of vd= 107 cm/s around Ey= 105V/cm at 300 K.

As the field increases above 104 V/cm, optical phonons areemitted alongside acoustic phonon.

Due to this, the drift velocity cannot increase above certainlevel and it becomes saturated. So, the current eventually isfound lesser than the anticipated value.


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SURFACE SCATTERING

As the channel length becomes smaller, due to the lateral extension

of the depletion layer into the channel region, the longitudinal

electric field component Ey increases, and the surface mobility

becomes field-dependent.

Since the carrier transport in a MOSFET is confined within the

narrow inversion layer, and the surface scattering, that is the

collisions suffered by the electrons that are accelerated toward the

interface by Ex causes reduction of the mobility and the electrons

move with great difficulty parallel to the interface.

So, the average surface mobility becomes less as compared to that

of the bulk mobility and eventually it affects the current.


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HOT ELECTRON


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HOT ELECTRONEFFECTS

Due to high electric field near theSi-SiO2 interface electrons gainsufficient energy to cross theinterface potential barrier andenter into the oxide layer .

They are trapped causing oxidecharging which accumulate withtime.

This causes transistor threshold

shift and mobility change effectinggatescontrol on drain current.

It can be reduced by using betterquality oxides.


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Punch Through:For large drain bias voltage, the depletionregion of drain extends towards source andmerges. This is called punch through.

Punch through can be minimized by:

1. Thinner oxide

2. Larger substrate doping3. Shallower junctions4. Longer channels


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Increased gate-oxide leakage

The gate oxide, should be made as thin as possible to increasethe channel conductivity and performance when the transistoris on and to reduce subthreshold leakage when the transistor is

off.

However, with very thin gate oxides the quantum mechanicalphenomenon of electron tunnelling occurs between the gate andchannel, leading to increased power consumption

Insulators that have a larger dielectric constant than silicondioxide (referred to as high-k dielectrics), such as group IV Bmetal silicates e.g. hafnium and zirconium silicates and oxidesare being used to reduce the gate leakage from the 45

nanometre technology node onwards.


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GATE INDUCED DRAIN LEAKAGE (GIDL)

Vgs0

Higher supply voltage and thinner oxide increase GIDL.


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The n+ drain region under the gate is bedepleted and even inverted. This causes field

crowding and the peak.

So field increase, resulting in avalanchemultiplication and band-to-band tunneling.

Thus minority carriers are emitted in the drainregion underneath the gate and leakage currentflows through the substrate.

Thinner oxide, higher Vddenhances the electricfield and therefore increase GIDL.


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GIDL increases with the increase in Vdband Vdg.


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LOWER TRANSCONDUCTANCE

The transconductance of the MOSFET decides its

gain and is proportional to hole or electron mobility.

As MOSFET size is reduced, the fields in thechannel increase and the dopant impurity levelsincrease. Both changes reduce the carrier mobility,

and hence the transconductance.

Velocity saturation of the carriers, limiting thecurrent and the transconductance.


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STRESS INDUCED LEAKAGE CURRENT

Stress Induced Leakage Current (SILC) is an

increase in the gate leakage current of a MOSFET,due to defects created in the gate oxide duringelectrical stressing.

No SILC was observed for thinner films, whilethicker oxides shows large variation due to processinduced charging damage.

The effect of different gate poly-Si etchingprocess in a high density plasma system were alsoevaluated. Only the gate that was etched with anabnormally high bias power over etch process, and

connected to large connection antenna ratio shows


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Channel Length Modulation

The pinch-off point moves toward the source as VDSincreases. The length of the inversion-layer channel becomes

shorter with increasing VDS. ID increases (slightly) with increasing VDS in the

saturation region of operation.

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The effect of channel-length modulation is less for along-channel MOSFET than for a short-channelMOSFET.


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An example of an incoming electron impact ionizing to

produce a new electron-hole pair

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Scaling of MOSFETs and Short Channel Effects