Schoo 1-wee k:s /972 - VTDAvtda.org/docs/computing/SEL/SEL_810ASchool_1971.pdf · 2020. 3. 23. · 2. Power Supplies 1F3 1. BPC 2. BTC/CGP's 3. Mnm~VH Module# 4. Interrupts 1st cabinet

Sel g IOA Schoo (

1-wee k:s /972

nGP1 ~ DATE January 21, 1971

SUBJECT Computer Course & School

Mr. R. L. Jepsen Ml-. R. D. Pilcher

TO Mr. R. D. Kelly Mr. G. R. Frimann Mr. R. E. Praeuner Mr. T. c. Losh Mr. L. G. Gillis

INTER - OFFICE CORRESPONDENCE

FROM Mr. V • K. Patfr, .✓ Mr. M. J. Findlin,,

You are scheduled for a four week SEL 810A Computer Maintenance School begimrlng April 26th, 1971 at Station No. 106, Beatrice, Nebraska. This School assUJ1es that you already have a basic understanding of Computer operation, Computer programming, and logic circuits as covered in the Computer Course lessons which you have received and the attached 8 Lesson book on binary logic. You should complete Computer Course Lessons and the attached bi.D&r;r book prior to the School. With an understanding of these Lessons the Ccaputer School will not be difficult; without this aformation the School will be extremely difficult. If you have any problems or require assistance under-standing these Lessons or parts of these Lessons, please let me know. Th• Lessons contain a considerable 8ll.Ount of information, :au.ch of which is not the easiest to understand, so don't be afraid to ask for help.

The attached Binary Logic Book, Chapter 3, gees into Boolean Algebra in considerable detail. It is not necessary to be able to design circuits via Boolean Algebra but you should understand basic Boolean terminology and operations. 1he attached vrite-up on Boolean ilgebra will assist you in understanding the subject and in completing the Binary Logic Book Lessons.

Copies of Computer Course Lessons l through 4 are alao attached to Mr. G. R. Frimann and Mr. L. G. Gillie's copy of this Memo since they- were not included in the original distribution of the Computer Course.

KIF/gr cc: Mr. c. E. Upson Attach:

_l

CON'l1 ROL

I INTRODUC'l'ION

STUDENT i DATA I PANEL TO DIAGNOSTIC I INTRODUCTION AND I FORJ.VJ1-"'\TS FAMILIARIZATION PROG~"\MS TO COURSE I I PROGRAM ORIENTATION INTRODUCTI~ INTRODUCTION -1- ANALYZING WRITING

TO 810A TO ASSEMBLY DIAGNOSTIC LANGUAGE

INTRODUCTION I INSTRUCTION I PROGRAMS

TO TURBINE CONTROL SYSTEM SET

GENERAL DESCRIPTION OF I RUNNI.NG 810A INSTRUCTION CONTROL I REVIEW DIAGNOSTIC SET PANEL TEST BASIC I PROGRAMS BLOCK DIAGRt"\M WORK LAB CRITIQUE

LAB SESS IO~\J

MEMORY I LOADER ORGANIZATION LAB

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INTRODUCTION TO SYSTEMS

LOGIC

READING LOGIC DRAWINGS AND MAINTENANCE

FLOWCHARTS

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UNIT

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THEORY 'Y.dEORY OF INPUT/OUTPUT SUPPLIES

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C0Jv'J.cl\1UNICATIONS I POWER FAILSAFE

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L OPERATION OPEPJ\.TION

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PROCEDURE FOR ENTERING ABSOLUTE VERSION OF STANDARD BOOTSTRAP PACKAGE - #300000 SHEET 1

START

THUMB-IN BOOTSTRAP

LOADER FROM BLUE CARD "4K"

INSERT TAPE NO.

300000 IN READER

SET PROGRAM

COMPUTER WILL FIALT WHEN TAPE IS LOADED

LOADERS & DUMP NOW RESIDENT IN lV1EMORY

TO PLACE LOADERS IN HIGHER MAPS REFER TO NEXT

PAGE

.re-: :1:-7777, 810B 000000 810A

STARTING ADDRESSES: REL. LOADER='6007 DUMP ='7561 ABS. LOADER='7673

PROCEDURE FOR RELOCATING THE LOADER PACKAGE TO HIGHER MEMORY IvtAPS SHEET 2

ENTER '16000

IN

( START J ~l

EXECUTE OPERATIONS ON SHEET l

INSERT TAPE NO.

300001 IN READER

SET PROGRAM COUNTER = 0 6007

ENTER '36000

IN " ACC. "A" ACC. I

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IDENTIFICATION:

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SOURCE PROGRAM LANGUAGE:

COMPUTER CONFIGURATION:

STORAGE:

SUBROUTINES REQUIRED:

TIMING

USE:

SEL PROGRAM LIBRARY

PROGRAM DESCRIPTION

Mainframe Exercis_er (MFE)

SEL

13 January 1967

Catalog No. 303001A

A fast no-loop program designed to use each of the mainframe instructions in such a way that if a Halt occurs, the operator can tell from the program listing which instruction is malfunctioning.

MNEMB LER - 81 0A

Standard SEL 81 0A

20008

to 23038

30008 to 3021 8 - Not Relocatable

81 0A Mainframe Diagnostic Loading Procedure

Approx. l ms/ cycle

Start at location 20008 , the program will run until halted manually. If a halt occurs consult the listing or halt log using the P- Counter location to find the instruction that failed.

HALT LOG FOR MAINFRAME EXERCISER

P-Counter Location 20063 20118 20203 20233 20308 20343 2041g

Instruction in Error AMA, SOF AMA AMB SOF AME LSL RSA, SMA FLL

of 2 Catalog No. 303001A

20448 FLL 20518 FRA 2053 8 FRA 2061 8 LSA 2065 8 LSA 20713 CLA 21023 FRL 21063, 2107g Cl\1A 21123, 21148 CMA 2117 8 , 21208 CMA 21253, 21273 STB 21343 ABA 21413 OBA 21538 NEG, CNS, SMA 21s18 , 21608 SAS 21633, 21653 SAS 21703, 21718 SAS 22003 FLA, SMA 22163 RSL. FR.A, RNA, TAB,

CLA, IAB, ASC 22223 SNO 22253 SNO 22323 LOB 22363 SMA 2241g IBS 22513, 22548 MPY 22623 MPY, SMA 22618 AMA, SMA, TBA 30038 BRU Indirect 30133 SOF 30163 SOF

METHOD: N/A

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01 00

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0158 0223U 054U0JUO UAC CAT~ 0159 02231 UOUOUJOO HLT 0 60 022 2 l2J023U4 RTN 5P~ CHAR 0161 02233 l,i6102_277__ S,"IA ___ H:10 0162 02~34 v00Uv022 SAZ 0 1 6 3 0 2_~ 3_:;j u :JUD u OU O ____ H L T 0 64 02236 UOUU0005 TA8 0165 02237 jQUOu026 9S 0166 02~40 00000000 HLT

Tt:l SMA E12

0 1 6 9 0 2 2 4 3 ~--SA Z __ _ __ __ _ __ _ 0170 02~44 L8A TE11 0171 02245 MPY Tf12 0172 02246 U61U22/7 SMA Tt10 0173 0?247 UOUOD022 SAl U174 02~50 JOOOuOUO LT

--~'-"'-----"'----~---"-''-~_,,_.,_,,_y __ , ___________ , 8 A ___________ _ SAZ

0177 00000000 HLT LBA F :'1

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T8 A

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________________ SA Z 0188 02~66 UDOUUDOO ~LT u:e9 ~Q2_26l 111ucooo_ dRu 0190 02270 UOUUJOUO T~S1 DATA

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_________ 4,..

uo1~,252 S3 DATA 2S S2 Ll J O 2_~2 2 5_ T E S D /\ T 1 5 5

4 uJlU~OOO S DATA 1 :LOOO'JO

200 IN MULT Y BY 00 SUBTRACT 0Nt:

b SEVENS SUBTRACT 0Nt:

- ·-·-. --

--- -~

00015900 00016000 --000 00 00016200_ 00016300 000 6 00 00016500

__ 0 Q O 16 6 Q O ---00016700

____ o oo 16 a o o _ 00016900 00017000

• ------- ~"--~-~scc. .. --

Q 01 300 ________ O_QQ17 4 O_Q __

00017580 00017600 00017700

001 Q_oo_i e_o ou __ 00018100 0001 200 000 8300 00 8400 00 8500 0001~600 00018700 00018800 00018900 0001~000_ 00019 00 D 019200

0195 02~7~ U8J7/777 TcSb DATA 9 77777 __ 01_£6 02276 i.J014b,3l4_ TES7_UATf\ '146314

U197 02~77 000Uu0U1 Tl::10 DAT~ 1 0 1 9 8 0 2 3 0 lJ U OU O O 2 0 0 _ T l::J_l ___ tJ A TA ' ~ ,JO 0 99 02S01 JOUUu400 TE1 DATA '400 O 2 0 O o 2 0 O 2 U Ou o u 1J O O L iJ C 1 _Z Z L 0201 02303 uooouOGO L0C2 ZZl 0202 02304 ..S::i4LJjOQ_3 __ _(J::!.A_F{ DAC t:D ..... ___ ,. 0203 03000 700USUOO 0RG 1 000 0 2 0 0 3 u O O ..:5 0 0 0 0 1 C A~ U--".-:- 1 0205 0300 S 4Ui232 UAC ~T~

__u_2.D.Q_Q300d UOQO.\JOOO _ .r'

- - --- ------ - - --

c:11 Uc.300 -----~t:12 Oc.3O1 ____ _ -·----·-----·-·--------- - --- - --- -- --·.

LL:JCl U 3U2 LillC2 Ud03 CHAR U23O4 ~AT~ 0300~0,_ ____ _

--- . -·---------- ---------------Rt:0 LJjQlJ3

_____ P_SEV QjQ20 ------------ -- - ---·-------

0NE U.5O21

~

I-: ~

~ 'J ~ ~

\; ~Q._

' .. -1 0 "!J ~ ~

I

II

~

-,

PR

=r::::.-v;~;

TB

UNC JO

PR ! J

. ' u

(CARRY IN) 2

(Vccl 4

(Ct',ftRY OUT)

SM-10 SERIES FULL ADDER

14

8 (ADDEND)

SM-20 SERIES DEPENDENT CARRY - FASLADQ£!_

( \+)INPUT I (DIRECT

!4 CAFhH' IN FROM N-2 0 FROM N-3 STAGE I

_,-fMITTER -~j I STAGE I ( 13 L±.'1 INPUT (CARRY

2~ r c6t:.itCTOR -,- FROM N-1

~~~Z~trR 1, ------~ ~ STAGE)

TERMINALS~ l JI : 1 ' 12 121i~V1N - I ~---7-0 jl FROM N-2 I Du' STAGE! ~ :71

11 rg~E~/1,-.1 (Vee) 4 n~ ,:' --- _97:0~ FROM N-1 STAGE)

!SUMI f·O~ 1 ~iDti! 1 10 I ~J@ ..

(DIOUTI 6 f-

r

\

Div Add

No

Div Sub

Yes T-Tfl I-CRY

Ye3

T-TB ' I-CRY

Yes No T-TB

Yes No T-TB

Process = Load sum t o A ,and shift AB l - · Q = Set LSB of B to ON E 0 - Q = Set LSB of B to ZERO 0 - R = Se,t remainder to ZERO Q ~. l....:.. Q= Add carry during IAB

Carry Out First Add

'T '.llF

T O A B = 0 , ANS FSNI

Table 3-2. Divide Algorithm.

Carry Out

/1 /$/A/ ProL·ess 1-Q

!TRIAi Shift

o-o

IT!{. / AI Process

o-o

ITl"2IAI Shift 1-Q

Carry Out Co rre ct i on s Overflow First Add

1T l>/A ! , ='1one (DIV, IABl /T~!A/ Shift I~

/TiIAI Shift

1-0

/T/

Location Y Even Decode Assembly (Top Boa.rd)

Diode Location Chart for Y Odd Decode Board Assembly (Middle

for Board ( BoUom Board)

I::ormal )?:i:cgram

("""""~"""'"'-~~

;:Inetrnctim~

~l~ 1 I

810A/B

PRIORITY INTERRUPT

PROCESSING

Interrupt Service

Program #1

,_ Instructio _.::::--

# 1

r'«-f ~k'"';"'" ~.~1--~ ~l SPB l .....,Jrns~ructio /i~ (Indirect);:_ . _ r;;,,j # 3 ':l /. /_ /'. / J /' ~I1g1:~r !

, ·-·- - ; "Y'; =x, ·;"~~~~~~;i-1

\ To Next Program

TOI BRU*

Interrupt Service

Program #2

Instructio1\ ±t 2 ' " I ._ ______ :! di \JI

Instructio # 3 !

i / ____ ,__ __ \~/ ~--.

Instructior!

# 4 ! '--~---1

,Jl; Instructio

# 5

IN RR

1~1,1; ')/'S"i

INTt!X"li"tJp,

/} 0 0;(',,f;,s,

OF 7/-f/5

6€7

flf"tbtet0' J/Vff,('£-'/.,JP,-

rfi/ Se:-R//10.? Fl1P Fit)/J

SPt3

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J:'t-':,€ T

/f;,:;.p[o-7 r\e,crt'1ry

/A.-'

l?ES€T

Pt:c(iU[ST

//JTCI/

CotJ T /,A/ti[: tll/ T/-J

Ait'tiJ ·· / /1/ 7-C-R l?I//' r /7,frr;:. ir.7/J/71

i ,,J

C) r: ;,,

l e;u ·, , , 1 1-1 7

,; f ~~

/c

/

810a Auto Start Option

I. :\,t~to start option enables the computer to resume operation when A. c. PD"';J0:r io applied after a power failure if 1) The computer was in the .!0 ttn mode and 2) certain programming techniques are observed prior to,. during and after power loss.

'Fhis option consists of adding P. c. cards 160-100124 (Loe. 23A lRl) , 160-083240-002 (Loe. 25B lRl); changing P. c. card in location 9G lRl from 8296-001 to 8296-002: and adding wire list w. L. 83240 to 1Rl plane.

/

II. Drawings 824201, 824501, 829602, 160-083186, 160-083240~002, 160-100124<

~l~~ Adjustments Note: 29 Pin card extender (8013), Variac, and Weston 0-150 v. A. c. meter are required to perform adjustments.

Verify that Po C. cards 8245 (Loe. lOG lRl) and 8296- (Loe. 9G lRl) adjustmenta are correct as described in 810a tech. manual 303-095000-002 ,PcL'Cc.~grnphs 4··70 through 4-73 and paragraphs 4-82 through 4-83. Pa?'.'c,graph 4~·84 need not be performed as auto-start option does not use output from 8296 pin 5.

Pl. Theory of Operation:

1?" c. card 160-083240 contains c1 relay (Kl) which is a bi-stab] e relay Leo the armature remains in the position to which it was last operated until sufficient current of opposite polarity is applied. Vfuen the computer is in the run mode, the term EEG on pin 16 is ground which caunes Ql and Q4 to conduct. 'I'his current flow causes Kl to set which provides continuity between pin 12 and pin 26.

'.two types of power failure may occur O A) complete loss of A. C" and B) a power dip which is defined as A. c. voltage being less than 95 Volts and greater than 0 Volts.

A. Sequence of events for complete power loss:

L When A. C. power drops to 95 Volts, P. c. card 8296 generates + voltage OFF+ ON pin 6. This signal at next CLll time generates interrupt request OFFZ and start~ 500 microsecond delay on P. C. 8245. The term OFFZ sets PFS interrupt on 824201. When active F. F, on 8242 P. C. is set, the term AFCO+ on pin 24 goes to+ voltage. This term is applied to 160-083240 and prevents Kl from resetting. The computer enters the power dawn interrupt routine and performs necessary housekeepinq functions. After 500 microsecond delav on P. Co 8245 times out, "turn off memory"' Term OZOF+ is generated on 8245 pin 23. This signal g~tes off the data saver P. C. card8639-2 in each memory module (refer to BK memory module logic diagram 53103) . The computer remains in this state , . ..;hile A. C. and D. C. voltages drop to zero.

(

v.

I

2. When A. c. is applied to computer, the term zww+ is immediately generuted on P. c. 83240. This, inturn, generates ICBl thru ICB4 and Z¥4+ terms. These are initial condition pulses that reset all ~ritical latches, flip-flops, registers and force a "HALT" condition. This clearing condition exists for approximately 3.2 seconds. ICB2+ is applied to P. C. 83240 to prevent Kl armature from changing position. At the trailing edge of zww+, a 5 microsecond pulse (O~T+) is produced at pin 26 of 83 240 P. C. via pin 13 ~ 12 a£a- KL This pulse generates an interrupt request (OFFZ) on P. C. 8245 pin 20 and generates a start pulse (Res+CP) on P. C. 160-083186. The computer enter the "run" mode, an interrupt traps to the power up interrupt routine which restores registers and computer operation is resumed.

B. Sequence of events for A. c. power Dip:

1.

2.

When the A. C. voltage drops below 95 volts, the term (OFF) is gated to P. C. 100124 to remove the +16V supplied to P. c;.83240 via Ql and R4 on 100124. Removing +16V from the junction point of Cl 0 R6 on 83240 allows Cl to discharge through CR4 (CRl is ommitted on 83240-002).

The flip~flop (PUD+) is set on P. C. 100124 by the decrease of +16 Volts which is caused by A. c. voltage drop. The term PUD+ is gated to the 83240 card to prevent Kl armature from changing positions due to unreliable voltage levels of AFCO+

When the A. C. voltage rises above 105 volts, the term (OFF) at pin 14 of 100124 P. c. card goes positive allowing +16 volts to be applied to the junction of Cl, R6 on 83240 card which in turn produces Z~M+. Refer to paragraph IV A.2 for sequence of events. The ICB4+ term resets the PUD+ flip-flop and computer operation resumes.

i,Jire List 83240 A Remove 10G08 09G05 A.dd FROM 'I'O FROM TO

25B04 25B24 25Bl7 10G08 25B08 25B18 25Bl5 05G25 22ga. Red l0G26 08F08 04K21 05H25 22ga. Red 08F08 25B26 23A10 25B06 25Bl6 03D24 25B06 25B20 25Bl0 25B14 23A20 25B21 25B08 01Bl5 23Al4 09Gl0 25B54 23Dl6 021313 23A08 25Bl3 25Bl2 23A26 25Bl5

/ f

S~o~t program to verify proper operation of auto-start option

_!,9_~• Octal Code Mnemonic

50 010053 I.AA' 53 51 032054 STA I, '54 52 110052 BRU * 53 000055 '55 54 001000 '1000 55 000000 x--x 56 010055 LAA' 55 57 030072 STA' 72 60 010063 LM'63 61 032064 s·rA I, '64 62 110062 BRU 1': 63 000065 '65 611 001000 '1000 65 000000 x--x 66 010053 LAA'53 67 032054 STA I, '54 70 000035 TOI 71 112072 BRU I, '72 72 000000 x--x

'lII. P1:-ogram will continuously type message 11 turn off 810-then on--program will resume'' Frequently an extra character will be typed as power is dropping due to unreliable TTY operation, this should be ignored.

J.,oc. Octal Code

100 010140 101 032141 102 010142 103 03014 7 104 020143 105 130101 106 002000 107 01214 7 110 170001 111 110110 112 001016 l.13 170001 .114 110113 115 14014 7 116 000026 117 110107 120 110100 121 000000 122 030144 ]_2 3 040145 124 OJ.0146 125 032141 126 lJ 0126 127 000000 130 010140 131 032141

Mnemonic

LAA' 140 STA Io '141 Ll'\A'142 STA' 14 7 LBA' 143 CEU DAC LAA I, '147 AOP BRU *-1 LSL Bo 0 AOP BRU *-1 IMS'147 ms BRU' 107 BRU' 100

x--x STA'] 44 STD'l4S LAA' 14() STA I '141 mm *

x--x Ll\A' J 40 STA I '141

Remarks

Start of program

Unit not ready

Unit not ready

Powe~ down routine Temp 1 Temp 2

Power up routine

;"'.•· Lo~,; Octal Code Mnemonic Remarks

132 010144 LAA' 144 Temp l 133 020145 LBA' 145 'l'emp 2 134 130101 CEU w, 1 135 002000 DAC 136 000035 TOI 137 112121 BRU Io '121 Last addre before P. F. s. J-40 000121 1st Loe. of power down 141 001000 P. F. s./Auto-start interr. loc. 142 000150 Loe. of 1st data word JA3 177752 No. of data words 144 000000 Temp 1 145 000000 Temp 2 146 000127 1st Loe. of power up 147 000000 Loe. of current data word 150 106612 DATA C/R L/F 151 152325 T u 152 151316 R N 153 120317 Sp 0 154 143306 F F 155 120270 Sp 8 156 130660 1 0 157 120255 Sp -160 152310 T H

( 161 142716 E N 162 120317 Sp 0 163 147255 N 164 120320 Sp p 165 151317 R 0 166 143722 G R 167 140715 A M 170 120327 Sp w 171 144 714 1 L 172 146240 L Sp 173 151305 R E 174 151725 s u 175 146705 M E

• UP TO o4 DE.VICE. CONTR-,t.lC,'-

/r')('/

810A/B COURSE

worksheet 1

l ,, List the four major units of the 810A Computer.

a.

b.

c.

d.

2. Describe the functions of the memory unit.

3. Describe the functions of the control unit.

4. Describe the functions of the arithmetic unit.

5. Describe the functions of the input/output unit.

6. How is information transferred between the four major units of the 810A Computer?

7. How are negative numbers expressed?

8. Which units form the mainframe?

9. How many words may be stored in a memory module?

10. How many bits may be stored in one location of memory?

11. What is the minimum number of memory modules in a memory unit.?

12. What is the maximum number of memory modules in a memory unit?

13. List the four elements which comprise each memory module.

a.

b.

c.

d.

14. What types of information are stored in memory?

a.

b.

15. How many memory locations may be addressed by the 13 bit Memory Address Register?

16. How many memory locations may be addressed by the 15 bit Program Counter?

17. What type of information is contained in the memory locations addressed by the Program Counter?

18. ~That is an instruction?

is an operand?

20. What arithmetic functions may be performed by the 810A Computer?

a.

C

2 What logical functions may be performed by the 810A Computer?

22.

a.

a.

b.

c.

C: .Lo

h.

bits of any instruction describe the operation code?

the types of instructions.

What do the XI.M bits mean in instructions using the memory reference format?

a.

c.

25. What is operand address indexing?

26. What is preindexing?

27. What is postindexing?

28. tmat is indirect addressing?

29. What is address mapping?

13-'(

810A/B SOFTWARE COURSE

Instruction Set worksheet 2

1. Given: Instruction=050505 (00505)=007327

(A) =050450

What will be contained in the A accumulator after execution of the above instruction?

2. Given: Instruction=l60606 (00606) =177337

(B) =000441

What will be contained in the B accumulator after execution of the above instruction?

3. Given: Instructio:n.=060606 (00606)=177337

(A) =050450


4. Given: Instruction=070707 (00707)=000020

(A) =050450 (B)=000331

What will be contained in the A & B accumulators after execution of the above instruction?

5. Given: Inatruction=l03010 Instruction@lllll

(11010)=030020 (30020)=000666

(A) =066600 (B)=OOOOOO

What will be contained in the A & B accumulators after execution of the above instruction?

6. Given: Instruction=OOOOOl (A) =066600 (B) =066600


I

7a Given: Instruction=n·lOll Instruction(,· t.'645

(00011) =124242 (10011) =153535


8. Given: Instruction=022022 Instruction@l0646

( 11111) =022000 (00022) =0l.1111 (10022)=022222 (22022)=033333

What will be contained in the B accumulator after execution of the above instruction?

9. Given: Instructi on==033033 Instruction@l0647

(B)=003333 (10033)==021111 (00033)=004444

Where will the contents of the A accumulator be stored after execution of the above instruction?


~ ·where will the contents of the B accumulator be stored after execution of the above instruction?

11~ Given: Instruction=llllll Instruction@l0651

What is the address of the n~:>~~)ill.,~truction to be executed?

12. Given: Instruction=l21212 Instruction@l0652

"'-J'

What is the address of the next instruction to be executed?


(10414) =177776

l j

I



(10515)=065217 (A) =04 7301



s·wi tches=040404



(B) =177775



(A) =177775



(10667)=030344


19. Given: Instruction=000027 (A) ==050450 (B) =000441

() CJ

What will be contained in the A o, B accumulators after execution of the above instruction?

20. Given: Instruction=000030 (A) =050450 (B)=000441

What will be contained in the A & B accumulators after execution of tie above instruction?



22. Giveng Instruction=000020 (A) =050450


23. Given: Instruction=000034 (A)=050450


24. Given: Instruction=000003 (A) =050450


25" Given: Instruction=000004 (A) ==050450 (B)=000441

What will the A&. B accumulators contain after execution of the above instruction?

26~ Given: Instruction=000005 (A) =050450 (B)=000441

27.

What will the A & B accumulators contain after execution of the above instruction?

Given: Instruction=000006 (A) =050450 (B) =000441

\~~at will the A & B accumulator contain after execution of the above instruction?


What will the A & B accumulators contain after execution of the above instruction?

29. Given: rnstruction=000612 (A) =050450 (B)=000441

What will the A 8, B accumulators contain after execution of the above instruction?

30. Given: Instruction=000715 (A) =050450 (B) =000441

"What will the A & B accumulators contain after execution of the above instruction?


·what will the A & B accumulators contain after execution of the above ins.truction?


vfuat will the A & B accumulators contain after execution of the above instruction?


vlhat will the A & B accumulators contain after execution of the next instruction?


C)

What v1ill the A & B accumulators contain after execution of the next instruction?

Documents

Schoo 1-wee k:s /972 - VTDAvtda.org/docs/computing/SEL/SEL_810ASchool_1971.pdf · 2020. 3. 23. · 2. Power Supplies 1F3 1. BPC 2. BTC/CGP's 3. Mnm~VH Module# 4. Interrupts 1st cabinet