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5-1
Instruction Cycle Instruction Cycle
1) Instruction Fetch from Memory 2) Instruction Decode 3) Read Effective Address(if indirect addressing mode) 4) Instruction Execution 5) Go to step 1) : Next Instruction[PC + 1]
Instruction Fetch : T0, T1
T0 = 1» 1) Place the content of PC onto the bus by making the bus selection inputs S2S1S0=010» 2) Transfer the content of the bus to AR by enabling the LD input of AR
PCART :0
1],[::
1
0
PCPCARMIRTPCART
5-2
T1 = 1» 1) Enable the read input memory» 2) Place the content of memory onto the bus by making S2S1S0= 111» 3) Transfer the content of the bus to IR by enable the LD input of IR» 4) Increment PC by enabling the INR input of PC
1],[:1 PCPCARMIRT
Instruction Decode : T2
IR(12-14)에 따라 Fig. 5-6 에서 D0 - D7 출력
Instruction Execution : T3, T4, T5, T6D7=1 Register(I=0) D7I’T3(Execute)
I/O (I=1) D7IT3 (Execute)D7=0 : Memory Ref. Indirect(I=1) D7’IT3( )
Direct (I=0) nothing in T3
Register 와 I/O 명령은 T3에서 실행되며 Memory Ref. 명령은 T3에서 Operand의 effective address를 읽음
Memory Ref. 명령은종류에따라 T4, T5, T6을 갖음 :
)15(),110(),1412(,....,: 702 IRIIRARIRDecodeDDT
][ARMAR
Read effectiveAddress111
)1412(
IR
Op.code Address Di/Indirect
5-3
IR
Memory unit
LD
s2
s1
s0
Bus
7
Common bus
5
Clock
Read
Address
Memory unit
PC
INR
2
AR
LD
1
T1=1T0=1 0
10
111
5-4
StartSC 0
Executememory- reference
instructionSC 0
Decode operation code in IR(12- 14)AR IR(0- 11), I I(15)
NothingExecuteinput- outputinstruction
SC 0
AR M[ AR]Executeregister- reference
instructionSC 0
IR M[ AR] , PC PC+1
AR PC
I
I
I
T0
T3T3T3T3
T2
T1
(Register or I/O) = 1 0 = (Memory- reference
0 = (register)(I/O) = 1 (indirect) = 1 0 = (direct)
Fig. Flowchart for instruction cycle(initial)
5-5
Register Ref. Instruction r = D7I’T3 : 공통항 IR(i) = Bi IR(0 -11) B0 - B11 : 12 개의 Register Ref.
Instruction (Tab. 5-3)
5-6 Memory Ref. InstructionD7 : Register or I/O = 1 D6 - D0 : 7 개의 Memory Ref.
Instruction(Tab. 5-4) AND to AC
ADD to AC
LDA : memory read
Address 로사용되지않음
IR(12,13,14)= 111
0,:][:
50
40
SCDRACACTDARMDRTD
0,,:][:
51
41
SCCEDRACACTDARMDRTD
out
0,:][:
52
42
SCDRACTDARMDRTD
5-6
STA : memory write
BUN : branch unconditionally
BSA : branch and save return address
Return Address : save return address ( 135 21 ) Subroutine Call : Fig. 5-10
ISZ : increment and skip if zero
Control Flowchart : Fig. 5-11 Flowchart for the 7 memory reference instruction
» The longest instruction : ISZ(T6)» 따라서 3 bit Sequence Counter로 구현가능(현재 4 비트는 확장에 대비함)
0,][:43 SCACARMTD
0,:44 SCARPCTD
0,:1,][:
55
45
SCARPCTDARARPCARMTD
0),(136)(136:1135)(136),(21]135[:
55
45
SCARPCTDARPCMTD
Fig. 5-10 Example of BSA
0 BSA 135next instruction
21(return address)
Subroutine
1 BUN 135
PC = 10PC = 21
135PC = 136
0),1()0(,][:1:][:
66
56
46
SCPCPCthenDRifDRARMTDDRDRTD
ARMDRTD