Departement Elektriese, Elektroniese

en Rekenaar-Ingenieurswese

Semester Toets 2 Invulvraestel

Kopiereg voorbehou

Vakkursus ERS220

22 September 2011

Student se besonderhede:

Student's details:

Van (opsioneel):

Surname (optional): MEMO

Voorname (opsioneel):

First name (optional):

Tel. nr. gedurende toetsreeks:

Tel no. during test series:

Toetsinligting:

Test information:

Maksimum punte:

Maximum marks: 100

Duur van vraestel:

Duration of paper: 90 minutes

90 minute

Totale aantal bladsye (hierdie blad ingesluit):

Total numer of pages (including this page):

1. The examination regulations of the University of Pretoria apply.

Die eksamenregulasies van die Universiteit van Pretoria geld.

2. No programmable calculators are allowed.

Geen programmeerbaar sakrekenaars word toegelaat nie.

3. No notes are allowed.

Geen notas word toegelaat nie.

4. Show all calculations.

Toon all berekeninge.

5. Complete all the sections.

Voltooi al die afdelings.

Examiner(s):

Eksaminator(e): P.A. Jansen van Vuuren

Departement Elektriese, Elektroniese

Ingenieurswese

Department of Electrical,

and Computer Engineering

Semester Test 2Fill in paper

Copyright reserved

Course ERS22022 September

MEMO Studentenommer:

Student number:

Tel. nr. na toetsreeks:

Tel. no. after test series:

Volpunte:

Full marks: 90

Open / closed book:

Oopboek / toeboek:

Closed

Toe

Totale aantal bladsye (hierdie blad ingesluit):

this page):

13 Punt:

Mark:

BELANGRIK- IMPORTANT

The examination regulations of the University of Pretoria apply.

Die eksamenregulasies van die Universiteit van Pretoria geld.

No programmable calculators are allowed.

Geen programmeerbaar sakrekenaars word toegelaat nie.

P.A. Jansen van Vuuren

1

Department of Electrical, Electronic

and Computer Engineering

Semester Test 2

Fill in paper

Copyright reserved

Course ERS220 September 2011

90

Closed

Toe

ERS 220 Semester Test 2 2011 2

Section A: Combinational Logic Design Principles [40]

Switching Algebra Theorems / Omruiling Algebra Teorië

1. Prove theorem 11 using the axioms and the other theorems above. / Bewys teorie 11deur gebruik te

maak van die aksiomas en die ander teorië hier bo. (10)

X.Y +X’.Y + Y.Z = X.Y + X’.Z + Y.Z(X+X’)

= X.Y + X’.Z + Y.Z.X+ Y.Z.X’

= (X.Y + X.Y.Z) + (X’.Z + X’.Z.Y)

= X.Y(1 + Z) + X’.Z(1+Y)

= X.Y + X’.Z

2

2

2

2

2

ERS 220 Semester Test 2 2011 3

2. Given the following equation. / Gegee die volgende vergelyking.

F = A’.B’.C.D + A’.B’.C.E + B’C.E + A’.C’.D.E + B.C.E + A.B’ + A’C.D.E +

A.B’C’.D + A’.D.E’

2.1 Simplify the above equation using the switching algebra theorems given above. Indicate which

theorem, if any, is being used at each step. / Vereenvoudig die vergelyking hierbo deur gebruik te

maak van die omruiling algebra teorië gegee hierbo. Dui die teorie wat gebruik word by elke stap

aan, indien ‘n teorie gebruik word. (10)

= A’.B’.C.D + (A’ + 1)B’C.E + B.C.E+ A’.C’.D.E + A’C.D.E + (C’.D + 1).A.B’ +

A’.D.E’ (T6,T8){+T2}

= A’.B’.C.D + (B’ + B).C.E+ (C’ + C).A’.D.E + A.B’ + A’.D.E’ (T8){+T5}

= A’.B’.C.D + C.E+ (E + E’). A’.D + A.B’ (T6,T8){+T5}

= (A’.D).B’.C+ (A’.D) + C.E + A.B’ (T6’)

= (1 + B’.C).A’.D + C.E + A.B’ (T8){+T2}

= A’.D + C.E + A.B’

2

2

2

2

1

1

ERS 220 Semester Test 2 2011 4

3. Given the following circuit. / Gegee die volgende stroombaan.

3.1 Complete the following truth table. Hint: Use all the input combinations. / Voltooi die

waarheidstabel. Wenk: Gebruik al the toevoer kombinasies. (8)

A B C F

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

1

1

1

1

1

1

1

1

ERS 220 Semester Test 2 2011 5

4. For the product-of-sums function H below, use the Karnaugh maps to derive the minimum sum-of-

products expression. / Vir die produk-van-somme funksie H hieronder, gebruik die Karnaugh

diagram om die minium som-van-produkte uitdrukking af te lei. (12)

H = �������(0,4,7,10,11,12,15,16,17,22,26,27,28,30,32,33,36,37,39,42,43,45,47,48,

49,52,53,54,55,58,59,61,62,63) + d(1,6,14,19,20,38,40,44,46,50,51,60)

H =

4

ERS 220 Semester Test 2 2011 6

Section B: Hardware Description Language [20]

1. For the following VHDL program find 5 syntax errors. / Vir die volgende VHDL program vind 5

sintaks foute. (5)

library ieee;

-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions

use ieee.std_logic_1164.all;

-- SIGNED and UNSIGNED types, -- and relevant functions

use ieee.numeric_std.all;

entity left is

port

(

-- Output ports

fun_one : out std_logic_vector(0 to 2);

fun_two : out std_logic_vector(0 to 2);

-- Input ports

select : in std_logic_vector(0 to 3);

-- Inout ports

hash : in std_logic_vector(0 to 3);

);

end left;

architecture behaviour of left is

begin

process(select)

begin

if select = "0110" then

FUN_one <= hash XOR hash;

fun_two <= hash and hash;

elseif select = "1010" then

fun_one <= hash OR hash;

fun_two <= hash nand hash;

else

fun_one <= "000";

fun_two <= "000";

endif;

end process;

end behaviour;

ERS 220 Semester Test 2 2011 7

left => keyword

select => keyword

hash : in std_logic_vector (0 to 3); => should not end with ;

elseif => elsif

endif => end if

2. The following VHDL code simulates a circuit that uses a 74x138 (3-to-8 binary decoder). Complete

the following truth table describing the code. / Die volgende VHDL kode simileer ‘n stroombaan wat

gebruik maak van ‘n 74x138 (3-to-8 binere decoder). Voltooi die volgende waarheidstabel wat the

kode beskryf. (10)

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity dec_FG_data is

port

(

-- Input ports

A,B,C : in std_logic;

-- Output ports

F : out std_logic;

G : out std_logic

);

end dec_FG_data;

1

1

1

1

1

ERS 220 Semester Test 2 2011 8

architecture behavior of dec_FG_data is

signal dec_out : std_logic_vector(0 to 7);

signal temp1,temp2 : std_logic;

signal sel : std_logic_vector(0 to 2);

begin

sel <= (A,B,C);

dec_out <= -- Begin Decoder Statement

"11111110" when sel = "111" else

"11111101" when sel = "011" else

"11111011" when sel = "101" else

"11110111" when sel = "001" else

"11101111" when sel = "110" else

"11011111" when sel = "010" else

"10111111" when sel = "100" else

"01111111" when sel = "000" ; -- End Decoder Statement

temp2 <= not(dec_out(7)) OR not(dec_out(4)) OR not(dec_out(1)) OR not(dec_out(0));

temp1 <= not(dec_out(6)) OR not(dec_out(3)) OR not(dec_out(1)) OR not(dec_out(0));

F <= temp2;

G <= temp1 OR temp2;

end behavior;

A B C F G

0 0 0 1 1

0 0 1 1 1

0 1 0 0 0

0 1 1 0 1

1 0 0 1 1

1 0 1 0 0

1 1 0 0 1

1 1 1 1 1

1 1

1 1

1

1 1

1

1 1

ERS 220 Semester Test 2 2011 9

The following VHDL code simulates a combinational circuit. Derive a circuit diagram for this code. / Die

volgende VHDL kode simileer ‘n kombinasie stroombaan. Skep ‘n stroombaan vir die gegewe kode. (10)

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity com_G is

port

(

-- Input ports

X,Y,Z : in std_logic;

-- Output ports

O_one : out std_logic

);

end com_G;

architecture behavior of com_G is

signal P_one,P_two,P_three,P_four,P_five,P_six : std_logic;

begin

P_one <= (P_two OR P_three) AND not(Z);

P_two <= not(X) AND not(Y);

P_three <= X AND Y;

O_one <= Z OR P_one;

end behavior;

X

Y

Z O_one

Unsimplified

Simplified

Simplified

6

+2 +2

ERS 220 Semester Test 2 2011 10

Section C: Combinational Logic Design Practices [40]

1. Given the following Boolean function. / Gegee die volgende Bool funksie.

F = ���� , �, �, �, �, , �, �� Implement the function F using a single 74x151 MUX and one inverting gate. / Implementeer die

funksie F deur gebruik te maak van ‘n enkel 74x151 MUX en een omkeer hek. (10)

ERS 220 Semester Test 2 2011 11

2. Given the following Boolean function. / Gegee die volgende Bool funksie.

F = ��������, �, �, , �, ��, ��, ��� Implement the function F using four 74x138 decoders, one inverter and one 8 input NAND gate. /

Implementeer die funksie F deur gebruik te maak van vier 74x138 dekodeerders, een omkeer hek en

een 8 inset NEN hek. (15)

ERS 220 Semester Test 2 2011 12

3. Given the following Boolean function. / Gegee die volgende Bool funksie.

F = ��������, �, �, �, �, �, �, � , ��, ��, ��, � �

A B C D E F

0 0 0 0 0 0 1

1 0 0 0 0 1 0

2 0 0 0 1 0 1

3 0 0 0 1 1 1

4 0 0 1 0 0 0

5 0 0 1 0 1 0

6 0 0 1 1 0 0

7 0 0 1 1 1 0

8 0 1 0 0 0 0

9 0 1 0 0 1 1

10 0 1 0 1 0 1

11 0 1 0 1 1 0

12 0 1 1 0 0 0

13 0 1 1 0 1 0

14 0 1 1 1 0 0

15 0 1 1 1 1 0

16 1 0 0 0 0 0

17 1 0 0 0 1 0

18 1 0 0 1 0 1

19 1 0 0 1 1 1

20 1 0 1 0 0 0

21 1 0 1 0 1 1

22 1 0 1 1 0 0

23 1 0 1 1 1 0

24 1 1 0 0 0 0

25 1 1 0 0 1 1

26 1 1 0 1 0 0

27 1 1 0 1 1 0

28 1 1 1 0 0 1

29 1 1 1 0 1 1

30 1 1 1 1 0 0

31 1 1 1 1 1 1

5

ERS 220 Semester Test 2 2011 13

3.1 Implement function F using one 74x151 MUX, one 74x138 decoder, one inverting gate and one multiple

input NAND gate. / Implementeer funksie F deur gebruik te maak van een 74x151 MUX, een 74x138

dekodeerder, een omkeer hek en een NEN hek. (20)

******************* END / EINDE *******************

6

3