Semiconductor Manufacturing Technologyweng/courses/IC_2007... · 2020. 4. 23. · Bernas ion source assembly Arc chamber Extraction electrode E x t r a c t i o n a s s e m b l y Ion

© 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda

Semiconductor Manufacturing Technology

Michael Quirk & Julian Serda© October 2001 by Prentice Hall

Chapter 17

Doping Processes

Semiconductor Manufacturing Technology

Michael Quirk & Julian Serda© October 2001 by Prentice Hall

Chapter 17

Doping Processes


Common Dopants Used in Semiconductor Manufacturing

Acceptor DopantGroup IIIA

(P-Type)

SemiconductorGroup IVA

Donor DopantGroup VA(N-Type)

Element AtomicNumber Element Atomic

Number Element AtomicNumber

Boron (B) 5 Carbon 6 Nitrogen 7

Aluminum 13 Silicon (Si) 14 Phosphorus (P) 15

Gallium 31 Germanium 32 Arsenic (As) 33

Indium 49 Tin 50 Antimony 51

Table 17.1


CMOS Structure with Doped Regions

n-channel Transistorp-channel Transistor

LI oxide

p– epitaxial layer

p+ silicon substrate

STISTI STIn+ p+

p-welln-well

p+p–p+p–

p+

n+n–n+

n–

n+

A

B

CE

F

DG

H

K L I JMMN O

n+n

n++p+p

p++

Figure 17.1


Common Dopant Processes in CMOS Fabrication

Process Step Dopant MethodA. p+ Silicon Substrate B Diffusion

B. p- Epitaxial Layer B Diffusion

C. Retrograde n-Well P Ion ImplantD. Retrograde p-well B Ion ImplantE. p-Channel Punchthrough P Ion ImplantF. p-Channel Threshold Voltage (VT) Adjust P Ion ImplantG. p-Channel Punchthrough B Ion ImplantH. p-Channel VT Adjust B Ion ImplantI. n-Channel Lightly Doped Drain (LDD) As Ion ImplantJ. n-Channel Source/Drain (S/D) As Ion ImplantK. p-Channel LDD BF2 Ion ImplantL. p-Channel S/D BF2 Ion ImplantM. Silicon Si Ion Implant

N. Doped Polysilicon P or B Ion Implantor Diffusion

O. Doped SiO2 P or B Ion Implantor Diffusion

Table 17.2


Ion Implant in Process Flow

Used with permission from Lance Kinney, AMD

Implant

Diffusion

Test/Sort

Etch

Polish

PhotoCompleted wafer

Unpatternedwafer

Wafer startThin Films

Wafer fabrication (front-end)

Hard mask (oxide or nitride)Anneal after implant

Photoresist mask

Figure 17.2


Doped Region in a Silicon Wafer

OxideOxide

p+ Silicon substrate

Dopant gas

N

Diffused region

Figure 17.3


Diffusion

• Diffusion Principles– Three Steps

• Predeposition• Drive-in• Activation

– Dopant Movement– Solid Solubility– Lateral Diffusion

• Diffusion Process– Wafer Cleaning– Dopant Sources


Dopant Diffusion in Silicon

Displaced silicon atom in interstitial site

Si Si Si

Si Si

Si Si SiSi

c) Mechanical interstitial displacement

Si Si Si

Si Si Si

Si Si Si

a) Silicon lattice structure b) Substitutional diffusion

Si Si Si

Si Si

Si Si Si

VacancyDopant

d) Interstitial diffusion

Si Si Si

Si Si

Si Si Si

Si

Dopant in interstitial site

Figure 17.4


Solid Solubility Limits in Silicon at 1100°C

Dopant Solubility Limit (atoms/cm3)Arsenic (As) 1.7 x 1021

Phosphorus (P) 1.1 x 1021

Boron (B) 2.2 x 1020

Antimony (Sb) 5.0 x 1019

Aluminum (Al) 1.8 x 1019

Table 17.3


Diffusion Process

Eight Steps for Successful Diffusion:1. Run qualification test to ensure the tool meets production

quality criteria.2. Verify wafer properties with a lot control system.3. Download the process recipe with the desired diffusion

parameters.4. Set up the furnace, including a temperature profile.5. Clean the wafers and dip in HF to remove native oxide.6. Perform predeposition: load wafers into the deposition furnace

and diffuse the dopant.7. Perform drive-in: increase furnace temperature to drive-in and

activate the dopant bonds, then unload the wafers.8. Measure, evaluate and record junction depth and sheet

resistivity.


Typical Dopant Sources for Diffusion

Dopant Formula of Source Chemical NameArsenic (As) AsH3 Arsine (gas)

Phosphorus (P) PH3 Phosphine (gas)

Phosphorus (P) POCl3 Phosphorus oxychloride (liquid)

Boron (B) B2H6 Diborane (gas)

Boron (B) BF3 Boron tri-fluoride (gas)

Boron (B) BBr3 Boron tri-bromide (liquid)

Antimony (Sb) SbCl5 Antimony pentachloride (solid)

SEMATECH “Diffusion Processes,” Furnace Processes and Related Topics, (Austin, TX: SEMATECH, 1994), P. 7.

Table 17.4


Ion Implantation

• Overview– Controlling Dopant Concentration– Advantages of Ion Implant– Disadvantages of Ion Implant

• Ion Implant Parameters– Dose– Range


Controlling Dopant Concentration and Depth

a) Low dopant concentration (n–, p–) and shallow junction (xj)

MaskMask

Silicon substrate

xj

Low energyLow doseFast scan speed

Beam scan

Dopant ions

Ion implanter

b) High dopant concentration (n+, p+) and deep junction (xj)

Beam scan

High energyHigh doseSlow scan speed

MaskMask

Silicon substrate

xj

Ion implanter

Figure 17.5


General Schematic of an Ion Implanter

Ion source

Analyzing magnetAcceleration columnIon beam

Plasma

Process chamber

Extraction assembly

Scanning disk

Figure 17.6


Advantages of Ion Implantation(from Table 17.5)

1. Precise Control of Dopant Concentration2. Good Dopant Uniformity3. Good Control of Dopant Penetration Depth4. Produces a Pure Beam of Ions5. Low Temperature Processing6. Ability to Implant Dopants Through Films7. No Solid Solubility Limit

Table 17.5


Classes of Implanters

Class of ImplanterSystem Description and Applications

Medium Current

• Highly pure beam currents <10 mA.• Beam energy is usually < 180 keV.• Most often the ion beam is stationary and the wafer is scanned.• Specialized applications of punchthrough stops.

High Current

• Generate beam currents > 10 mA and up to 25 mA for high doseimplants.

• Beam energy is usually <120 keV.• Most often the wafer is stationary and the ion beam does the

scanning.• Ultralow-energy beams (<4keV down to 200 eV) for implanting

ultrashallow source/drain junctions.

High Energy• Beam energy exceeds 200 keV up to several MeV.• Place dopants beneath a trench or thick oxide layer.• Able to form retrograde wells and buried layers.

Oxygen Ion Implanters • Class of high current systems used to implant oxygen in silicon-on-insulator (SOI) applications.

Table 17.6


Range and Projected Range of Dopant Ion

Incident ion beam

Silicon substrate

Stopping point for a single ion

Rp∆Rp dopantdistribution

Figure 17.7


Projected Range Chart

Implantation Energy (keV)

Proj

ecte

d R

ange

, Rp

(µm

)

10 100 1,0000.01

0.1

1.0

B P AsSb

Implanting into Silicon

Figure 17.8

Redrawn from B.El-Kareh, Fundamentals of Semiconductor Processing Technologies, (Boston: Kluwer, 1995), p. 388


Energy Loss of an Implanted Dopant Atom

Si Si Si Si Si Si

Si Si Si Si Si Si

Si Si Si Si Si Si

Si Si Si Si Si

Si

X-rays

Electronic collision

Atomic collision

Displaced Si atom

Energeticdopant ion

Silicon crystal lattice

Figure 17.9


Crystal Damage Due to Light and Heavy Ions

Light ion impact Heavy ion impact

Figure 17.10


Ion Implanters

• Ion Source• Extraction and Ion Analyzer• Acceleration Column• Scanning System• Process Chamber• Annealing• Channeling• Particles


Schematic of Ion Source Chamber

Used with permission from Applied Materials Technology, Precision Implanter 9500Figure 17.11

Extraction assembly

Source chamber

Turbo pump

Ion source insulator

Bernas ion source assembly

Arc chamber

Extraction electrodeEx

tract

ion

asse

mbl

y

Ion beam


Schematic of Bernas Ion SourceFront Plate

Aperture

Arc Chamber

Filament

Electron repeller

Gas inlets

5 V

Electron reflector

Anode +100 V

Arc chamber

Vapor nozzle

Oven

Gas feed tube

DI cooling water inlet

Dopant gas inlet

Used with permission from Applied Materials Technology, Precision Implanter 9500

Figure 17.12


Interaction of ion Source and Extraction Assemblies

Used with permission from Applied Materials Technology, Precision Implanter 9500

+++++++

+++++++

+++++++

+++++++

------------

------------

NS

NS

120 VArc

Extraction AssemblyIon Source

60 kVExtraction

2.5 kVSuppression

Source magnet supply

5VFilament

To PA+Ion beam

Terminal reference (PA voltage)

Suppression electrodeGrounded electrode

Arc chamber

Figure 17.13


Analyzing Magnet

Graphite

Ion source

Analyzing magnet

Ion beam

Extraction assembly

Lighter ions

Heavy ions

Neutrals

Figure 17.14


Dose Versus Energy Map

Proximity gettering

Present applicationsEvolving applications

Poly doping

Source/drainDamageengineering

Buried layers

Retrogradewells

Triple wells

Vt adjust

Channel and drain engineering

0.1 1 10 100 1000 10,000

1016

1011

1012

1013

1014

1015

1017

Energy (keV)

Dos

e (a

tom

s/cm

2 )

Used with permission from Varian Semiconductor Equipment

Figure 17.16


Linear Accelerator for High-Energy Implanters

Source

Atomic mass analysis magnet

Linear acceleratorFinal energy analysis magnet

Scan disk

Wafer

Figure 17.17


Space Charge Neutralization

++ ++++

++

+

+

+

+

+

+++

+

+

+ +

+

+

+ +

+

Cross section of beamwith space charge neutralization

++ +++

+

+

+

+

+

+

++

+

+

+

+

+

+ +

+

+

+ +

+

Cross section of beam blow-up

Dopant ion Secondary electron

Figure 17.18


Neutral Beam Trap

Source

Analyzing Magnet

Accelerator

Neutral beam trap

Focussinganode

Y-axisdeflection X-axis

deflection

Neutral beam path

Wafer

Ion beam

Grounded collector plate

Used with permission from Varian Semiconductor Equipment

Figure 17.19


Electrostatic Ion Beam Scanning of Wafer

+ Ion beam

Y-axisdeflection

X-axisdeflection

Wafer

Twist Tilt

High frequency X-axis deflection

Low frequency Y-axis deflection

Figure 17.20


Implant Shadowing

Resist

a) Mechanical scanning with no tilt

Ion beam

b) Electrostatic scanning with normal tilt

Resist

Ion beam

Figure 17.21


Electron Shower for Wafer Charging Control

Adapted from Eaton NV10 ion implanter, circa 1983

+

+

+++

+ +

+ ++

+

++

+

+

+

+ ++

+

+++

+

+

+

+

++ +

++ + ++

+

+

+

+ +

+

+

Ion beam

-Biased aperture

Electron gun

Secondary electron target

Secondary electrons

+Ion - electronrecombination

Wafer

Figure 17.23


Plasma Flood to Control Wafer Charging

-Biasedaperture

Ion beam

Neutralized atoms

Wafer scan direction

Current(dose)

monitorPlasma electron

flood chamber

Argon gas inlet

Electron emission

Chamber wall

+

+

+

++

+ ++ ++

+

+

+

++ ++ ++

+ + ++

+

+

S

N

S

N+ +

+ + +

+

+

+

ArAr

Ar

Figure 17.24


Faraday Cup Beam Current Measurement

Redraawn from S. Ghandhi, VLSI Fabricaton Principles: Silicon and Gallium Arsenide, 2d ed., (New York: Wiley, 1994), p. 417

Scanning disk with wafers

Scanning direction

Faraday cup

Suppressor aperture

Current integrator

Sampling slit in disk

Ion beam

Figure 17.26


Annealing of Silicon Crystal

Repaired Si lattice structure and activated dopant-silicon bonds

b) Si lattice after annealinga) Damaged Si lattice during implant

Ion Beam

Figure 17.27


Silicon Lattice Viewed Along <110> Axis

Used with permission from Edgard Torres Designs

Figure 17.28


Ion Entrance Angle and Channeling

Used with permission from Edgard Torres Designs

<111><100> <110>

Figure 17.29


Implantation Damage from Particulate Contamination

MaskMask

Silicon Substrate

Beam scan

Ion implanter

Particle creates a void in implanted area

Figure 17.30


Ion Implant Trends in Process Integration

Examples of Different Implant Processes• Deep buried layers• Retrograde wells• Punchthrough stoppers• Threshold voltage adjustment• Lightly doped drain (LDD)• Source/drain implants• Polysilicon gate• Trench capacitor• Ultra-shallow junctions• Silicon on Insulator (SOI)


Buried Implanted Layer

Figure 17.31

n-well p-well

p− Epi layer


p+ Buried layer

Retrograde wells


Retrograde Well

n-well p-well

p+ Buried layer


n-type dopant p-type dopant

p++n++

Figure 17.32


Punchthrough Stop

n-well p-well

p+ Buried layer



p+

p++n+

n++

Figure 17.33


Implant for Threshold Voltage Adjustment

n-well p-well

p+ Buried layer



p+

p++

pn+

n++

n

Figure 17.34


Source-Drain Formations

+ + + + + + + + - - - - - - - - - -+ + + ++ + + + + + + ++ + + +- - - -- - - - - - - -- - - -

n-well p-well

p+ Buried layer


p+ S/D implant n+ S/D implantSpacer oxide

DrainSource DrainSource

b) p+ and n+ Source/drain implants(performed in two separate operations)

+ + + + + + + + - - - - - - - - - -

n-well p-well

p+ Buried layer


p-channel transistorp– LDD implant

n-channel transistorn– LDD implant

DrainSource Drain Source

Poly gate

a) p– and n– lightly-doped drain implants(performed in two separate operations)

Figure 17.35


Dopant Implant on Vertical Sidewalls of Trench Capacitor

n+do

pant

n+

p+

Tilted implantTrench for

forming capacitor

Figure 17.36


Ultra-Shallow Junctions

Figure 17.37

180 nm

20 Å gate oxide54 nm arsenic implanted layer

Poly gate


CMOS Transistors with and without SIMOX Buried Oxide Layer

a) Common CMOS wafer construction

n-well p-well

Epi layer

Silicon substrate

b) CMOS wafer with SIMOX buried layer

n-well p-well

Implanted silicon dioxide

Silicon substrate

Silicon substrate

Figure 17.38

Documents

Semiconductor Manufacturing Technologyweng/courses/IC_2007... · 2020. 4. 23. · Bernas ion source assembly Arc chamber Extraction electrode E x t r a c t i o n a s s e m b l y Ion