Abstract - Semiconductor Process and Device Modeling is asenior / graduate level course on the application of simulationtools for design and verification of microelectronic processes andoperation of semiconductor devices. The goal of the course is toprovide a more in-depth understanding of complex processes anddevice physics through the use of simulation tools.Silvaco-SUPREM (Athena/Atlas) is the primary process anddevice simulation tool used throughout the course. The courseexplores the various models that are used for front-end siliconprocesses, emphasizing the importance of complex interactionsand 2-D effects as devices are scaled deep-submicron. Electricaldevice simulation and parameter extraction provides a study onhow changes in the device structure can influence deviceoperation. The investigation continues to the circuit levelthrough modifications of SPICE model parameters and analogcircuit simulation.

I. INTRODUCTION

Process and device simulation is an important part of themicroelectronic engineering curriculum at RIT. The first partof this paper will give an overview of the topics discussed inthe course, and how the simulation tools are used toinvestigate various process and device effects. In addition tothe laboratory exercises, individual student projects that havebeen investigated will also be discussed. The second part willpresent results from a recent full-class investigation ondeveloping a baseline 2µm CMOS process. Variousprocessing considerations were discussed as the baselineprocess was assembled. A tolerance analysis was performedusing Athena/Atlas simulation in order to develop a robustprocess that yielded consistent device results. Once a finalprocess flow was decided, electrical parameters (SPICElevel-2) were extracted from electrical simulation results in amanual/iterative fashion. The operation of actual fabricateddevice structures (fabricated at RIT, outside of this class) wasused to verify the simulation models. The baseline processwas then modified as necessary, using simulation to explorehow to scale the devices down to submicron dimensions.Simulated device performance results were compared totheoretical and empirical predictions.

II. EMCR604/704 - SEMICONDUCTOR PROCESS & DEVICE MODELING

A course titled "Semiconductor Process & DeviceModeling" (RIT catalog EMCR604/704) is taught as arequired graduate course / undergraduate elective to studentsthat are enrolled in the M.S. and B.S. programs inMicroelectronic Engineering. The course provides anin-depth study on the use of numerical simulation to modelcomplex processes (i.e. process interactions, non-equilibriumeffects) and electrical operation. This section will describethe topics, and highlight the important focal points of thelaboratory exercises.

A. Numerical Solutions

The course begins with the use of numerical solutions tomodel silicon processes. Although the students are introducedto SUPREM process simulation quite early in themicroelectronic engineering p rogram [1], a full appreciationof the power of numerical simulation is not usually realizeduntil the student is at the senior or graduate level. Reference[2] is the key resource for the lecture material. Differentialequations that describe the mechanisms of front-end siliconprocesses (i.e. oxidation and diffusion) are reviewed, and thesolution to these using numerical methods are discussed. Thestudents become familiar with descretization in space andtime, and the ability of the simulation tool to solve a given setof coupled equations at each node defined in the structuremesh. Laboratory exercises involve simulating oxidation anddiffusion processes, while exploring the influence of meshdensity and models of varying degrees of complexity. Thetradeoff between model accuracy and simulation time isobserved in comparing the Fermi model (default method,doping concentration dependent diffusivity, thermalequilibrium defect concentrations) and fully-coupled models(considers complex interactions between dopants and defects,non-equilibrium conditions).

1

Semiconductor Process and Device Modeling: A Graduate Course /Undergraduate Elective in Microelectronic Engineering at RIT

Karl D. Hirschman, Jeremiah Hebding, Robert Saxer and Keith TabakmanDepartment of Microelectronic Engineering

Rochester Institute of Technology82 Lomb Memorial Drive

Rochester, NY 14623-5604kdhemc@rit.edu

B. Process Simulation

Although closed-form solutions to the differentialequations that describe oxidation and diffusion are available,the conditions required for the solutions to be valid are quiteoften not satisfied. In addition, there are usually simultaneousevents taking place such as in the case of growing thermalSiO2 (i.e. moving silicon interface, dopant segregation, dopantdiffusion) which simplified solutions cannot accommodate.Non-equilibrium levels of defects (vacancies and/orinterstitials) that are supported by certain processphenomenon, and the interactions that they can have withdopant atoms can only be handled by computer simulation. Inorder to model two-dimensional structures fabricated usingmodern process technology a numerical solution is required.

The lecture material on process simulation focuses on theprocesses of oxidation, diffusion, and ion-implantation.Reference [3] is an excellent resource for material on themodels used for these processes. The following list describessome of the specific elements of each process that areexplored in the laboratory exercises using Athena.

1) Diffusion: E-field effects on dopant distribution,fully-coupled defect-impurity interactions, non-equilibriumdefect concentration effects such as the emitter-push effectand transient-enhanced diffusion (TED), dopant clusterformation

2) Oxidation: 2-D oxide growth kinetics (shapedstructures, LOCOS), crystal orientation effects, influenceof stress and relaxation, dopant-dependent oxidation,oxidation-enhanced/retarded diffusion

3) Ion Implantation, damage annealing and impurityactivation: Dual-Pearson & Monte Carlo ion implantationmodels, implant damage, 311 defect clusters &dislocation loops, cluster evaporation (transient-enhanceddiffusion)

In addition to using Athena, the Stopping and Range of Ionsin Matter (SRIM-2000) [4], by J.F. Ziegler, IBM WatsonResearch Center, is used for implant and damage modeling.Various assignments also involve developing custom mathprograms for performing a numerical analysis.

C. Device Modeling

Silvaco Atlas is Athena's counterpart for electricalsimulation. Although various types of device structures canbe simulated, MOS transistors are the principle devicesdiscussed and explored in the laboratory exercises. Asignificant portion of the lecture material involves reviewingthe physics that ultimately determines the on-state andoff-state characteristics of the devices.

Most of the on-state device performance is describedwithin the context of a Level-2 (physically based) SPICEmodel. Basic MOS transistors (channel length ~ 2µm) areinitially used for electrical simulation and parameterextraction exercises. Although automated parameterextraction and optimization software is available (SilvacoUTMOST), a manual/iterative approach is highly effective indemonstrating the challenges of device engineering tostudents. SPICE Level-2 parameters are extracted thatdescribe the on-state device operation, including the influenceof short-channel effects (e.g. velocity saturation) and deviceparasitics (e.g. source/drain series resistance).

The limitations of a device structure are often defined bythe off-state, or subthreshold, device performancecharacteristics. Short-channel effects such as V T roll-off,drain-induced barrier lowering (DIBL) and punchthrough areobserved as the device structures are scaled beyond theiroperational capability. A systematic investigation of thedevice design is done to see how changing certain physicalparameters (i.e. gate oxide thickness, source/drain junctiondepths, well doping concentration) can improve subthresholdperformance, using the criteria established by Brews et al. [5]as a guideline. The methodologies used to characterize theon-state and off-state parameters, as well as investigate thescalability of the device designs, will be discussed in furtherdetail in the presentation of the full-class investigationdescribed in section III.

D. Student Investigations

In addition to a class-oriented simulation project, thestudents must choose an individual project for investigation.The projects can range from exploring a specific processmechanism to the operation of a device structure. Many ofthe projects start by looking into the example files that Silvacoprovides with the simulation tools. The following listdescribes some of the individual simulation projects that havebeen investigated:

1) Process Mechanisms: Ion-implant distribution models,Transient-enhanced diffusion (TED), 2-D oxide growthmodels, silicide formation

2) Device Technologies: Advanced bipolar processes,Deep submicron CMOS, GaAs device isolation, SiGeHBTs, tunnel diodes, SOI CMOS devices, Vertical MOSdevices

3) Device Operation: Flash EEPROM read/write,charge-coupled devices (CCDs), transient analysis ofCMOS latch-up

Many of the projects involve using design-of-experiments(DOE) methodology to explore how a specific processparameter influences device operation. Upon completion, thestudents discuss their projects and findings during classpresentations.

2

III. CLASS INVESTIGATION - CMOS PROCESS DEVELOPMENT

The most recent offering of the EMCR704 course hasfocused on using process and device simulation to develop abaseline 2µm CMOS process (referred to as 704CMOS) thatwould be robust against process variation. RIT currently hasa twin-well submicron CMOS process [6] being fabricated inthe Semiconductor & Microsystems Fabrication Laboratory(SMFL) [7]. The exercise of d eveloping this new CMOSprocess variation has provided an excellent educationalexperience for the students involved, as well as resulting in aCMOS process that has demonstrated successful fabricationresults.

A. Process Definition

The 704CMOS process development used a collectivestrategy; certain modules were taken from processesdeveloped at RIT, while other ideas were borrowed from thework of other g roups [8]. A thorough review was done tojustify the sequence and process recipes used in each stepthroughout the entire process. In a few cases before a finaldecision was made on the process strategy, a toleranceanalysis [9] was used to determine the sensitivity of the deviceoperation to variation on the processing parameters.

The 704CMOS process is a double-LOCOS, twin-well,n+poly gate CMOS process [10] designed to provide goodperformance at effective transistor channel lengths as small as2µm. The gate oxide thickness was chosen to be 400Å, andthreshold voltages were specified at +/- 1V, intended for usein 5V supply circuit applications. The following descriptionsummarizes the details of the process modules:

1) Substrate & twin-well formation p-type 10Ω-cm (100) substrate grow 400Å pad oxide, 1200Å nitride deposition N-well lithography, window etch P31 implant 7.4E12cm-2 @ 90KeV LOCOS#1 5000Å n-well oxidation Nitride etch, B11 p-well implant, 7E12cm-2 @ 50KeV Well drive-in - 1100°C, 6hr dryO2 + 38hr N2

2) Device isolation BOE oxide etch, grow 400Å pad oxide Nitride#2 deposit 1000Å (thickness important) Active lithography, Nitride RIE Channel stop litho (open p-well regions) Channel-stop implant (field) / nfet active adjustment

(through nitride): B11 5E12cm-2 @ 180KeV LOCOS#2 field oxide - steam @ 950°C, 6500Å

3) Transistor fabrication Kooi oxide growth - steam @ 900°C, 1000Å PFET VT adjust litho, B11 2E12cm-2 @ 35KeV

Gate oxide, 400Å dryO2 w/TransLC @ 1000°C polysilicon deposition - 6000Å n+ spin-on-dopant - 1000°C, 15min N2

gate lithography, polysilicon RIE n+ source/drain litho, 2E15cm-2 @ 75KeV p+ source/drain litho, 2E15cm-2 @ 50KeV Polysilicon re-oxidation, 850°C steam, 20min

4) Dopant activation & contact formation Low-temp oxide (LTO) deposition, 0.3µm LTO densification / thermal activation,

30min @ 1000°C Contact cut lithography, etch windows Sputter deposit aluminum, pattern and etch Sinter at 450°C, 15min in H2/N2

A detailed report of each process recipe is beyond the scopeof this paper, however there are some interesting features ofthe developed process worth discussing. All thermalprocesses are 6-inch substrate compatible (slow thermalramping, T max < 1150°C), and are designed to minimizethermal stress. The n-well profile leads to a relativelylow-dose boron V T adjustment for the buried-channel PFET.The NFET V T adjustment is performed through the activenitride/pad-ox at the same time (same implant) as thechannel-stop field V T adjustment, avoiding the need for anexcessively thick active nitride layer. Note that punchthroughimplants are not specified, however they could easily beadded for a scaled process design. The level of the detail thatwas considered during the process design goes well beyondthat necessary for a simulation exercise. It is obvious that the704CMOS process was developed with the intent to actuallyfabricate the transistors, which is discussed in section D.

B. Process & Device Simulation

Using a simplified 1-D channel conductance analysis,Athena was used to converge on the final processspecifications to yield the target threshold voltages. Thesimulated NFET and PFET 2-D device structures are shownin fig. 1a and fig. 1b, and the 1-D doping profiles in thechannel region are shown in fig. 1c and fig. 1d. Table Iprovides a summary of the physical parameters that describethe NFET and PFET structures. Once the processdevelopment was complete, Atlas was used for a 2-Dinvestigation on the on-state and off-state characteristics ofthe transistors. The text task was to extract SPICE Level-2parameters that describe the operation of the devices.Numerous simulations were performed to provide the datarequired to separate and optimize SPICE model parametersthat influence both the voltage-dependent andvoltage-independent portion of the current equations. Thesystematic methodology used is discussed in section C.

3

NFET Athena Simulation

micron

mic

ron

depth (micron)

Con

cent

ratio

n (c

m-3

)

Nsur ~ 3E16cm-3

NFET: Boron p-well Impurity Profilewith active adjustment

PFET: Phosphorus n-well profile &Boron VT adjustment

phosphorusn-well

boron VT adj.

depth (micron)

conce

ntr

atio

n (

cm-3

)

PFET Athena Simulation

micron

mic

ron

(a)

(c) (d)

(b)

TABLE INFET & PFET PHYSICAL PARAMETERS

Fig. 1. Athena process simulation results. Fig. 1a and fig. 1b show the 2-D structural simulation of the NFET and PFET, respectively. The simulated device structures were adjusted to provide 2µm channel lengths defined by the metallurgical junctions. Fig. 1c and fig. 1d shows the 1-D doping profile in the center of the channel region of the NFET and PFET, respectively. The NFET is fabricated in the defined p-well, with the channel-stop implant serving as an active-region (threshold voltage) adjustment. The PFET is fabricated in the defined n-well, with a boron VT adjustment that forms a p-type region within approx. 0.25µm from the surface. Note that the PFET is a buried-channel device.

ND=4E16cm-3

w/o adjust

NA=3E16cm-3Surface Conc.

0.75µm0.50µmJunction Depth

400Å400ÅGate Oxide

-1.0V+1.0V1-D VT

buriedsurfaceChannel Type

PFETNFET

C. Parameter Extraction

Atlas-simulated NFET and PFET family of curves areshown in fig. 2a and fig. 2b, respectively. SPICE Level-2parameters were extracted using a systematic approach. Someof the parameter extractions were quite straightforward,however in other cases parameter values were not uniquelysolvable. This section will describe, in sequential order, thevarious procedures that were used to extract parameters on thesimulated device characteristics. The only initial parametersthat were taken as known values were the gate oxide thickness(XOX taken to be 400Å) and the effective width of thetransistor (Weff taken to be 1µm). Note that in the followingequations, all symbols have their usual meaning unlessotherwise specified. Also, equations are given in reference toan NFET (p-substrate) device.

1) Threshold voltage (VT), body-effect coefficient (γ)and mobility degradation (θ)

Linear-region threshold voltage characteristics (IDS vs.VGS @ V DS = 0.1V) were taken at source-substrate biasconditions of VSB = 0V and VSB = 1V. Neglecting the smallVDS

2 term, VT comes directly from a linear extrapolation of theVSB = 0V characteristic to the X-axis from the steepest-slope(highest transconductance) region. Gamma ( γ), or thebody-effect coefficient of the V T equation, was found usingthe following relationships:

(1)∆VT = γ( 2φF + 1V − 2φF )

(2)γ = 1Cox

2qεSiNA

(3)φF = kTq ln

NAn i

Gamma was found iteratively by varying N A until (1) wassatisfied. Theta ( θ), or the low-field mobility degradationterm, is also readily extracted from the VSB = 0V characteristicusing the difference between the actual IDS @ VGS = VDD, andthe extrapolated value (IDS') using the maximumtransconductance region as follows:

(4)IDS

IDS= 1 + θ(VGS − VT)

Theta reduces the low-field mobility ( from µO to µlf) asfollows:

(5)µlf =µO

1 + θ(VGS − VT)

Although theta can be found, the effective channel length (Leff)must be determined in order to isolate the carrier mobility.Note that in a 3-D analysis the effective channel width (Weff)would also need to be extracted.

2) Effective Channel Length (Leff)

The effective channel length was determined using theTerada-Muta m ethod [11]. This m ethod uses linear-region(VDS = 0.1V) current data taken from devices with varyingmask-defined channel lengths (Lm) at different gate bias(VGS-VT) conditions. Values of the measured channelresistance (Rm) are plotted against L m, with the uniqueintersection of the characteristics found at the channel lengthreduction (X = ∆L) and the source/drain series resistance (Y =RDS), as shown on the T-M plot in fig. 2c for the simulatedPFET. The effective channel length was then taken to be:

Leff = Lm - ∆L (6)

Although the Terada-Muta method has noted shortcomings atlow temperature (77K) and deep submicron conditions, theanalysis works extremely well on this relatively conservativedevice structure. Once L eff was established, µ O could becorrectly determined.

3) Velocity saturation (VMAX) and channel-length modulation (λ)

The extracted value of the saturation current (IDSsat , taken@ VGS=VDS=VDD) must be matched by the saturation currentequation. What is required are best-fit values of VMAX(maximum carrier drift velocity, or νsat) and λ that bestreproduce the family of curves with the saturation currentmatched, however these parameters cannot be uniquelydetermined by this one data point. These parametersinfluence the saturation current by lowering the VDS at whichthe device enters the saturation regime (VDSsat), decreasing theeffective carrier mobility (µeff) due to velocity saturation, andincreasing the saturation current due to channel lengthmodulation (λ) as follows [12]:

, (7)VC =(VMAX)(Leff)

µlf

where VC is an intermediate "critical voltage"

, (8)VDSsat = Vsat + VC − Vsat2 + VC

2

where Vsat is the original onset of saturation taken to be VGS - VT

, (VDS VDSsat) (9)µeff =µlf

1 + VDSsat

VC

≥

(10)IDSsat =Weff

Leff(µeff)COX

(VGS − VT)VDSsat −

VDSsat2

2

, (VDS VDSsat)×

11 − λ(VDS)

≥

5

0.00E+00

2.00E-05

4.00E-05

6.00E-05

8.00E-05

1.00E-04

1.20E-04

1.40E-04

0.00 1.00 2.00 3.00 4.00 5.00

NFET Family of Curves Lmet = 2µm

Voltage (V)

Cur

rent

(A

)

ATLAS

PFET Family of Curves Lmet = 2µm

Voltage (V)

Cu

rre

nt

(A)

0.00E+00

5.00E-06

1.00E-05

1.50E-05

2.00E-05

2.50E-05

3.00E-05

3.50E-05

4.00E-05

4.50E-05

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00

ATLAS

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50

Atlas Simulation / SPICE Level-2 overlayPFET Family of Curves Leff = 2µm

Voltage (V)

Cur

rent

(A

)4E-5

3E-5

2E-5

1E-5

-5.00E+04

0.00E+00

5.00E+04

1.00E+05

1.50E+05

2.00E+05

-1 0 1 2 3 4

L m ( u m )

Rm

(o

hm

)

Vg=-2.2

Vg=-3.3

Vg=-4.4

Vg=-5.5

Linea r (Vg=-2.2)

Linea r (Vg=-3.3)

Linea r (Vg=-4.4)

Linea r (Vg=-5.5)

PFET Terada-Muta Plot

Fig. 2. Atlas simulated electrical characteristics, and SPICE model parameter extraction. Fig. 2a and 2b show the family of curves for the NFET and PFET, respectively, with a metallurgical channel length Lmet = 2.0µm. Fig. 2c shows the Terada-Muta plot for the PFET device, which yields the extracted values of ∆L and RSD listed in table 2. Fig. 2d shows a PFET family-of-curves overlay comparing Atlas simulation and SPICE Level-2 characteristics, using the parameter values listed in table 2.

TABLE IISIMULATED PFET SPICE PARAMETERS

0.075V-1Lambda

1E6cm/secVMAX

318cm2/v-secUO

ValueParameter

2.5KΩ-µmRSD

100mV/decS-Swing

0.06µm∆L

0.016V-1Theta

0.874V0.5Gamma

-1.025VVTO

(a)

(c)

(d)

(b)

Fig. 2d shows an overlay of family-of-curvescharacteristics, comparing the Atlas simulation and the SPICELevel-2 model for the PFET. The SPICE model parametersfor the simulated PFET, including the iteratively determinedVMAX and λ, are given in Table II. The SPICE modelcharacteristics involve all of the parameters listed in Table II,and a V DS adjustment is made to take R SD into account.Although the comparison between the Atlas simulation andthe SPICE model is reasonable, there is a clear limitation ofthe ability to match a Level-2 model to the simulatedcharacteristics. This limitation is overcome by usinghigher-level SPICE models such as BSIM3 [13] andautomated parameter extraction software, such as SilvacoUTMOST®, which has the ability to adjust many parametersand converge on a least-mean-square-error (LMSE) fit to thesimulated characteristics. The subthreshold swing (SS) of thePFET is also given in Table II, as a noted exception to thepure Level-2 parameter set.

D. Verification

The same methodology that was used for parameterextraction on simulated device characteristics was alsoimplemented on recently fabricated 704CMOS transistors.The device fabrication was done outside of the class, and fullcharacterization of the devices is still in progress at the timeof this writing. The I-V characteristics were measured usingan HP4145 Semiconductor Parameter Analyzer, withfamily-of-curves plots and threshold voltage characteristicsshown in fig. 4. Note that the tested devices havemask-defined channel lengths Lm = 8µm (see fig. 3 above).

The NFET threshold voltage came in right on the 1Vtarget (see fig. 4c), with excellent uniformity bothwithin-wafer and wafer-to-wafer. The PFET thresholdvoltage measured at -2.1V, which was ~ 1V higher (inmagnitude) than the target value. However, it was found thatprocess splits used to investigate the impact of the PFET VT

adjust implant dose showed that it had very little influence,

indicating that there may have been a problem with theequipment or process during that implant. Table III gives apartial listing of SPICE Level-2 parameters for the fabricatedNFET and PFET devices; characterization is still in progress.Although most of the SPICE parameters on measured devicesare for the NFET and the previous section describes SPICEparameters for the simulated PFET, comparisons are stillvaluable.

The simulated PFET had a Gamma value thatcorresponded to an effective substrate doping N Deff =1.7E16cm-3. This number has no real physical meaning, sincethe PFET is a buried-channel device. The measuredsurface-channel NFET exhibited a Gamma value thatcorrelates nicely with the simulated p-well surfaceconcentration. Using the Terada-Muta method, thechannel-length reduction ∆L was determined to be 2.45µm forboth the fabricated NFET and PFET devices. This issignificantly higher than the simulated result, due to processbiases (primarily the poly gate lithography and RIE) that donot appear in the simulated device.

The low-field mobility µ O for the measured NFET cameout relatively low for an electron channel mobility, howeverthis value is coupled with an assumed W eff = 8µm. Processbiases, such as RIE over-etch of the active nitride andfield-oxide encroachment during the LOCOS isolationprocess, will reduce W eff, and thus result in an increased µ O

value. The Theta value for the measured NFET device wassignificantly higher than the value extracted on the simulatedPFET device, attributed to differences betweenburied-channel and surface-channel behavior.

The R SD (Ω-µm) value for the simulated PFET structurepredicts a RSD ~ 300Ω for an 8µm wide active area. The RSD

values extracted from the measured NFET and PFETcharacteristics were 600Ω and 100Ω, respectively. However,these differences are easily attributed to the additionalinfluence of contact resistance, and differences in the actualdevice layout.

7

NFET: L=8µmW=16µm

CMOS Ring Oscillator

NFET: L=8µmW=16µm

NFET: L=8µmW=16µm

CMOS Ring Oscillator

Fig. 3. Testchip devices and circuits. (a) isolated NFET (b) CMOS ring oscillator

Testchip Devices & Circuits

0.00E+00

2.00E-04

4.00E-04

6.00E-04

8.00E-04

1.00E-03

1.20E-03

0.00E+00 1.00E+00 2.00E+00 3.00E+00 4.00E+00 5.00E+00

NFET Family of Curves Lm = 8µm Wm = 8µm

Voltage (V)

Cur

rent

(A

)

HP4145-6.00E-05

-5.00E-05

-4.00E-05

-3.00E-05

-2.00E-05

-1.00E-05

0.00E+00

-5.00-4.00-3.00-2.00-1.000.00

PFET Family of Curves Lm = 8µm W m = 8µm

Voltage (V)

Cu

rre

nt

(A)

HP4145

TABLE IIIMEASURED SPICE PARAMETERS

125mV/dec

---

---

600Ω

2.45µm

0.066V-1

430cm2/v-sec

1.13V0.5

1.0V

NFET Value

---Lambda

---VMAX

---UO

PFET ValueParameter

100ΩRSD

140mV/decS-Swing

2.45µm∆L

---Theta

---Gamma

-2.1VVTO

Fig. 4. Measured I-V characteristics on fabricated NFET and PFET devices, with mask-defined channel dimensions of Lm = 8µm & Wm = 8µm. Fig. 4a and fig. 4b show family-of-curves plots for the NFET and PFET, respectively. Fig. 4c and fig. 4d show linear-region threshold voltage characteristics. The electrical characteristics yield the SPICE model parameters listed in Table III.

(a)

(c) (d)

(b)

VMAX and Lambda values for the measured NFET arecurrently under investigation, as well as the remainingparameters for the measured PFET device. The simulatedNFET subthreshold swing (SS) was 110mV/decade, and thesimulated PFET SS = 100mV/decade. Subthreshold swingvalues for the measured NFET and PFET devices were125mV/decade and 140mV/decade, respectively, bothsomewhat higher than the simulation results.

E. Scaling

The 704CMOS process has a significant amount ofheadroom for scaling the structure down to submicrondimensions. The following relationship taken from [5]provides guidelines for scaling MOS designs and maintaininglong-channel behavior:

, (11)Lmin = A[toxrj(Xs + Xd)2]13

where A is 0.41Å-1/3, tox is the oxide thickness (in Å), rj is thejunction depth (in µm), Xs & Xd are depletion widths at thesource and drain ends (in µm), and L min is the minimumchannel length (in µm) for long-channel behavior, as definedby subthreshold performance.

Scaling experiments were simulated in order toinvestigate the influence of the gate oxide thickness, junctiondepth, and well doping concentration on the subthresholdcharacteristics. The first set of experiments scaled the704CMOS process into the submicron region by reducing thegate oxide thickness, increasing the well dopingconcentrations, and reducing the thermal budget (source/drainanneal). A second set of experiments investigated LDDstructures and punchthrough implants in order to scale thedimensions further.

The subthreshold parameters that were investigatedincluded V T roll-off, drain-induced barrier lowering (DIBL)and subthreshold swing. As the device scaling continuesbeyond the limits at which long-channel behavior dominates(Lmin), the off-state characteristics become unacceptable.Atlas electrical simulation models the effects of V T roll-offand DIBL, however there are some issues in modelingpunchthrough that require further investigation. Thepunchthrough effect seems to behave as expected for theburied-channel PFET. However when shrinking NFETdimensions into deep submicron, VT roll-off and DIBL effectsgreatly increased the subthreshold current flow, while theslope of the subthreshold characteristic remainedapproximately the same as the long-channel value.

IV. CONCLUSIONS

The EMCR604/704 course at RIT has been extremelyeffective at teaching students the details of numerical solutionmethods and process models, as well as utilizing the processand device simulation tools for an actual CMOS processdevelopment project. SPICE model parameter extraction hasalso become a major focus of the course, with an emphasis onthe systematic methodology required for an optimized SPICEparameter set. Although automated parameter extraction isbeing introduced to the students, the manual/iterative methoddescribed provides an excellent learning experience.

The class investigation on CMOS process developmentwas extremely successful. SPICE Level-2 models for thesimulated devices were developed, and characteristics werecompared with the numerical simulation results. With thecapability of CMOS fabrication at RIT, the process designwas verified to yield working devices, with additional devicecharacterization work in progress. Although certainlimitations of the process and device simulations wererevealed, this course clearly demonstrated the advantages inusing simulation tools for process and device design.

REFERENCES

[1] K.D. Hirschman and P.D. Rack, "Exploring Silicon Process TechnologyThrough RIT's NPN BJT Process," IEEE UGIM Symp. Proc. 13, 94(1999).

[2] S. Wolf, Silicon Processing for the VLSI Era: Volume III - TheSubmicron MOSFET, chapters 1&2, Lattice Press, 1995.

[3] J.D. Plummer, M.D. Deal and P.B. Griffin, Silicon VLSI Technology -Fundamentals, Practice and Modeling, chapters 6,7&8, PrenticeHall, Upper Saddle River, NJ, 2000.

[4] J.F. Ziegler, "The Stopping and Range of Ions in Matter (SRIM-2000)," http://www.srim.org/index.htm

[5] J.R. Brews et al., "Generalized Guide to MOSFET Miniaturization,"IEEE Electron Dev. Letts., EDL-1, 2 (1980).

[6] L.F. Fuller, "An Advanced CMOS process for UniversityMicroelectronics Laboratory Courses," IEEE UGIM Symp. Proc. 14, 36(2001).

[7] http://smfl.microe.rit.edu[8] L. Voros, "CMOS Baseline Process in the UC Berkeley Microfabrication

Laboratory Report II," Memorandum No. UCB/ERL M00/61, (2000).[9] K.D. Hirschman, "A Tolerance Analysis for Manufacturing to Direct

Process Capability Improvement Efforts," IEEE/SEMI ASMC Symp.Proc. 11, 377 (2000).

[10] S.M. Sze, VLSI Technology, 2nd Edition, pp. 485- 487.McGraw-Hill, New York, 1988.

[11] J.J. Liou, A. Ortiz-Conde and F. Garcia-Sanchez, Analysis and Designof MOSFETs, pp. 206-210. Kluwer Academic Publishers, Boston,1998.

[12] Meta-Software, HSPICE User's Manual, Volume 2 - Elements andModels, pp. 7.5-7.12. Meta-Software, Inc., Campbell, CA, 1992.

[13] Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P.K. Koand C. Hu, "A Physical and Scalable I-V Model in BSIM3v3 forAnalog/Digital Circuit Simulation," IEEE Trans. Electron Devices 44,277 (1997).

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