Semitool Confidential

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Copper Damascene Plating

1/5/06

Brandon BrooksProcess Development Engineer

2Semitool ConfidentialSemitool Confidential

Outline

•Why Cu Interconnects?

•Damascene Process Flow

•Parameters Affecting Cu Interconnects

•Backside Clean and Bevel Etch


Damascene Plating?


Why Cu Interconnects?

Al Cu W

Melting Pt (°C) 660 1,083 3,410

Oxidation in Air Rapid; Self-Sealing

Slow; Not Self-Sealing

Inert

Resistivity (m-cm)

Crystalline 2.82 1.77 5.6

As Deposited 3.0-3.3* 1.8-2.0 8-11

Self-Diffusion Coefficient (cm2s-1) @ 100 °C 2.1·10-20 2.1·10-30

Coefficient of Thermal Expansion (Unit/°C)

24·10-6 17·10-6 4.3·10-6

* Alloy (Si, Cu)

Resistivity Melting PointThermal Expansion Electromigration

Al

Resistivity Melting PointThermal Expansion Electromigration

Cu

Best!

Interconnect Metal Properties


Why Cu Interconnects?

Al Cu Ag

Etch Properties Cl & Br Plasmas Cl & Br Plasmas F & Cl Plasmas

Etch Rate (Å/min)

5,000 500 5,000

Cu has a very slow etch rate•Cu halides are solid at normal temperatures

Changing from Al to Cu interconnects requires new process flow•Enter Damascene plating

Interconnect Metal Properties


Damascene Process Flow

Typical Damascene Process Flow

1. Dielectric Deposition2. Photoresist Deposition3. UV Exposure4. Develop Photoresist5. Etch Dielectric6. Remove Photoresist7. Barrier Deposition8. Seed Layer Deposition9. Electrochemical Deposition (ECD)10. Backside Clean and Bevel Etch11. Anneal12. Chemical Mechanical Polish (CMP)13. Repeat Steps 1-10 for Every Metal Layer

Today’s Main Topics


Damascene Process Flow


Copper Interconnect Parameters

Key Factors Affecting Cu Interconnect Performance

1. Gap-Fill2. CD Uniformity3. Overburden4. Anneal

AMD’s 9 Cu Levels


Copper Interconnect Parameters: Gap-Fill

Key Parameters for Gap-Fill

1. Seed and Barrier Layers1. Uniformity2. Thickness

2. Plating Recipe1. Hot Start (Initiation)2. Fill Current Density3. Waveform

3. Plating Chemistry1. Inorganic2. Organic

0.12m, 8.3:1AR Trenches



Physical Vapor Deposition (PVD) Effects

Seed and Barrier Layers


Edge Shadowing Optimized Seed Layer


Seed and Barrier Layer Uniformity


1500Å Total Seed Thickness 2000Å Total Seed Thickness

0.30micron, 4.8:1 AR Vias 0.30micron, 4.8:1 AR Vias


Seed and Barrier Layer Thickness



Plating Recipe Hot Start

0.180 m Line Width Trenches48 Coulombs ECD

No Hot Start 2V Hot Start

2X Fill Rate on the 2V Hot Start



Plating Recipe Current Density

Current too Low

Current too High

The Effect of Current Density upon Gap Fill

Bad

Good

0.35μm, 4.3:1 AR Vias 0.35μm, 4.3:1 AR Vias

0.18μm, 5.1:1 AR Trench 0.18μm, 5.1:1 AR Trench

Gap

Fill

Current Density

Low High

Optimum Fillfor feature D

Optimum Current

Optimum Current



Plating Recipe Waveform

Waveform Cu Diffusion Additive Adsorption Bottom Up Fill

Direct Current (DC)

- + 0

Pulse DC + - 0

Pulse Reverse (PR) + - 0

DC plating provides better additive adsorption

Pulsed plating provides better Cu diffusion



Plating Chemistry

Inorganic Components

1. Copper Sulfate (CuSO4)2. Hydrochloric Acid (HCl)3. Sulfuric Acid (H2SO4)

Organic Components

1. Suppressor (PEG)2. Accelerator (SPS)3. Leveler (Amine)



Inorganic Plating Chemistry

Copper Effect on Gap Fill

High Copper

Low Copper




Chloride Effect on Gap-Fill

Cl- Effect on Suppressor

0

2

4

6

8

10

12

14

16

18

20

0 50 100 150 200

Cl Concentration ppm

CV

S S

trip

pin

gP

ea

k A

rea

(m

C)

Bad

Good

HighLow

Ga

p F

ill

Chloride (ppm)




Bad

Good

HighLow

Ga

p F

ill

Acid (g/l)

pH 3

pH 2

Acid Effect on Gap Fill

pH 2


• Accelerator– Catalytic effect

– Requires very small amount of Cl-

– Increased current for a given potential

• Suppressor– Suppresses deposition

– Requires Cl- to adsorb onto copper surface

– Decreases current for a given potential

• Leveler– Suppresses deposition at high current density areas

– Very low concentration (diffusion limited)


Organic Plating Chemistry

Organic Effect on Gap Fill


A

C

B

A = VMS

B = VMS + Suppressor

C = VMS + Sup. & Accel.

I

V

Cyclic Voltammetric Stripping Analysis (CVS)



Plating Region

Stripping Region


0

0.1

0.2

0.3

0 0.01 0.02 0.03 0.04 0.05

Suppressor Concentration

80 g/l

Low Acid (10g/l)

High Acid 150 g/l

0

5

10

15

20

25

30

0 1 2 3 4 5

Accelerator Concentration

80 g/l H2SO4

High Acid 150 g/l

Wors

eB

ett

er

Str

ippi

ng A

rea

Wors

eB

ett

er

Str

ipp

ing

Are

aCopper Interconnect Parameters: Gap-Fill





















Key Parameters for Current Density Uniformity

1. Chemistry1. High Acid2. Low Acid

2. CFD Reactor1. Electric Field Control

Intel: 8 Cu Levels

Copper Interconnect Parameters: CD Uniformity



+

Cathode(Reduction)

Current Path

Anode(Oxidation)

Cu2++2e- Cu0Cu0 Cu2++2e-

e- e-e- e-

Cu2+

V0

Electrolyte

Cu2+

Generalized Electrochemical SchematicElectrolytic Copper Deposition

Ammeter

Surface Area

Current Density = Current Surf. Area



= Surface Area

Relec 1/Bath Conductivity

Rcat 1/Seed Thickness

Rcat Wafer Radius

Relec

Ranode= 0

V+

Electrolyte

Cathode(Thin)

Anode(Thick)

Rcat

Relec

elecedge R

VI

)R(R

VI

cateleccenter

= Area


Relec

Ranode= 0

V+

Electrolyte

Cathode (Thin)

Anode (Thick)

Rcat

Relec

Edge I Loop

Center I Loop

)( catelecelec

catECcenteredge RRR

VRIII

How To Make ECI Small?

VCurrent DensityThroughput

Rcat

Seed Layer ThicknessWafer Radius

Relec

Bath Conductivity



Conductivity at Various Bath ConditionsConductivity at Various Bath Conditions

0

100

200

300

400

500

600

Con

du

ctiv

ity

(mS

/cm

)

175 g/l H2SO4

17 g/l Cu

80 g/l H2SO4

50 g/l Cu

10 g/l H2SO4

50 g/l Cu

“Low” Acid

“High” Acid

70

247

511



0sec

5sec

15sec

30sec

60sec

120sec

Cu

rren

t D

ensi

ty

Wafer Radius

Plating Time

(0,0)


Terminal Effect


Current too Low

Current too High

The Effect of Current Density upon Gap FillThe Effect of Current Density upon Gap Fill

Bad

Good

0.35mm, 4.3:1 AR Vias 0.35mm, 4.3:1 AR Vias

0.18mm, 5.1:1 AR Trench 0.18mm, 5.1:1 AR Trench

Gap

Fill

Current Density

Low High

Optimum Fillfor feature D

Optimum Current

Optimum Current



Are the center and edge receiving the same process?



Cathode

Anode2

V1+

V2+

Anode1

Advanced Reactor Design: Multiple Anodes

Robust system that can handle multiple chemistries

Built for the future with the ability to handle shrinking die size

Cost effective ability to handle increasing wafer diameters


0 ECIV1 and V2 adjusted until Independent of Rc and Relec


Dielectric

Electrolyte Virtual Anodes

Physical Anodes

WaferConventional Reactor CFD Reactor

Electrolyte



ConcentricAnnular Anodes

ElectrolyteBubble Trap

Rotating Wafer

Dielectric

Flow Inlet

Overflow

Virtual Anode



Superposition of Electric Field

-120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120

Wafer Diameter (mm)

Nor

mal

ized

Vol

tage

at C

atho

de (

V)Anode 1

Anode 2Anode 3

Anode 4

Summed Field



100 nm Seed layer, 1100 nm Seed layer, 1m depositionm depositionH

igh

Aci

d51

1mS/

cmL

ow A

cid

70m

S/c

m

Conventional SEMITOOL - CFD

14

18

22

26

30

34

Cu

rren

t D

ensi

ty (

mA

/cm

^2) 0sec

5sec

15sec30sec60sec120sec

133%

14

18

22

26

30

34

0 25 50 75 100 125 150

Cu

rren

t D

ensi

ty (

mA

/cm

^2)

0sec

120sec

20%

<5%

0 25 50 75 100 125 150

<5%

Wafer Radius (mm)



Dynamic Compensation for Constant Current DensityDynamic Compensation for Constant Current Density

1.0

1.5

2.0

2.5

0 20 40 60 80 100 120Deposition Time (sec)

An

ode

Cu

rren

t (A

mp

s)

Anode 2

Anode 3Anode 1

Anode 4



Key Parameters for Overburden

A. Local Overburden (Overplating) – Fill Step1. Chemistry

1. 3-Component2. 2-Component

2. Waveform1. Direct Current2. Pulse Reverse

B. Global Overburden – Cap Step1. Chemistry

1. High Acid2. Low Acid

2. CFD Reactor

Copper Interconnect Parameters: Overburden


Copper Interconnect Parameters: Local Overburden

Direct Current POR

3-Component Organic Package

Moderate Acid Electrolyte

Pulse Reverse POR 2-Component Organic Package

High Acid Electrolyte

Step Up No Step Up


Copper Interconnect Parameters: Local Overburden

Insufficient Leveler

Planar Deposition

Optimized Organic Conditions

Overplating

Post-CMP Residual Cu

No Post-CMP Residual Cu


Copper Interconnect Parameters: Global Overburden

-100mm 0 100-800

-600

-400

-200

0

200

400

600

800Å

Radial control of Thickness Variation (Å)

Cu

Th

ick

nes

s (Å

)

Wafer Diameter (mm)



Raider CFD Profile Before & After 30s CMP

4,000

8,000

12,000

16,000

Th

ick

ness

(A

)

POR Profile Before & After 30s CMP

4,000

8,000

12,000

16,000

Wafer Diameter

Th

ick

ness

(A

)

Early Clearing!

POR Profile before CMP

Profile after 30s CMP

Profile after 30s CMP

EdgeResidual!

CFD Profile before CMP

Uniform Post-CMP Profile



CMP Profile Matching

0.96

0.98

1

1.02

1.04

1.06

1.08

1.1

-150 -100 -50 0 50 100 150

Wafer Radius (mm)

No

rma

lize

d T

hic

kn

ess

ECD Profile CMP Profile


Copper Interconnect Parameters: Anneal

Key Parameters for Anneal1. Temperature

2. Feature Size

3. Barrier Layer


As Deposited

Self Annealed

Thermally Annealed

Small Grains

Large Grains


Effect of Temperature



1.0m Trenches

0.25m Trenches

Effect of Feature Size

Furnace AnnealSelf-Anneal



Ta Barrier Layer

TiNx Barrier Layer

•Strong Surface Interaction

•Reduced Migration

•Weak Surface Interaction

•Increased Migration

•Large Voids

Effect of Barrier Layer



Anneal Temp

Lin

e R

esis

tanc

e

Ta

TaNx

TiNx

Grain Growth

Void Formation

Optimum

Optimum Anneal Condition


Backside Clean and Bevel Etch

Why Backside Clean and Bevel Etch?• Cu is a highly mobile ion

• Backside contamination can have adverse effects across the fab

• Unstable films on the edge of the wafer can cause surface damage at CMP

Objective1. Remove bulk Cu on the edge of the wafer

1. Delamination

2. Flaking

3. Yield Problems

2. Remove atomic Cu on the back of the wafer1. Common Photolithography

2. Common Metrology

3. Cu ion diffusion



Capsule 1 Chamber Cut Away

Edge Exclusion Hardware

Capsule 1 Features

1. Hardware control of bevel etch (BE)

2. 0-4mm BE edge exclusion (EE) range

3. No front side protection needed

4. BE & backside clean simultaneously

5. Clean N2 purged microenvironment



Capsule Dynamics

WaferDevice Up

Seal

Chamber Rotation

Back Side Inlet: -Dilute Piranha Solution-DI H2O-N2

Front Side Inlet: -DI H2O-N2



Capsule Dynamics

Seal

Chamber Rotation

Back Side Inlet: -Dilute Piranha Solution-DI H2O-N2

Front Side Inlet: -DI H2O-N2

WaferDevice Up



A concentric 1.5mm EE BE clears the notch

Precision Control of Chemical Wrap-Around

Critical Bevel Etch Parameters1. Concentricity

2. Complete Cu Clearing

3. Clearing the Notch



Precision Control of Concentricity

Concentricity Spec (a) ≤ 0.2mm



E Beam Spot Magn WD 10 µm

10.0kV 2.0 3500x 17.1 STI. Bevel Etch

No Copper on Edge Exclusion Zone

No undercut

Target ECD 1.0µm

1 µm ECD Copper

1.5 mm Edge Exclusion Profilometer Reading

52º Tilt on SEM

<10 µm

Precision Control of Copper Removal


Why Cu Interconnects?•Resistivity•Reliability

Damascene Process Flow•Photolithography to CMP

Parameters Affecting Cu Interconnects•Gap-Fill•Current Density Uniformity•Overburden•Anneal

•Backside Clean and Bevel Etch•Bulk Cu on the Edge •Atomic Cu on the Backside

Summary


Acknowledgements

John Klocke – Cu Damascene Group Leader

Kevin Witt – Cu Damascene Business Development Leader

Tom Ritzdorf – Director of ECD Technology

Jake Cook – Marketing Communications

All Semitool personnel that have contributed data to this presentation

Documents

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