SentientChips-Using-Machine-Learning

Copyright © S.Sarma, 2014 https://students.ics.uci.edu/~santanus/ #1

Santanu Sarma Center for Embedded Cyber-Physical Systems (CECS)

University of California, Irvine

Towards Sentient Chips: Self-Awareness for Smart Processors

Research Partially Supported by the NSF Variability Expedition Project



Towards Sentient Chips: Self-Awareness for Smart Processors


Self-Awareness & Adaptation in Biology

[David Gallo: Underwater astonishments, TED]


Self-Awareness vs Context-Awareness

•  Self-Awareness [Hinchey2006]: System is aware of its self states and behaviors

•  Context-Awareness [Parashar 2005] : System is aware of context – i.e., its operational environment

•  Self-configuring -> capability of reconfiguring automatically •  Self-healing [Robertson2005] -> self-diagnosing and self-

repairing •  Self-optimizing-> capability of self-tuning or Self-adjusting •  Self-protecting -> capability of detecting dangerous outcomes

(e.g. security breaches) and recovering from their effects


A Hierarchical View Self-*

[SALEHIE 2009, TAAS]

Global Properties

self-managing, self-governing, self-maintenance, self-control, self-evaluating, self organizing

in accordance to biological self-adaptation

self-monitoring, self-situated


Self-Reflection

•  Self-Reflection:

–  Ability to create a self-model

–  Ability to model their own body/structure (usually known self-modeling)

–  Ability to model their own behavior

–  Metacognition capacity: ‘models one’s own thinking’, ‘think about thinking’

–  System with two/multiple minds: one being modeled and other doing modeling

–  Control Systems Theory: also called Dynamical System identification


Towards Sentient Chips: Self-Awareness through On-Chip

Sensemaking


Self-Assembling Robots (Sensemaking)

[Kilobots, Harvard 2014]


Outline

•  Self-Awareness, Sentience, Sensemaking

•  Cyber-Physical Systems-on-Chip (CPSoC)

•  CPSoC Exemplars and Prototype

•  Wrap-up


Outline




•  Wrap-up


Towards Sentient Chips: Self-Awareness through On-Chip

Sensemaking


What are Sentient Chips?

•  Sentient chips – Construct model of behaviors and environment

using sensor data – Achieve self-awareness through on-chip sensors

and monitors •  Experience phenomena •  Aware of state and behavior

– The ability to introspect – Adapt behavior based on model of external and

internal environment


Why On-Chip Self-Awareness?

•  Tremendous variation in applications, environment, platforms

•  Chips must adapt to Dynamic Performance, Power, Resilience, Security,…. – Radar chart examples

•  Provide Guarantees •  Exploit trade-offs in several dimensions


Ideal Radar Chart?


Performance Driven Energy/Power Driven

Reliability Driven Security Driven

QoS Combination

Reality




QoS Combination

Reality




QoS Combination

Reality




QoS Combination

Reality




QoS Combination

What we want: QoS Combination




QoS Combination

Need Adaptability and Autonomy


Outline


•  Cyber-Physical Systems-on-Chip (CPSoC) – First Step Towards Sentient Chips


•  Wrap-up


CPSoC Vision: Across Design Features

Tradi7onal MPSoC Cyber-‐Physical SoC (CPSoC) CPSoC provides opportunity to improve mul3ple design dimensions (in addi3on to performance)


CPSoC Vision: Across Applications

General Purpose Processor

Performance/Pow

er

Applica7ons FFT Matrix Mult. LDPC



Asymmetric Multiprocessor

Performance/Pow

er


Simple adaptation



Accelerators



Performance/Pow

er




Accelerators



CPSOC

Performance/Pow

er


Self-Aware Cross-Layer Adaptation


CPSoC aims to adapt across a wide range of dynamic applica3ons to yield acceptable QoS


Cyber-Physical System-on-Chip (CPSoC)

•  Cross-Layer Virtual and Physical Sensing & Actuation •  Sensor fusion and Actuation

–  Combine hardware and software sensors

•  Self-Awareness and Adaptation •  Combines Simple and Self-Aware adaptions •  A reflexive (Observe-Decide-Adapt) architecture to achieve

closed loop system control

•  Predictive Modeling & Learning •  Dynamic characterization of platform variability across

multiple levels of the system stack.


Cross-Layer Physical/Virtual Sensing & Actuation

Applications

Operating System

Network/Bus Communication

Architecture

Hardware Architecture

Device/Circuit Architecture

SA

SO

SN

SH

SC

Sensors (Observer)

Adaptive Control (Decide)

AA

AO

AN

AH

AC

Actua7on (Act)


Layers Virtual/Physical Sensors Virtual/Physical Actuators

Application Execution Time, Workload Power, Energy,

Loop perforation Algorithmic Choice

Operating System

System Utilization Peripheral States

Task Allocation, Scheduling, Migration, Duty Cycling


Bandwidth; Packet/Flit status; Channel Status, Congestion, Latency

Adaptive Routing Dynamic Bandwidth Allocation Ch. no and direction


Cache misses, Miss rate; access rate; IPC, Throughput, ILP/MLP, Core asymmetry

Cache Sizing; Reconfiguration, Resource Provision Static/Dynamic Redundancy

Circuit/Device Circuit Delay, Aging, leakage Temperature, oxide breakdown

DVFS, DFS, DVS ABB, Clock and Power-gating

Examples of Virtual Sensors and Actuators Across Layers of CPSoC


CPSoC Basic Computa7onal Block

ACTUATORS

CORE SE

NSO

RS

MEMORIES NIA

ACCELERATORS


CPSoC Computa7onal PlaMorm

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPS Core

Adaptive Router

Chip Hardware

App 1 App 2 App N

Cross-Layer Sensors(Virtual & Physical)

Decisions & Learning(Controller)

Actuation (softwareand hardware)

Refle

ctiv

e M

iddl

ewar

e La

yer

Scheduling MemoryManager File System

DeviceDrivers

Traditional Operating System

Hypervisor

Observe Decide

Act

App

licat

ion

Laye

r

CPS

Cor

e

DDRO(s)

OxideSensor(s)

TemperatureSensor(s)

LeakageSensor(s)

Aging Sensor(s)

Reliability Sensor(s)

Performance Counters

CPU(s)

$I $D

$L2

Scratch pad/On-Chip SRAM

NIA

Timer & RTC

PLL

On-chipActuation Unit

On-Chip Sensing & Actuation (OCSA)

GPIO

!

•  Sensor/Actuator-rich SoC fabric –  OCSA: On-Chip Sensing

and Actuation unit

•  NoC overlay (or separate network)

•  SW enabled sensors & actuators

•  Adaptive control of platform resources


CPSoC Hardware Fabric

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPS Core

Adaptive Router

Flexible Hardware Fabric

Distributed resources suppor3ng homogeneous or heterogeneous or mixed fabric


CPSoC HW/SW Stack

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPU CPU

$I $D

$L2

NIA OCSA

NoCRouter

OCSA

CPS Core

Adaptive Router

Chip Hardware

App 1 App 2 App N

Cross-Layer Sensors(Virtual & Physical)

Decisions & Learning(Controller)

Actuation (softwareand hardware)

Refle

ctiv

e M

iddl

ewar

e La

yer

Scheduling MemoryManager File System

DeviceDrivers

Traditional Operating System

Hypervisor

Observe Decide

Act

App

licat

ion

Laye

r

CPS

Cor

e

DDRO(s)

OxideSensor(s)

TemperatureSensor(s)

LeakageSensor(s)

Aging Sensor(s)

Reliability Sensor(s)

Performance Counters

CPU(s)

$I $D

$L2

Scratch pad/On-Chip SRAM

NIA

Timer & RTC

PLL

On-chipActuation Unit

On-Chip Sensing & Actuation (OCSA)

GPIO

!


Cross-Layer Physical/Virtual Sensing & Actuation

Applications

Operating System


Architecture


Device/Circuit Architecture

SA

SO

SN

SH

SC

Sensors (Observer)

Adaptive Control (Decide)

AA

AO

AN

AH

AC

Actua7on (Act)


Cross-‐Layer Physical/Virtual Sensing

•  Many restrictions in physical deployment of sensors and test structures in MPSoCs: – Resource constraints

•  e.g. Area, Power – Limited no, resolution, accuracy, range – Placement Restrictions – Complexity of sensing and observation structures –  Inaccessibility or inability of direct measurement – Prohibitive cost

Virtual Sensing is a Indirect Computa3onal Approach to overcome several sensing limita3ons


Core%

cNoC%router%sNoC%router%Sensor%%interconnect%

Core%%interconnect%sNoC%%Manager%

Core%Task%%Manager%

Legend%

R R R R

RRRR

Temp.%Sensors%

Accurate%%Temperature%

Power%

Total%Power%

Sensor%NoC%

Robust%Kalman%Filter%

Noisy%%Measurement% Virtual%Sensor%

(a)Virtual%Sensing%NetworkDonDChip%

(b)%SensorDNoC%(sNoC)% (c)%Independent%mulGple%coexisGng%NoC%%

…%

…%

Example Virtual Power Sensing with few Thermal Sensors


Example Virtual Power Sensing with few Thermal Sensors

0

2

4

6

8

10

Pow

er, W

atts

Average Power of Each Blocks

L2_lef

tL2

L2_rig

ht

Icach

e

Dcach

eBpred DTB

FPAdd

FPRegFPMul

FPMap

IntMap IntQ

IntReg

IntExec

FPQLdStQ ITB

ActualEstimated


Cyber-Physical System-on-Chip (CPSoC)

•  Cross-Layer Virtual and Physical Sensing & Actuation •  Sensor fusion and Actuation

–  Combine hardware and software sensors

•  Self-Awareness and Adaptation •  Combines Simple and Self-Aware adaptions •  A reflexive (Observe-Decide-Adapt) architecture to achieve

closed loop system control

•  Predictive Modeling & Learning •  Dynamic characterization of platform variability across

multiple levels of the system stack.


MPSoC with Simple Adaptation

Self-monitoring and simple adaptation

Simple Controller

QoS/ Goals output

Simple Adaptation Self-monitoring chip


Sentient Chips (Self-Awareness): CPSoC

Self-monitoring and behavior modeling

Adaptive Polices /

Controller / Governor

QoS/ Goals

System Behavior (Model Building)

measurement

input

Self-

Awar

e A

dapt

atio

n

output

Simple Adaptation Self-monitoring chip

[Sarma14, CODES+ISSS14]


AdaptivePolicies

CPSoC Fabric

VirtualSensors

PhysicalSensors NoC

PredictiveModels

Error±

Noise

Feedback

OptimizationPolices

Optimizing Loop

ReferenceBehaviors

adap

tatio

n

Virtual &Physical

Actuation±

TraditionalControl Loop

ApplicationGoals,

Intents, andHints

SystemPriorities and

Policies

Set PointGoals

Application Layer

CPSoC: Two Adaptation Loops

Simple Adaptation

Self-Aware Adaptation


AdaptivePolicies

CPSoC Fabric

VirtualSensors

PhysicalSensors NoC

PredictiveModels

Error±

Noise

Feedback

OptimizationPolices

Optimizing Loop

ReferenceBehaviors

adap

tatio

n

Virtual &Physical

Actuation±


ApplicationGoals,

Intents, andHints


Policies

Set PointGoals

Application Layer

1. CPSoC Simple Adaptation

Simple Adaptation



AdaptivePolicies

CPSoC Fabric

VirtualSensors

PhysicalSensors NoC

PredictiveModels

Error±

Noise

Feedback

OptimizationPolices

Optimizing Loop

ReferenceBehaviors

adap

tatio

n

Virtual &Physical

Actuation±


ApplicationGoals,

Intents, andHints


Policies

Set PointGoals

Application Layer

2. CPSoC Self-Aware Adaptation

Simple Adaptation



Adaptive, Reflexive CyPhy Middleware

•  Self-Aware Linux with CyPhy Middleware

•  Middleware Layer incorporates adaptation policies


Outline




•  Wrap-up


Sample Application and Use cases

•  Energy Efficiency (Throughput/Power) –  Dynamic Workloads –  Opportunistic Load balancing –  Adaptive Scheduler –  Evolutionary Approach

•  Thermal-Aware Performance –  Dynamic/Adaptive Parallelization –  Heterogeneous Architecture –  Adaptive Scheduling

•  Aging and Resilience –  Opportunistic Allocation –  Duty cycling of Active and Resting periods


Energy Efficiency Improvement

[Sarma13, CECS TR]

Goal: •  Energy Efficiency


0.00

1.00

2.00

3.00

4.00

5.00

6.00

1 3 5 7 9 11 13 15 17 19 21 23 25 27

Ene

rgy

Eff

icie

ncy

(Thr

ougp

ut/P

ower

)

Benchmarks [from PARSEC + synthetic]

Baseline Linux Oportunistic Linux

Energy Efficiency Improvement

51% Average Improvement for Quad-core

[Sarma13, CECS TR]


Thermal-Aware Performance

Goal: •  Improve

Throughput under max temperature & power constraint


Thermal-Aware Performance

For same power consumption and peak temperature, throughput improved

4 core

20 core, equal area

Throughput Improved by 70% -300% For same power & peak temp


CPSoC FPGA Prototype

NSF Expedition in Computing, Variability-Aware Software for Efficient Computing with Nanoscale Devices http://variability.org

Xilinx Vertex 6 Board

•  Goal: validate simulation studies for task migration, temperature, wear-out, etc.

•  Platforms: Virtex 5 and Virtex 6 •  Processor Core : SPARC/Leon 3,

Leon 2, S1 •  No Of Processor : 2-8 •  NoC : Mesh Connected, 200-800

MBPS Bandwidth •  On-chip Memory : 16-64kB per

core •  External Memory: 4 GB of DRAM •  Sensors:

–  Ring Oscillators: 20-50 –  Thermal: 20-40 –  Aging: 10-20 –  Razor/EDS: 20-50

•  OS: Linux 2.x/3.x [Sarma14, RSP14]


FPGA Library for CPSoC

• DPLL • Clock Gating • Bandwidth Controller • DVFS • Accelerators

• LEON • Alpha • OpenRISC • OpenSPARC • ARM/Ambit

• RO • Thermal • TDC • Reliability/Aging • PUFs • BIST, Scan etc

• sNOC • Aggregation Tree • Ring, custom

• cNoC • Mesh • Mesh edge extension

• Bus I/F converter • Peripherals Networks-

On-chip Sensors

Actuators Processors

& Memories

[Sarma14, RSP14]

Develop an FPGA library to construct CPSoC


CPSoC Multi-FPGA Distributed Platform

[Sarma13, CECS TR]


Task%0%

Task%n%App%0%

Task%0%

Task%n%App%n% Applica-ons%

Micro%Kernel/Linux%Kernel%%CyPhy%Middleware%

Gem5%Performance%Simulator%

Opera-ng%System%

McPAT%Power,%Area,%Timing%Models%Hotspot%

Aging%&%Reliability%

Vulnerability%

Process%Variability%Model%

Perf%Power%

Sensing%Interface% sNoC%&%

ISU%

Temp.%

Actua-on%%%Interface%

PlaOorm%

Mem

ory%(DRAMsim

2,%NVM

sim)%

CPSoC Simulation Framework

[Sarma14, RSP14]


Self-* Computing: Related Efforts

•  Autonomic Computing (IBM)

•  SEEC (MIT & Milano) –  Software centric/focused adaptation with homogeneous

arch –  Uses ODA loop for feedback control

•  Invasive Computing (Erlangen & KIT) –  Adaptive use of computing platform resources –  Distributed management –  No Self-modeling and system behavior identification


Self-Awareness in Software Systems (IBM’s Autonomic Computing)

[Autonomic Computing, IBM] [Kephart2003]


SEEC [MIT+Milano]

[Hoffmann2012, DAC]


Invasive Computing (Erlangen/KIT)

•  Definition: Invasive Programming denotes the capability of a program running on a parallel computer to request and temporarily claim processor, communication and memory resources and to be capable to subsequently free these resources again.

Program A Program A Program B Program B

Program C Program C [Kobe11] [www.invasic.de/]


Outline




•  Wrap-up


CPSoC Research Direc7ons

•  Cross-Layer Physical/Virtual Sensing & Actuation

•  Self-Awareness and Adaptation

•  Predictive Modeling & Learning


Key Take-Aways CPSoC: First step towards Sentient Chips

Key CPSoC features:

•  Cross-Layer Virtual and Physical Sensing & Actuation

•  Combine hardware and software sensors

•  Self-Awareness and Adaptation •  Simple and Self-Aware adaptions •  Adaptive, reflexive architecture (Observe-Decide-Adapt)

•  Predictive Modeling & Learning •  Dynamic platform characterization across multiple abstraction

levels


Acknowledgements •  Collaborating Faculty:

– UCI: Profs. Dutt, Alex Nicolau, Nalini Venkatasubramanian

– UCLA: Prof. Puneet Gupta – TU Wien, Austria: Prof. Axel Jantasch

•  NSF Variability Expedition Project Team – www.variability.org


Thank You!

www.variability.org NSF Variability Expedition


References •  S.Sarma, N.Dutt, A. Jantasch “Towards Smart Embedded Systems: A Self-Aware System-on-Chip (SoC)

Perspective,” ACM TECS, Sept 2015.

•  [Sarma14] S. Sarma, N. Dutt, P. Gupta, A. Nicolau, N. Venkatasubramanian, “On-Chip Self-Awareness Using Cyberphysical-Systems-On-Chip (CPSoC)” (CODES+ISSS'14)

•  [Sarma14] S. Sarma, N. Dutt, “FPGA Emulation and Prototyping of a CyberPhysical-System-On-Chip (CPSoC)” RSP’14.

•  [Hoffmann12] Hoffmann et al. “Self-aware Computing in the Angstrom Processor”, DAC 2012. •  [Invasive] Invasive Computing. TCRC 89, 2014. [Online]. Available: http://invasic.informatik.uni-

erlangen.de/en/index.php •  [SPP1500] Dependable Embedded Systems. DFG SPP 1500, 2014. [Online]. Available:

http://spp1500.itec.kit.edu/ •  [Kephard03] J. Kephart et al., “The vision of autonomic computing,” Computer, vol. 36, no. 1, pp. 41 – 50,

jan 2003. •  [Sarma13] S.Sarma et al., “Cyberphysical System-On-Chip (CPSoC): Sensoractuator rich self-aware

computational platform,” University of California Irvine, Tech. Rep. CECS TR-13-06, May 2013. •  [Gallo] David Gallo, Underwater astonishments, TED Talks.

http://www.ted.com/talks/david_gallo_shows_underwater_astonishments •  [Harvard] Programmable self-assembly in a thousand-robot swarm,

http://www.seas.harvard.edu/news/2014/08/self-organizing-thousand-robot-swarm?utm_source=youtube&utm_medium=social&utm_campaign=harvard-youtube

•  [RoboBee] http://robobees.seas.harvard.edu/


Self-Awareness in Robotics

[RoboBee, Harvard ]

“INSPIRED by the biology of a bee and the insect’s hive behavior ... we aim to push advances in miniature robotics and the design of compact high-energy power sources; spur innovations in ultra-low-power computing and electronic “smart” sensors; and refine coordination algorithms to manage multiple, independent machines.”

[http://robobees.seas.harvard.edu/]


Core Single-Thread Mode

Core Throughput

Mode

Core Throughput

Mode

A B C D

E F G H

Throughp

ut

Core

Throughp

ut

Core

Throughp

ut

Core

Throughp

ut

Core

ISU

Mem

orie

s

Introspective Sentient Unit (ISU)

R R R R

R R R R

A B C D E F G H

R

I/F

R

Separate sNoC with Introspective Sentient Unit (ISU)


Mul7-‐Layer-‐NoC

Core

cNoC router

sNoC router

Sensor interconnect

Core interconnect

sNoC Manager Task Manager

Legend

Coexis3ng independent mul3-‐layer networks suppor3ng both regular and irregular architectures


A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A15#

A7#A7#A7#

A7#

A9#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#

A9#

A7#A7#A7#

A7#A7#A7#

M3#A7#A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#M3#

A7#A7#A7#

A7#A7#A7#

A9#

A7#

A7#A7#A7#

A7#A7#A7#

A7#A7#M3#

A7#A7#A7#

A7#A7#A7#

A9#

A7#

A7#A7#A7#

A15#

A7# A9#A15#

A9#A7#A7#

A7#M3#

A7#

A7#A7#A7#

A9#

A9#

A7# A9#A15#

A9#A7#A7#

A7#A7#A7#

A7#A7#A7#

A9#

A9#

LLC#

A7# A9#A15#

A9#A7#A7#

A7#A7#A7#

A7#A7#A7#

A9#

A9#

A7# A9#A15#

A9#A7#A7#

A7#M3#

A7#

A7#A7#A7#

A9#

A9#

(a)# (b)#

(c)# (d)#

A7# A9#A15#

A9#A7#A7#

A7#M3#

A7#

A7#A7#A7#

A9#

A9#

x1# A9#A15#

A9#x4#x7#

x2#x5#x8#

x3#x6#x9#

A9#

A9#

LLC#

A9#A15#

A9#

A9#

A9#

A7# A9#A15#

A9#A7#A7#

A7#M3#

A7#

A7#A7#A7#

A9#

A9#

x1#x4#x7#

x2#x5#x8#

x3#x6#x9#

Multi-ISU for Clusters

Documents

SentientChips-Using-Machine-Learning