Sequential circuits - Amazon Web Serviceskth.s3-website-eu-west-1.amazonaws.com/ie1204_5/slides/...Sequential circuits William Sandqvist [email protected] If the same input may produce

Sequential circuits

William Sandqvist [email protected]

If the same input may produce different output signal, we have a sequential logic circuit. It must then have an internal memory that allows the output to be affected by both the current and previous inputs! Logic circuit

Same input can produce different output

Moore-machine


NEXT STATE DECODER STATE REGISTER

OUTPUT DECODER

State

Clk

Input- signals

Output- signals

For Moore machine the outputs depends on the inputs and the internal state. The internal memory is the state register consisting of D flip-flops.


State register D-flip-flops State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).

NEXT STATE DECODER

STATE REGISTER

OUTPUT DECODER

Output- signals

Input- signals


State register D-flip-flops

NEXT STATE DECODER

STATE REGISTER

OUTPUT DECODER

Output- signals

Input- signals

?

?

State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).


NEXT STATE DECODER

STATE REGISTER

OUTPUT DECODER

Output- signals

Input- signals

?

?

State register D-flip-flops

!

!

State register D flip-flops slows down the race between signals until the value is stable. (Compare with the tollbooth).

Quickie Question … flip-flop Which of the following timing diagram is valid for a

edge-triggered D flip-flop?

Alt: A Alt: B Alt: C

D Q

Clock

In1

In2

Out

In1

In2

Out

In1

In2

Out

In1

In2

Out


Quickie Question … flip-flop

Alt: B Alt: C

D Q

Clock

In1

In2

Out

In1

In2

Out

In1

In2

Out

In1

In2

Out


Alt: A D is copied to output at the edge, when Clock goes from 0 to 1

Which of the following timing diagram is valid for a edge-triggered D flip-flop?

Quickie Question … Latch Which of the following timing diagram is valid

for a D Latch?



D Q

Enable

In1

In2

Out

In1

In2

Out

In1

In2

Out

In1

In2

Out



D Q

Enable

In1

In2

Out

In1

In2

Out

In1

In2

Out

In1

In2

Out

D is connected to output when Enable is 1, and is locked when Enable is 0

Quickie Question … Latch Which of the following timing diagram is valid

for a D Latch?

Design: ”two consecutive”


Sequence Detector. If w has been 1 in two (or more) consecutive clock then z = 1.

w w z

C Clk

Specification Sequence circuit has an input w and an output z If input w has been 1 in during the current and previous clock cycle then z will be set to 1 Use a Moore machine with D-flip-flops to realizing the design.

(Reset)

Statediagram ”two consecutive”


C z 1 = ⁄

Reset

B z 0 = ⁄ A z 0 = ⁄ w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

State

State transition

State name Output value

A zero B single one C two or moore consecutive

State table


Present Next state Output state w = 0 w = 1 z

A A B 0 B A C 0 C A C 1

Three states – two flip-flops needed to hold state numbers!

”two consecutive” as Moore-machine


Combinational circuit

Combinational circuit

Clock

y 2

z

w y 1 Y 1

Y 2

Designdecissions


• The designer must decide which flip-flops? to be used

D-, T-, or JK-flip-flop • The designer must choose the code for each state

Designbeslut


This time:

• D-flip-flop • State code A = 00, B = 01, C = 10 • The code word 11 should not occur. We choose don’t care.

Coded state table


Present Next state

state w = 0 w = 1 Output z

A 00 00 01 0 B 01 00 10 0 C 10 00 10 1

11 dd dd d

12YY12 yy 12YY

2 1 2 1 2 1( ) ( )Y Y f y y w z f y y= =

A = 00 B = 01 C = 10

Next state decoder


)()()()(

12

1211221212

yyfzwyyfYwyyfYwyyfYY

====

The Next state decoder consists of two logic networks available as input network to the two flip-flops. In order to minimize logic networks, we enter the truth tables in the form of Karnaugh maps.

From coded statetable to Karnaughmap


w 00 01 11 10

0

1

0

1 0

y 2 y 1

d

d

0

0

0

Y1 = wy 1y 2

1Y

w 00 01 11 10

0

1

0 d

1 d

y 2 y 1

0

0

0

1

2Y

)( 21

212

yywwywyY

+==+=

)()()( 1211221212 wyyfYwyyfYwyyfYY ===

Output decoder


0 1

0

1

0

d

y 1

0

1

y 2

z = y2

)( 12 yyfz =

Implementation


z = y2

Y1 = wy 1y 2

)( 21

212

yywwywyY

+==+=

Timing diagram ”two consecutive”


t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0

1

0

1

0

1

0

Clock

w

y 1

y 2

1

0 z

State transitions occurs only on the positive clock edge!

In other terms


)()()( 1211221212 wyyfywyyfywyyfyy === ++++Exercises and Hemert-book:

+yyPresent state Next state

With another lineup


)()()( 1211221212 wyyfywyyfywyyfyy === ++++

You could directly write down the codet state table as a ”Karnaugh map”.

In exercises we use this method

A

B

C


Mealy-machine


NEXT STATE DECODER STATE REGISTER

OUTPUT DECODER

State

Clk

Input- signals

Output- signals

In a Mealy Machine output signals depends on both the current state and the inputs.

State diagram Mealy


A

w 0 = z 0 = ⁄

w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄

Reset w 1 = z 0 = ⁄

Value of output signal State name

Value of input signal

”Two consecutive” • The state diagram for the Mealy-machine only needs two states • Output signal depends booth on states and input.

State table


Present Next state Output z state w = 0 w = 1 w = 0 w = 1

A A B 0 0 B A B 0 1

A

w 0 = z 0 = ⁄

w 1 = z 1 = ⁄ B w 0 = z 0 = ⁄

Reset

w 1 = z 0 = ⁄

Two states – only one flip-flop is needed!

Coded state table


Present Next state Output state w = 0 w = 1 w = 0 w = 1

y Y Y z z

A 0 0 1 0 0 B 1 0 1 0 1

)()( wyfzwyfY ==

ywzwY ==Directly from the table:

A = 0 B = 1

Implementation


Clock

Resetn

D Q

Q

w

z

y

Timing diagram


t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0 1 0

1 0

1 0

Clock

y

w

z

• The output may change during the clock period, since it is a function of the input signal • Compared to Moore machine the Mealy machine is moore 'responsive' (bit sequence is detected in t4 compared to t5 for the Moore-machine)

Mealy with output register


Clock Resetn

D Q

Q

w

z

y

D Q

Q

Z

• The disadvantage of the Mealy machine is that the output can be changed during the entire clock period • You can add a register (flip-flop) at the end so to synchronize the output with the clock edge

Timing diagram with output register


t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 1 0

1 0

1 0

1 0

Clock

y

w

z

1 0

Z

With an output register there are no longer any differences between the timing diagrams!

Moore vs Mealy


• Moore-machine output values depend only on the current state • Mealy-machine output values depend on the current state and the values of the input signals • Mealy-machine often uses fewer states • Mealy-machine output signals are not inte synchronized with the clock, why you often has to add an output register


Selection of state encoding


Selection of state encoding can play a major role in implementation as it affects the logic for

• Next-state-decoder • Output decoder

”two consecutive” state diagram


C z 1 = ⁄

Reset

B z 0 = ⁄ A z 0 = ⁄ w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

State code = Binary


Present Next state

state w = 0 w = 1 Output

y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0 B 01 00 10 0 C 10 00 10 1

11 dd dd d

A = 00 B = 01 C = 10 11

Realization (Binary code)


2 D-flip-flops 2 AND-gates 1 OR-gate

State code = Gray code


Present Next state

state w = 0 w = 1 Output

y 2 y 1 Y 2 Y 1 Y 2 Y 1 z

A 00 00 01 0 B 01 00 11 0 C 11 00 11 1

10 dd dd d

• In the Gray-code only one bit at a time is changed, eg. 00, 01, 11, 10 • Gray-code is good for counters

A = 00 B = 01 C = 11 10

Realization (Gray code)


D Q

Q

D Q

Q

Y 2

Y 1 w

Clock

z

y 1

y 2

Resetn

2 D-flip-flops 1 AND-gate

As the Gray code did well in this case this sequential circuit has obviously has “counting properties”

One-Hot-encoding


• One-hot-encoding uses one flop-flop per state • For each state one bit is ‘hot’ (1), all other bits are 0, eg. 0001, 0010, 0100, 1000 • One-hot encoding minimizes the combinatorial logic, but increases the number of flip-flops!

What code should be chosen?


• There is not a code that is the best in every situation, it all depends on the state diagram • You can also have your 'own codes' that fits into the design, eg. 00, 11, 10, 01



Example. - wait - cw - wait - ccw -

q1

q2

013112101000

1

2

1

2

1

2

1

2

qqZqqZqqZqqZ

wait

cw

wait

ccw With this state encoding (Graycode) we need no output decoder!



Can you can set up the encoded state table and Karnaugh maps by your self … ?

q1

q2




q1

q2

211212 qiqiqqiqiq +=+= ++


- wait - cw - wait - ccw -

211212 qiqiqqiqiq +=+= ++

With NAND-gates


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Sequential circuits - Amazon Web Serviceskth.s3-website-eu-west-1.amazonaws.com/ie1204_5/slides/...Sequential circuits William Sandqvist [email protected] If the same input may produce