Seteo de Vrbild

7/30/2019 Seteo de Vrbild

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101 Innovation DriveSan Jose, CA 95134www.altera.com

Section I. DSP Builder Advanced Blockset User Guide

Document Version: 2.1

Document Date: April 2011

HB_DSPA_ADV_UG-2.1
http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.altera.com/


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Copyright 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all otherwords and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and othercountries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap-plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use ofany information, product, or service described herein e xcept as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version ofdevice specifications before relying on any published information and before placing orders for products or services.


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Preliminary

Contents

About This Section

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Chapter 1. About the DSP Builder Advanced BlocksetArchitecture versus Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Base Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Signals Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Device Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

FFT Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ModelBus Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ModelPrim Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14ModelIP Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Cycle Accuracy and Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Sample Rate and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Interoperability with the Standard Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Learning to Use the Advanced Blockset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2. Design FlowSetting Up Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Creating Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Writing Custom Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Implementing your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Staging your Design into Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Including Base Library Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Choosing the ModelIP Library or the ModelPrim Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Using ModelPrim Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29ModelPrim Subsystem Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210Specifying the Output Data Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210SynthesisInfo Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211Using Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Using ModelPrim Blocks Outside ModelPrim Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Converting Blocks and Specifying Output Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Using Interfaces as Subsystem Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215Using Interfaces as Scheduling Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Connecting Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Using Latency Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219Using Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

Use Multichannel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Using Vectorized Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Connecting Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Avoiding Minimum Latency in a Feedback Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227Managing your Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

Creating User Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228Revision Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228


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Preliminary

Verify the Design in Simulink and MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Creating a Plan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Using References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230Setting up Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230Analyzing your Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231Managing Basic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

Using a Testbench Checklist for Simulink Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231Exploring Design Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232Managing Bit Growth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232Implementing Rounding and Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

Verifying and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233Running an Automatic Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234Running an Automatic Testbench in ModelSim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Running an Automatic Testbench in MATLAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Simulating in the ModelSim Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

Integrating into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237Adding your Design to a Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Adding a DSP Builder Advanced Blockset Design to an Existing Quartus II Project . . . . . . . . . 240Adding Advanced Blockset Components to SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Interfacing with a Processor Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Assigning Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Integrating with SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241Building System Components with Avalon-ST Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 241Nios II Processor Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

Chapter 3. Design Examples and Reference DesignsOpening a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31


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Preliminary

Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Copying a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Running a Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Fine Doppler Estimator 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Floating Point Mandlebrot Set 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Floating Point Matrix Multiply 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Position, Speed, and Current Control for AC Motors 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Black-Scholes Floating Point 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313Single-Precision Complex Floating-Point Matrix Multiply Design Example . . . . . . . . . . . . . . . . 313Double-Precision Real Floating-Point Matrix Multiply Design Example . . . . . . . . . . . . . . . . . . . 313Single-Precision Real Floating-Point Matrix Multiply Design Example . . . . . . . . . . . . . . . . . . . . 313

Primitive FIR with Back Pressure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Primitive FIR with Forward Pressure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314Kronecker Tensor Product 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Rectangular Nested Loop 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315Triangular Nested Loop 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316Sequential Loops 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316Parallel Loops 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31616-Channel DDC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

16-Channel DUC 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3172-Channel DUC 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3172-Antenna DUC for WiMAX 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Decimating CIC Filter 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Interpolating CIC Filter 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Single Rate FIR Filter 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Decimating FIR Filter 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319Interpolating FIR Filter 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Fractional Rate FIR Filter 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Half Band FIR Filter 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Root Raised Cosine FIR Filter 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Fractional FIR Filter Chain 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Super-Sample FIR Filter 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321Filter Chain with Forward Flow Control 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322Multiple Coefficient Banks Interpolating FIR Filter 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322NCO 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323Real Mixer 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323Complex Mixer 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324Four Channel, Two Banks NCO 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324Four Channel, Four Banks NCO 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Four Channel, Eight Banks, Two Wires NCO 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326Four Channel, 16 Banks NCO 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326ModelIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Hello World 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327Fibonacci Series 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Automatic Gain Control 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Multi-Channel IIR Filter 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32888 Inverse Discrete Cosine Transform 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Quadrature Amplitude Modulation 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Radix 2 Streaming FFT 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330Radix 4 Streaming FFT 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3304K FFT 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3318K FFT 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314K IFFT 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332


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8K IFFT 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332Test CORDIC Functions Using Primitive Blocks 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Test CORDIC Functions Using the CORDIC Block 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Folded Color Space Converter 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Folded Single-stage IIR Filter 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334Folded 3-stage IIR Filter 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

Folded Primitive FIR Filter 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Hybrid Direct Form and Transpose Form FIR Filter 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Digital Predistortion Forward Path 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Run-time Configurable Decimating and Interpolating Half-rate FIR Filter 36 . . . . . . . . . . . . . . . . . 336Matrix Initialization of Vector Memories 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Matrix Initialization of LUT 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Vector Initialization of Sample Delay 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Memory-Mapped Registers 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Scale 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338Local Threshold 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

Reference Designs 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3384-Carrier, 2-Antenna W-CDMA DDC 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3381-Carrier, 2-Antenna W-CDMA DDC 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

4-Carrier, 2-Antenna W-CDMA DUC 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3401-Carrier, 2-Antenna W-CDMA DDC 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3404-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 32 41 3414-Carrier, 2-Antenna High-Speed W-CDMA DUC at 368.64 MHz with Total Rate Change 48 42 3424-Carrier, 2-Antenna High-Speed W-CDMA DUC at 307.2 MHz with Total Rate Change 40 42 . 3421-Antenna WiMAX DDC 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3432-Antenna WiMAX DDC 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3441-Antenna WiMAX DUC 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3442-Antenna WiMAX DUC 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345Single-Channel 10-MHz LTE Transmitter 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

Chapter 4. ModelIP TutorialOpening the NCO Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Setting the Configuration Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Configuring the NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Simulating the Design Example in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

Exploring the Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412Instantiating the Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413Customizing the NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415

Changing the Number of Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415Increasing the Spurious Free Dynamic Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417

Hardware Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

Chapter 5. ModelPrim Tutorial

The Fibonacci Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Creating the Fibonacci Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Create a New Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Add Blocks from the ModelPrim Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Create a Synthesizable Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Complete the Top-Level Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53


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Preliminary

Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Using Vector Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Using Complex Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Exploring the Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Simulating the RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ModelPrim Subsystem Designs to Avoid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Common Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510Timed Feedback Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510Loops, Clock Cycles and Data Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

Chapter 6. System TutorialSystem Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61The DDC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Signals Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Source Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Sink Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Tool Interface Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

DDCChip Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Primary Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Merge Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66NCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Mixer Scale Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67DecimatingCIC and Scale Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Decimating FIR Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613Exploring the Generated Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

Compiling with the Quartus II Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Chapter 7. Latency ManagementZero Latency Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Nonexplicit Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Distributed Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Latency and fMAX Constraint Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Chapter 8. FoldingTime-Division Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Folded Subsystem without Time Division Demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Folded Subsystem with Time Division Demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83When to Use Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Effects of Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Effects on Manual Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Effects on Combinational Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Chapter 9. Floating-Point Data TypesConverting Between Floating- and Fixed-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Interacting with Other Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Pipelining Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Accuracy and Automatic Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93


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viii


Preliminary

Arithmetic Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Floating Point Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Word FormatsSingle Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Internal Floating Point NumberSingle Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Addition and Subtraction FormatSingle Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Multiplication and Division FormatSingle Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Double Precision Word Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Internal Floating Point NumberDouble Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Addition and Subtraction MantissaDouble Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Multiplication, Division, and Function MantissasDouble Precision . . . . . . . . . . . . . . . . . . . . . . . . 98

Floating-Point Type Propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Special Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910Floating-Point Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910

Chapter 10. Flow ControlFlow Control Using Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Forward Flow Control Using Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Flow Control Using FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Flow Control and Back Pressure Using FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Flow Control using Simple Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Flow Control Using the ForLoop Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Chapter 11. DSP Builder Standard and Advanced Blockset InteroperabilityCombined Blockset Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Combined Blockset Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Archiving Combined Blockset Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112Advanced Blockset Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112

Additional Information

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info1


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Preliminary

About This Section

Revision HistoryThe following table shows the revision history for this section.

Date Version Changes Made

April 2011 2.1 Reordered some of the information in the chapters

Added Getting Startedchapter

Added Floating-Point Data Typeschapter

Updated description for multiple coefficient banks interpolating FIR filter

Added the following two examples:

Fine Doppler Estimator

Position, Speed, and Current Control for AC Motors

December 2010 2.0 Added the following design example descriptions:

Rectangular nested loop

Triangular nested loop

Sequential loops

Partial loops

Folded color space converter

Folded single-stage IIR filter

Folded 3-stage IIR filter

Folded primitive FIR filter

Hybrid direct form and transpose form FIR filterDigital predistortion forward path

Run-time configurable decimating and interpolating half-rate FIR filter

Matrix initialization of vector memories

Matrix initialization of LUT

Vector initialization of sample delay

Added General Primitive Library Guidelines

June 2010 1.0 First published. Replaces DSP Builder Advanced Blockset User Guide


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iv About This Section

Revision History


Preliminary


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Preliminary

1. About the DSP Builder AdvancedBlockset

The DSP Builder advanced blockset adds specialized Simulink libraries to the

MATLAB design environment that allow you to implement DSP designs quickly andeasily. The advanced blockset is based on a high-level synthesis technology thatoptimizes the high-level, untimed netlist into low level, pipelined hardware for yourtarget Altera FPGA device and clock rate. DSP Builder writes out the hardware asplain text VHDL, with scripts that integrate with the Quartus II software and theModelSim simulator.

The combination of these features allows you to create a design without needingdetailed device knowledge, and generate a high quality implementation that runs ona variety of FPGA families with different hardware architectures.

By specifying your desired clock frequency, you can solve timing closure issues bygenerating register transfer level (RTL) code that pipelines to meet your goal. Filtersin the blockset automatically use a high-clock rate to increase folding, and reducehardware size.

DSP Builder advanced blockset allows you to manually describe algorithmicfunctions and apply rule-based methods to generate hardware optimized code.

FPGA design is highly implementation focused. You exploit multipliers based on theavailable features, you map shift registers to memories, and balance overall deviceresources by the chosen implementation to make sure you do not force a design into alarger device based solely on suboptimal memory or multiplier implementations.State machines match pipeline latencies of memory or multiplier structures, and youcarefully place routing registers in key structures to account for routing delays to andfrom various hard blocks that complicate FPGA placement. Floor planning oftenallows you to reduce compilation times and help fit a marginal design because board

prototypes are already finalized.

DSP Builder advanced blockset separates the algorithm from the tedious rules-basedimplementation. This design process results in new opportunities for system-leveldesign.

DSP Builder advanced blockset focuses on the design architecture (notimplementation) and text-based entry where you describe the design as naturally aspossible. It is very difficult to know what is the highest amount of time-divisionmultiplexing (TDM), or folding, you can apply to a design. If the design runs too fast,the design does not close timing, if the design runs too slowly, the design may wastemultipliers.

In a DSP-based design, there are many tradeoffs: bit precision, and memory efficiency,

for example, but the biggest tradeoff is the algorithm. How much value does using amore sophisticated channel estimation algorithm give you in system versus howmuch more it costs in FPGA resources? These are all important tradeoffs, but aregenerally made with incomplete information. DSP Builder advanced blockset allowsyou to measure these tradeoffs as they can be parametrically swept, or quicklyentered to measure real results in hardware. DSP Builder advanced blockset can yield

better than hand-coded results in practice.


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12 Chapter 1: About the DSP Builder Advanced Blockset

Architecture versus Implementation


Preliminary

Consider this approach when starting a design, to maintain flexibility andparameterization in the design, so you can sweep these parameters.

While understanding how to efficiently implement a design in an FPGA is alwaysuseful and can augment the tools automated features, significant gains can be realized

by starting from a point of algorithmic purity, and considering implementationspecific optimizations as necessary. Architecture first, implementation second.

1 The DSP Builder advanced blockset uses Simulink fixed-point types for all operations.

You can use the advanced blockset entirely independently of the DSP Builderstandard blockset, or you can embed its blocks in top-level DSP Builder designs thatuse the standard blockset.

f For information about interoperability with the DSP Builder standard blockset, referto Chapter 11, DSP Builder Standard and Advanced Blockset Interoperability.

Architecture versus ImplementationDSP Builder advanced blockset focuses on the design architecture (notimplementation) and text-based entry where you describe the design as naturally aspossible. It is very difficult to know what is the highest amount of time-divisionmultiplexing (TDM), or folding, you can apply to a design. If the design runs too fast,the design does not close timing, if the design runs too slowly, the design may wastemultipliers.

In a DSP-based design, there are many tradeoffs: bit precision, and memory efficiency,for example, but the biggest tradeoff is the algorithm. How much value does using amore sophisticated channel estimation algorithm give you in system versus howmuch more it costs in FPGA resources? These are all important tradeoffs, but aregenerally made with incomplete information. DSP Builder advanced blockset allows

you to measure these tradeoffs as they can be parametrically swept, or quicklyentered to measure real results in hardware. DSP Builder advanced blockset can yield

better than hand-coded results in practice.

Consider this approach when starting a design, to maintain flexibility andparameterization in the design, so you can sweep these parameters.

While understanding how to efficiently implement a design in an FPGA is alwaysuseful and can augment the tools automated features, significant gains can be realized

by starting from a point of algorithmic purity, and considering implementationspecific optimizations as necessary. Architecture first, implementation second.

LibrariesThe advanced blockset comprises the following Simulink libraries:

Base blocks

FFT blockset

Filters (ModelIP)

ModelBus


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Chapter 1: About the DSP Builder Advanced Blockset 13

Libraries


Preliminary

ModelPrim

ModelVectorPrim

Waveform synthesis (ModelIP)

f For more information about the advanced blockset libraries, refer to the DSP BuilderAdvanced Blockset Libraries section in volume 3 of the DSP Builder Handbook.

Base Blocks

The top-level design of a DSP Builder advanced blockset design is a testbench andmust include Control and Signals blocks. A design may include any number ofsubsystems that can combine blocks from the DSP Builder advanced blockset with

blocks from the MATLAB Simulink libraries.

The functional subsystem containing a Device block marks the top-level of the FPGAdevice and specifies the target device that the generated hardware uses.

Altera provides other blocks to control and view the signals in your design, and toautomatically load your design into the ModelSim simulator or the Quartus IIsoftware.

Control Block

The Control block traverses your design, synthesizes the individual ModelPrim orModelIP blocks into RTL, and maintains an internal data flow representation of yourdesign. Simulink simulation uses the internal representation of your design exampleand to write out the RTL and scripts for other tools. A single Control block must bepresent in your top-level model.

1 DSP Builder applies globally the options in the Control block to your design.

Signals BlockEach design example must have a Signals block, which you should place at the toplevel of your model. The Signals block specifies the details for the clocks and resetsthat drive the generated logic.

The DSP Builder advanced blockset uses a single system clock to drive the maindatapath logic, and, optionally, a second bus clock to provide an external processorinterface. It is most efficient to drive the logic at as high a clock rate as possible. Thestandard DSP Builder blockset is better for managing multiple clock domains forexample, when interfacing to external logic.

The Signals block allows you to name the clock, reset, and memory bus signals thatthe RTL uses, and also provides the following information, which is important for the

clock rate: To calculate the ratio of sample rate to clock rate determine the amount of folding

(or time-division multiplexing) in the ModelIP filters.

To determine the pipelining required at each stage of logic. For example, thedesign modifies the amount of pipelining that hard multipliers uses, and pipelineslong adders into smaller adders based on the absolute clock speed in relation tothe FPGA family and speed-grade you specify in the device block.
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Libraries


Preliminary

1 Cyclonedevice families do not support a separate bus clock due to the limitedmultiple clock support in block RAMs on those devices. For this reason, you mustde-activate the separate bus clock option for the Signals block when using Cyclonedevice families.

Device Block

The Device block marks a particular Simulink subsystem as the top-level of an FPGAdevice and allows you to specify the target device and speed grade for the device.

1 All blocks in subsystems below this level of hierarchy, become part of the RTL design.All blocks above this level of hierarchy become part of the testbench.

FFT Blockset

The FFT Blockset library contains common blocks that support fast Fourier transform(FFT) design. It also includes several blocks that support the Radix-22 algorithm.

f For information about the Radix-22 algorithm, refer toA New Approach to Pipeline FFTProcessor Shousheng He & Mats Torkleson, Department of Applied Electronics, LundUniversity, Sweden.

ModelBus Blocks

The ModelBus library provides memories and registers that you can access in yourDSP datapath with an external interface. You can use these blocks to configurecoefficients or run-time parameters and to read calculated values. This library alsoincludes blocks that you can use to simulate the bus interface in the Simulinkenvironment.

ModelPrim Blocks

The ModelPrim library allows you to create fast efficient designs captured in thebehavioral domain rather than the implementation domain by combining primitivefunctions. For example, you can use a Delay block and let DSP Builder decide how toimplement that delay. You do not need to understand the details of the underlyingFPGA architecture, as the ModelPrim blocks automatically map into efficient FPGAconstructs.

ModelIP Blocks

The ModelIP (filters and waveform synthesis) libraries include parameterizablemultichannel filters and waveform synthesis blocks that allow you to quickly createdesigns for digital front-end applications. Altera provides the ModelIP blocks in the

following libraries:

The Filters library contains several decimating and interpolating cascadedintegrator-comb (CIC), and finite impulse response (FIR) filters includingsingle-rate, multi-rate, and fractional-rate FIR filters.

The Waveform Synthesis library contains a numerically controlled oscillator(NCO), complex mixers, and real mixers.


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Chapter 1: About the DSP Builder Advanced Blockset 15

Cycle Accuracy and Latency


Preliminary

After you run a Simulink simulation, DSP Builder updates the online Help page foreach ModelIP block to show specific design documentation describing itsimplementation in your design. This information typically includes the latency, portinterface, and resource utilization. For the blocks in the Filters library, the updatedHelp page also includes details of the parameterization, input and output dataformats, and memory interface.

To display the latency that a ModelIP block adds, add the% parameter asannotation on the block.

After you run a simulation, the added latency shows as a text annotation below theblock.

1 You cannot use latency constraints with folding.

Cycle Accuracy and LatencyThe DSP Builder advanced blockset supports the following design styles:

ModelIP blocks designs, such as the FIR and CIC filters. These blocks are 100%cycle accurate and the Simulink behavior represents exactly the RTL behavior. Youcan turn on display of the latency added by each block.

Synthesized ModelPrim block designs from the ModelPrim library. These blocksare 100% cycle accurate at their boundaries, therefore interfacing to other blocks isstraightforward.

You can also use ModelPrim blocks outside of synthesizable subsystems, to createglue logic around other subsystems. The Boolean logic and delay blocks are cycleaccurate, but other ModelPrim blocks are not.

The ModelPrim blocks are untimed circuits, so are not cycle accurate. In fact, there isnot even a one-to-one mapping between the blocks in the Simulink model and the

blocks implement your design in RTL. It is this decoupling of design intent fromdesign implementation that gives the productivity benefits. The boundary betweenthe untimed block and the outsized, cycle accurate block is the ChannelOut block.This block models the additional delay that the RTL introduces, so that data going into the ChannelOut block delays internally, before DSP Builder presents it externally.The latency of the block displays on the ChannelOut mask.

To read the added latency value for a ModelIP block (or for the ChannelOut ModelIPblock), select the block and type the following command:

get_param(gcb, 'latency')

You can also use this command in an M-script. For example when you want to use thereturned latency value to balance delays with external circuitry.

1 If you use an M-script to get this parameter and set latency elsewhere in your design,by the time it updates and sets on the ModelIP block, it is too late to initialize thedelays elsewhere. You must run your design twice after any changes to make sure thatyou have the correct latency. If you are scripting the whole flow, your must run oncewith end time 0, and then run again immediately with the desired simulation endtime.

f For more information about latency, refer to Latency Management on page 71.


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Sample Rate and Clocks


Preliminary

Sample Rate and ClocksSimulink uses the time-step representation of the system clock rate to represent adesign. Although, the multi-rate system has multiple sample rates, the Simulinkmultiple sample-time features does not represent them. Other Simulink-based designsystems disable the hardware based on the sample time (wasting hardware that is

inactive for much of the time).The sample rate is the rate at which real data is clocked through the system at anypoint. In a multi-rate environment, the sample rate may vary along the datapath.

The datapath components in the DSP Builder advanced blockset use a single clockrate. An external processor uses a separate bus clock to read and write any ModelPrimregisters or shared memories and ModelIP block parameters through an AvalonMemory-Mapped (Avalon-MM) interface.

The bus clock is usually not performance critical and can run at a lower clock rate,which allows easier timing closure in many cases. Running the clock as an integerfraction of the system clock rate ensures that no timing issues exist and that bothclocks have co-incident edges. In many cases, the bus clock can have any frequency.

Set the clock rates in the Signals block (Signals Block on page 13).

1 The memory-mapped input and output registers clear when the system is reset butDSP Builder retains the contents of the dual memory that the FIR Filter, NCO, andModelBus blocks use.

f For information about the Avalon-MM Interface, refer to theAvalon InterfaceSpecifications.

Interoperability with the Standard BlocksetYou can use the advanced blockset in a design flow that includes blocks from the DSP

Builder standard blockset.

f For information about interoperability, refer to Chapter 11, DSP Builder Standard andAdvanced Blockset Interoperability.

Learning to Use the Advanced BlocksetTo learn about the advanced blockset examine the design examples in Chapter 3 andperform the following tutorials in Chapters 4, 5, and 6:

The ModelIP Tutorial (Chapter 4) shows how to use the ModelIP NCO block tocreate a customized NCO. The tutorial performs RTL simulation in ModelSim,

compiles your design in the Quartus II software, and instantiates your design as asubsystem in the SOPC Builder.

The ModelPrim Tutorial (Chapter 5) shows how you can use blocks from theModelPrim library to build a simple design.

TheSystem Tutorial (Chapter 6) shows how you can plug blocks together to createa digital downconverter (DDC).
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Preliminary

2. Design Flow

The top-level design in Simulink is a testbench that must contain DSP Builder

advanced blockset blocks that define system parameters. When the basicconfiguration is complete, you can start your top-level test plan. With the testbench inplace, model your algorithm using a hierarchical approach. The main entity in thetop-level testbench is often implemented in a FPGA. Within this entity are manysubsystems that model functions and modules.

During the design process you can simulate and debug your design in MATLAB andthe Simulink environment. Simulink generates synthesizable VHDL codes for thedesign at the start of every Simulink simulation. When these subsystems and modulesare verified, you can perform system-level verification and debugging, in bothSimulink and ModelSim. The final step is compilation in the Quartus II software andhardware verification.

Figure 21 shows the typical design flow.


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22 Chapter 2: Design Flow


Preliminary

Figure 21. Design Flow

(Optional) MATLABreference model fixed

or floating point

Simulink Setup

Scripts for stimulus andoutput analysis

MATLAB configuration scriptfor parameterization

Design implementation inDSPBuilder advanced

blockset

Design and tradeoffexploration

Verification in MATLAB andModelSim

Verification in hardware

Meeting resourcerequirement?

Successful?

Hardware and systemintegration in the

QuartusII software

Y

Early verification in MATLABor Simulink

Functionality correct ?

N

N

N

Y


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Chapter 2: Design Flow 23


Preliminary

The design flow involves the following steps:

1. Develop reference models in MATLAB. The models can be either fixed-point orfloating-point data types. You can use these models to assess the results of the DSPBuilder advanced blockset design. This step is optional.

2. Set up Simulink.

3. Create scripts for generating and analyzing your DSP Builder advanced blocksetdesign. This step includes the basic setup of any DSP Builder advanced blocksetdesign, such as stimulus and output data gathering for analysis.

4. Analyze the parts of a design you might wish to keep flexible, and place theseparts and derived parameters in a configuration script so that you can changethese parameters. The configuration script is typically a MATLAB script with thescript base addresses for registers and memory from your design.

5. Implement your design in DSP Builder advanced blockset.

6. Verify the functionality of the design in Simulink and MATLAB. This earlyverification process focuses on the functionality of your algorithm. Iterate thedesign implementation and setup scripting, if needed.

7. Explore design tradeoffs. You can get early estimates of resource utilization beforeyou go to hardware verification, which allows you to experiment with variousimplementation optimizations early. You can access memory-logic tradeoff, orlogic-multiplier tradeoff by modifying threshold parameters. You may not need tophysically modify the design. DSP Builder can automate design space exploration

based on your tradeoff options.

8. Verify the design in MATLAB and in ModelSim with the automatic testbench flow.This step is the final verification before you port the design to system-levelintegration. If you sufficiently verify your design early in the design flow, thereshould be no need to iterate your design.

9. Verify the design in hardware. To verify the design in hardware use the hardwarein the loop (HIL) design from the standard blockset.

f For more information, refer to the Using HIL chapter in the DSP BuilderStandard Blockset User Guide section in volume 2 of the DSP Builder

Handbook.

10. Integrate your DSP Builder advanced blockset design as a black-box design inyour top-level design. This integration can involve SOPC Builder integration witha processor, and eventually Quartus II integration.

DSP Builder advanced blockset allows scripting, which combines the importing andexporting data functions of Simulink. You can create batch testing using MATLAB .m

scripts that execute design simulation and test results. With DSP Builder advancedblockset you can automate sequential tests and explore design space options, all in atext script.

Follow theses guidelines for the top-level design:

1. Use workspace variables to set parameters you may want to vary. For example,clock rates, sample rates, bit widths, channels.
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Setting Up Simulink


Preliminary

2. Set workspace variables in initialization scripts. Execute them on the model'sPreLoadFnc and InitFcn callbacks, such that the design opens with parametersset, and the next simulation reflects any changes in the next simulation, withoutexplicitly running the script or opening and closing the model.

3. Call your main initialization script for the model setup_, and as ashortcut to editing it include the Edit Params block in the top level design.

4. Build a testbench that is parameterizable with the Channelizer block, whichvaries correctly with system parameters such as sample rate, clock rate, andnumber of channels.

5. Use the model's StopFnc call back to run any analysis scripts automatically.

6. Build systems that use the valid and channel signals for control andsynchronization, not latency matching. For example, capture valid output in FIFO

buffers to manage dataflow.

7. Build up and use your own libraries of reusable components.

8. Keep block and subsystem names short, but descriptive. Avoid names with specialcharacters, slashes, or that begin with numbers.

9. Use LocalThreshold blocks, with the top-level thresholds, for localizedtradeoffs or pipelining.

Setting Up SimulinkTo set up a DSP Builder advanced blockset design in Simulink, configure thefollowing preferences in Simulink:

Use fixed-step solver type unless you have folding turned on in some part of yourdesign. In that case, you need to use variable-step solver.

Set the solver to be discrete (no continuous states).

Turn on sample time colors, port types, and so on.

Creating ScriptsDSP Builder advanced blockset supports scripting and parameterization of yourdesign. By defining most of the parameters such as clock frequency, data sample rate,number of channels and bit width at various stages of your design in a script, youcreate a design that can be easily reparameterized without even opening the Simulinkmodel. One such useful script is the setup script, which is usually an MATLAB .m file.The setup script may have clock rate, bit width, and other important information thatmust be evaluated before you update your design in Simulink or start a simulation.

To evaluate the setup script, use the callbacks functionality of Simulink. To configurecallbacks, follow these steps:

1. In a Simulink model file .mdl, browse on the File menu click Model properties.

2. Select Callbacks tab.

3. Select PreLoadFcn and type the setup script name in the window on the righthand side. When you open your Simulink design file, the setup script runs.


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4. Select InitFcn and type the setup script name in the window on the right handside. Simulink run your setup script first at the start of each simulation before itevaluates the model design file .mdl.

Callbacks make your design more robust, and ensures all parameters are evaluatedbefore hardware is generated.

When designing with DSP Builder advanced blockset use the following visualizationfeatures of MATLAB and Simulink:

OutScope block. In addition to exporting data to work space for analysis, you canuse the OutScope block to visualize a signal or multiple signals. The OutScope

block probes and displays data on a wire or a bus relative to the time samples,which is useful when debugging your design.

OutputSpectrum block. You can also use the OutputSpectrum block, whichdisplays the signal spectrum in real time, when your design has filtering or FFT.

Fixed-point toolbox. When dealing with bit growth and quantization, thefixed-point toolbox can be a valuable tool. You can even visualize the dynamicrange of a signal by looking at the histogram of the signal.

Writing Custom ScriptsYou can write scripts that directly change parameters (such as the hardwaredestination directory) on the Control and Signals blocks.

For example, in a script that passes the design name (without .mdl extension) as modelyou can use:

%% Load the model

load_system(model);

%% Get the Signals block

signals = find_system(model, 'type', 'block', 'MaskType', 'DSPBuilder Advanced Blockset Signals Block');

if (isempty(signals))

error('The design must contain a Signals Block. ');

end;

%% Get the Controls block

control = find_system(model, 'type', 'block', 'MaskType', 'DSP

Builder Advanced Blockset Control Block');

if (isempty(control))

error('The design must contain a Control Block. ');

end;

%% Example: set the RTL destination directory

dest_dir = ['../rtl' num2str(freq)];

set_param(control{1},'destination',dest_dir);

Similarly you can get and set other parameters. For example, on the Signals blockyou can set the target clock frequency:

fmax_freq = 300.0;


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set_param(signals{1},'freq', fmax_freq);

You can also change the following threshold values that are parameters on theControl block:

distRamThresholdBits

hardMultiplierThresholdLuts

mlabThresholdBits

ramThresholdBits

You can loop over changing these values, change the destination directory, run theQuartus II software each time, and perform design space exploration. For example:

%% Run a simulation; which also does the RTL generation.

t = sim(model);

%% Then run the Quartus II compilation flow.

[success, details] = run_hw_compilation(, './')

%% where details is a struct containing resource and timing

information

details.Logic,

details.Comb_Aluts,

details.Mem_Aluts,

details.Regs,

details.ALM,

details.DSP_18bit,

details.Mem_Bits,

details.M9K,

details.M144K,

details.IO,

details.FMax,

details.Slack,

details.Required,

details.FMax_unres,

details.timingpath,

details.dir,

details.command,

details.pwd

such that >> disp(details) gives output something like:

Logic: 4915

Comb_Aluts: 3213

Mem_Aluts: 377

Regs: 4725

ALM: 2952

DSP_18bit: 68


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Mem_Bits: 719278

M9K: 97

M144K: 0

IO: 116

FMax: 220.1700

Slack: 0.4581

Required: 200

FMax_unres: 220.1700

timingpath: [1x4146 char]

dir: '../quartus_demo_ifft_4096_natural_for_SPR_FFT_4K_n_2'

command: [1x266 char]

pwd: 'D:\test\script'

1 The Timing Report is in the timingpath variable, which you can display bydisp(details.timingpath). Unused resources may appear as -1,rather than 0.

You must previously execute load_system before commands such asfind_system and run_hw_compilation work.

A useful set of commands to generate RTL, compile in the Quartus II software andreturn the details is:

load_system();

sim();

[success, details] = run_hw_compilation(, './')

Implementing your DesignImplementing your design involves the following steps:

Staging your Design into Subsystems

Including Base Library Blocks

Choosing the ModelIP Library or the ModelPrim Library

Using ModelPrim Blocks

Connecting Blocks

Using Latency Constraints

Using Folding

Use Multichannel Operation

Using Vectorized Inputs

Connecting Modules

Avoiding Minimum Latency in a Feedback Loop

Managing your Designs


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Staging your Design into Subsystems

Before you start implementing your algorithm, you should consider how to stageyour design into subsystems. A hierarchical approach makes a design easier tomanage, more portable thus easier to update, and easier to debug. If it is a largedesign, it also makes design partition more manageable.

DSP Builder advanced blockset achieves timing closure based on your timingconstraints, namely sample rate and clock rate. A modular design with well-definedsubsystem boundaries, allows you to precisely manage latency and speed of differentmodules thus achieving time closure effortlessly.

Consider the following factors when staging your design into subsystems:

Identify the functionality of each submodule of your algorithm, and if you canpartition your design into different functional subsystems.

In multi-rate designs consider the sample rate variation at different stages of adatapath. Try not to involve too many different sample rates within a subsystem.For example, a synchronization block when merging datapaths of different samplerates.

If your design has very tight latency requirement, use latency management todefine the boundary of a subsystem, because DSP Builder advanced blocksetapplies latency constraints on a subsystem basis.

Synchronization is simplified if modules which can be computed in parallel areimplemented in the same subsystem. DSP Builder can apply the same rules moreeasily to each of the parallel paths. You need not worry about constraining the twopaths that may otherwise have different latencies.

Including Base Library Blocks

The DSP Builder advanced blockset base library has the most basic blocks of any DSP

Builder advanced blockset designs. Every DSP Builder advanced blockset designmust have Control block and Signal blocks, otherwise your design does notsimulate or compile. The Run Quartus II block and Run ModelSim block providean automated way of initiating compilation and simulation outside of Simulink.

For more information on the Control and Signal blocks, refer to the Base Librarychapter in the DSP Builder Advanced Blockset Libraries section in volume 3 of the DSPBuilder Handbook.

Choosing the ModelIP Library or the ModelPrim Library

DSP Builder advanced blockset offers the following two libraries to implement youralgorithms:

An IP (ModelIP) library that has the most commonly used functions such as FIRfilters and NCOs, ready to be plugged in to your design using drag-and-drop.

The primitive (ModelPrim) library that has all the blocks you need to buildcustomized logic, such as multipliers, memories, and simple control blocks.
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DSP Builder generates the ModelIP blocks at runtime while running simulations inSimulink. The ModelIP blocks do not have a predetermined architecture. Based on thesystem clock frequency, you can further optimize the blocks by time sharing theinternal resources. All the ModelIP blocks accept system parameters. For example forthe interpolating FIR, you can specify system variables as parameters such as inputrate per channel, rate change factor, and number of channels. It also accepts MATLAB

functions to generate coefficients. You can specify the base address for thememory-mapped interface to reload coefficient.

The ModelPrim library contains basic operators such as add, multiply, and delay, aswell as signal type manipulation functions to provide support for building hardwarefunctions using the MATLAB fixed-point types. You do not need to understand thedetails of the underlying FPGA architecture, as the ModelPrim blocks areautomatically mapped into efficient FPGA constructs.

Using ModelPrim Blocks

Most arithmetic and memory ModelPrim blocks allow you to use Simulink 1-D vector(array) and complex types. A design that uses a vector input of width Nis the same as

connecting Ncopies of the block with a single scalar connection to each.

Signals that pass through a single ChannelIn, ChannelOut, GPIn, or GPOut blockline up correctly in time at their boundaries. However, DSP Builder does not specifythe timing relationship between different sets of inputs and outputs, and does notguarantee any fixed relationship if you change clock frequencies or devices.

You should use the protocol described in Folding on page 81 to decode outputs,rather than exact clock counting where possible.

You can design and debug quickly with zero-latency blocks, without tracking blocklatencies around your design. DSP Builder displays and calculates the additionallatency that your design requires to meet timing constraints as a parameter on theChannelOut block.

The ChannelIn and ChannelOut blocks delineate the boundary of a synthesizableModelPrim subsystem. They pass inputs through to the outputs unchanged, withtypes preserved. These blocks indicate to the tools that these signals arrivesynchronized from their source, and depart from this subsystem synchronized.

Parameters on the ChannelIn and ChannelOut blocks allow the control ofautomated folding for the ModelPrim subsystems. Folding allows DSP Builder toimplement the design with fewer expensive resources, such as multipliers, at theexpense of a little more logic by sharing them when the sample rate is below the clockrate.

f For more information on folding, refer to Folding on page 81.

ChannelIn and ChannelOut blocks must be in their own subsystem and directlyconnected to the subsystem in and out ports. Within the channel in and out pair, youcan use nested subsystems, but without the channel in and out pairs. You cannot nestChannelIn or ChannelOut blocks.

Before using ModelPrim blocks, follow these guidelines:

1. Ensure the ModelPrim subsystem contain a SynthesisInfo block with style setto Scheduled.


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2. Ensure the ModelPrim subsystems do not contain ModelIP blocks.

3. Route all subsystem inputs with associatedvalid and channel signals that areto be scheduled together through the same ChannelIn blocks immediatelyfollowing the subsystem inputs. Route any other subsystem inputs through GPIn

blocks.

4. Route all subsystem outputs with associatedvalid and channel signals that areto be scheduled together through the same ChannelOut blocks immediately

before the subsystem outputs. Route any other subsystem outputs through GPOutblocks.

5. Use Convert blocks to change data type preserving real-world value.

6. Use Specify via dialog options to change data type to preserve bit pattern, or to fixa data type.

7. Ensure the valid signal is a scalar Boolean signal or ufix(1).

8. Ensure the channel signal is a scalar uint(8).

ModelPrim Subsystem Recommendations

Follow theses guidelines for ModelPrim subsystems:

1. Use vectors to build parameterizable designsthey do not need redrawing whenparameters such as number of channels changes.

2. Ensure there are sufficient sample delays around loops to allow for pipelining(Vector Initialization of Sample Delay on page 337).

3. Simulink performs data type, complexity, and vector width propagation.Sometimes Simulink does not successfully resolve propagation around loops,particularly multiple nested loops. If Simulink is unsuccessful, look for where datatypes are not annotated. You may have to explicitly set data types. Simulinkprovides a library of functions to help in such situations, which duplicate data

types. For example, the data type prop duplicate block, fixpt_dtprop, (typeopen fixpt_dtprop from the MATLAB command prompt, which the controllibrary latches use.

Specifying the Output Data Type

Many of the ModelPrim blocks provide the following options in their BlockParameters dialog box to inherit or specify the output data type:

Inherit via internal rule: the number of integer and fractional bits is equal to themaximum of the number of bits in the input data types. Word growth occurs if theinput data types are not identical.

Inherit via internal rule with word growth: the number of fractional bits is equal

to the maximum of the number of fractional bits in the input data types. Thenumber of integer bits is the maximum of the number of integer bits in the inputdata types plus one. This additional word growth allows for subtracting the mostnegative number from 0, which exceeds the maximum positive number that DSPBuilder can store in the number of bits of the input.

Specify via dialog: additional fields that allow you to set the output type of theblock explicitly.

Boolean: the output type is Boolean.


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In general, you can set the output type of a ModelPrim block to Inherit via internalrule, or Inherit via internal rule with word growth. The type propagates throughyour design naturally, with blocks potentially growing the word length wherenecessary. If there are loops in your design, use the dialog box to specify the outputtype for at least one block in the loop.

f For information about the options that DSP Builder supports by each block, refer totheModelPrim Library chapter in the DSP Builder Advanced Blockset Libraries section involume 3 of the DSP Builder Handbook.

Using the Specify via Dialog Option

Specifying the output type with the dialog box is a casting operation. This operationdoes not preserve the numerical value, just the underlying bits and never addshardware to a blockjust changes the interpretation of the output bits.

For example, a Mult block with both input data types specified as sfix16_En15naturally has an output type ofsfix32_En30. If you specify the output data type assfix32_En28, the output numerical value is effectively multiplied by four, and a 1*1input gives an output value of 4.

If you specify output data type ofsfix32_En31, the output numerical value iseffectively divided by two and a 1*1 input gives an output value of 0.5.

If you want to change the data type format in a way that preserves the numericalvalue, use a Convert block, which adds the corresponding hardware. Adding aConvert block directly after a ModelPrim block allows you to specify the data typein a way that preserves the numerical value. For example, a Mult block followed by aConvert block, with input values 1*1 always gives output value 1.

SynthesisInfo Block

The ModelPrim library includes a SynthesisInfo block that sets the synthesis

mode and labels a subsystem described by ModelPrim blocks as the top-level of asynthesizable subsystem tree. DSP Builder flattens and synthesizes the subsystem,and all those below as a unit. If no SynthesisInfo block is present, the styledefaults to WYSIWYG and DSP Builder issues error messages if there is insufficientdelay.

The inputs and outputs to this subsystem become the primary inputs and outputs ofthe RTL entity that creates. After you run a Simulink simulation, the online Help pagefor the SynthesisInfo block updates to show the latency, port interface, andestimated resource utilization for the current ModelPrim subsystem.

1 The SynthesisInfo block can be at the same level as the Device block (if thesynthesizable subsystem is the same as the generated hardware subsystem).

However, it is often convenient to create a separate subsystem level that contains theDevice block. Refer to the design examples for some examples of design hierarchy.

Two styles of operation exist during synthesis: WYSIWYG and Scheduled.
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WYSIWYG Style

WYSIWYG is the default style of operation. Use when you want full control over thepipelining in a system. A Delay ModelPrim block must follow every ModelPrim

block that requires registering (such as an adder or multiplier). The preceding blockabsorbs the delay ModelPrim block to satisfy its delay requirements. DSP Builderissues error messages if there is insufficient delay.

1 The ModelPrim logic blocks (And, Or, Nand, Not, Nor, Xnor, Xor) and the SimulinkMux and Demux blocks do not require a register.

The algorithm performs the following operations:

1. Reads in and flattens your design example for any subsystem that contains aSynthesisInfo block.

2. Builds an internal graph to represent the logic.

3. Based on the absolute clock frequency requested, adds enough pipeline stages tomeet that clock frequency. For example, long adders may be pipelined into severalshorter adders. This additional pipelining helps reach high clock frequencies.

Scheduled Style

The Scheduled style of operation uses a pipelining and delay distribution algorithmthat creates fast hardware implementations from an easily described untimed blockdiagram. Thisstyle takes full advantage of the automatic pipelining capability.

1 Altera recommends the Scheduled style of operation.

The algorithm performs the following operations:

1. Reads in and flattens your design example for any subsystem that contains aSynthesisInfo block.

2. Builds an internal graph to represent the logic.

3. Based on the absolute clock frequency requested, adds enough pipeline stages tomeet that clock frequency. For example, you may pipeline long adders into severalshorter adders. This additional pipelining helps reach high clock frequencies.

Consider the following two main cases:

The simpler case is feed-forward. When no loops exist, feed-forward datapaths arebalanced to ensure that all the input data reaches each functional unit in the samecycle. After analysis, DSP Builder inserts delays on all the non-critical paths to

balance out the delays on the critical path.


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The case with loops is more complex. DSP Builder creates all loops with a delay toavoid combinational loops that Simulink cannot analyze. Typically, one or morelumped delays exist. Preserve the delay around the loop for correct operation,therefore the functional units borrow delays from the lumped delay that needthem.

Because loops can intersect or be nested with each other, observe a set of

simultaneous constraints. The synthesis engine solves these constraints,distributes delay around the functional units as required, and leaves any residualdelay as lumped delay elements. When there is insufficient delay to distribute, anerror generates. The following list gives the delay requirements for some typical

blocks:

Boolean logic operations: 0 delay

Adders: 1 delay, but potentially more at higher clock rates

Two input multiplexers: 1 delay with potentially more for large number ofinputs and at high clock rates

Multipliers: 3 cycles or 4 at higher clock rates

When you select the Scheduled style, you can optionally specify a latency constraintlimit that can be a workspace variable or expression but must evaluate to a positiveinteger.

Using Vectors

Using vectors with ModelPrim blocks has the following advantages:

Makes the design more parameterizable

Speeds up simulation

Simplifies the schematic

Avoids cut-and-paste duplication in many instances Enables flexible designs that scale with input vector width

This section describes using vectors for building more parameterizable designcomponents.

The following three design examples demonstrate using vectors:

Matrix Initialization of Vector Memories

Matrix Initialization of LUT

Vector Initialization of Sample Delay

Vector Utils Library

Often to go to and from single connections to vectors using parameters either byreplicating or selectingstops you building a a vector parameterizable librarycomponent. For example, replicating a single signal x times to form a vector. If youhave to draw and connect this connection when the desired vector changes, you losethe ability to parameterize. You can use Simulink commands in the initialization ofmasked subsystems to parameterize and reconnect automatically.


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The following blocks in the Vector Utils library all use standard Simulink commandsfor finding blocks, deleting blocks, and lines, also adding blocks, lines, andpositioning blocks.

Expand Scalar (ExpandScalar)

Vector Multiplexer (VectorMux)

Tapped Delay Line (TappedDelayLine)

You can use these techniques to build parameterizable utility functions.

Other Vector BlocksSimulink Selector

The Simulink Selector block enables you to select some signals out of a vector ofsignals, including operations such as reordering. DSP Builder only supports Startingindex (dialog) index option, which is equivalent to a static selection. DSP Builder doesnot support Starting index (port). Set the index and input port size with work spacevariables.

The Simu

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