SH-Linux ボード · PDF fileSH-Linuxボード. SH-2009ユーザーズガイド. Rev.1.0.1 2009/6 . 株式会社アイ･ティー･オー

SH-Linuxボード

SH-2009ユーザーズガイド

Rev.1.0.1 2009/6

株式会社アイ･ティー･オー

a

内容１はじめに ............................................................................................................ 1２ハードウェア ..................................................................................................... 1

２-１ハードウェア仕様 ...................................................................................... 2２-２システムブロック図 .................................................................................. 4２-３ CPUボード配置図 ..................................................................................... 5２-４ IOボード配置図 ......................................................................................... 6２-５接続コネクタ ............................................................................................. 7２-５-１ CN1 .................................................................................................. 7２-５-２ CN2 .................................................................................................. 7２-５-３ CN3 .................................................................................................. 8２-５-４ CN4・CN5 ....................................................................................... 9２-５-５ CN6 ................................................................................................ 11２-５-６ CN7 ................................................................................................ 13２-５-７ CN8 ................................................................................................ 13２-５-８ CN9 ................................................................................................ 14２-５-９ CN10・CN11 .................................................................................. 14２-５-１０ CN12 ........................................................................................... 15２-５-１１ CN13 ........................................................................................... 15２-５-１２ CN14 ........................................................................................... 15２-５-１３ CN15 ........................................................................................... 16２-５-１４ CN16 ........................................................................................... 16２-５-１５ CN17 ........................................................................................... 16２-５-１６ CN18 ........................................................................................... 17２-５-１７ CN19 ........................................................................................... 17２-５-１８ CN20 ........................................................................................... 18２-５-１９ CN21 ........................................................................................... 19２-５-２０ SH2009IO-CN1 .......................................................................... 20２-５-２１ SH2009IO-CN2 .......................................................................... 20２-５-２２ SH2009IO-CN3 .......................................................................... 21２-５-２３ SH2009IO-CN4(ttyS0)～CN11(ttyS7) ....................................... 21２-５-２４ SH2009IO-CN12 ......................................................................... 22

２-６ディップスイッチ .................................................................................... 23２-６-１ SW2-1 FPGAプログラムデータの選択 ......................................... 23２-６-２ SW2-4,5,6 ブートデバイス選択 .................................................... 24

２-７メモリ・IOマップ・割り込み ................................................................. 24

b

２-７-１物理アドレスマップ ........................................................................ 24CPU内部要因以外の割り込み ........................................................................ 25

２-８ CPUボード回路図 ................................................................................... 27１-１-１トップページ ................................................................................... 27１-１-２ CPU-A ............................................................................................ 28１-１-３ CFスロット ..................................................................................... 29１-１-４ DDR2 メモリ .................................................................................. 30１-１-５ PC104BUS ..................................................................................... 31１-１-６ FPGA/CPLD ................................................................................... 32１-１-７ Gbit LAN ........................................................................................ 33１-１-８ LAN ................................................................................................ 34１-１-９ NAND Flash ROM ......................................................................... 35１-１-１０電源 ............................................................................................. 36１-１-１１ RS232C ....................................................................................... 37１-１-１２ RTC ............................................................................................. 37１-１-１３タッチパネル ............................................................................... 37１-１-１４ USB ............................................................................................. 38１-１-１５ VGA ............................................................................................ 39

２-９ IOボード回路図 ....................................................................................... 40１-１-１６トップ .......................................................................................... 40１-１-１７ ADC ............................................................................................ 41１-１-１８ IDE .............................................................................................. 41１-１-１９ RS232C ....................................................................................... 42１-１-２０ RS485 .......................................................................................... 43

２-１０ CPLDソース ........................................................................................ 44２-１０-１ VHDL .......................................................................................... 44２-１０-２ UCF ............................................................................................ 48

２-１１ FPGAソースファイル .......................................................................... 49２-１１-１トップsh2009.vhd ....................................................................... 49２-１１-２ sh2009_sys.vhd ........................................................................... 64２-１１-３ conpact_flash.vhd ....................................................................... 72２-１１-４ uart.vhd ...................................................................................... 76２-１１-５ intr_cont.vhd .............................................................................. 95２-１１-６ adc.vhd ........................................................................................ 99２-１１-７ i2c.vhd ....................................................................................... 104２-１１-８ sh2009.ucf ................................................................................. 105

c

３ SH2009 の起動 .............................................................................................. 120３-１-１ファーストライト .......................................................................... 120３-１-２ネットワーク・ユーザ名の出荷時設定 .......................................... 120３-１-３起動メッセージ ............................................................................. 121３-１-４出荷時にインストールされているパッケージ ............................... 127３-１-５起動しているデーモン .................................................................. 130３-１-６コンパイル .................................................................................... 131

３-２ MTDデバイス ....................................................................................... 132３-２-１ NOR Flash ROM .......................................................................... 132３-２-２ NOR Flash ROM書き換えの手順 ................................................. 132３-２-３ NAND Falsh ROM ....................................................................... 132３-２-４ UBIFS初期化方法 ......................................................................... 133

３-３ YUM (Yellow dog Updater, Modified) ................................................. 133パッケージのupdate .................................................................................... 133３-３-１アップデートパッケージのチェック ............................................. 134３-３-２パッケージのアップデート ........................................................... 134３-３-３パッケージのインストール ........................................................... 136

４ソフトウェア ................................................................................................. 139４-１クロスコンパイル環境 ........................................................................... 139４-２ FedoraCoreマシンにパッケージをインストール .................................. 139４-３ IPL ........................................................................................................ 139４-４ kernel .................................................................................................... 140４-４-１本ボードへ新しいkernelモジュールをコピーする ........................ 140４-４-２ IOを制御するデバイスドライバを作成される方へ ........................ 141４-４-３ ttyS0～ttyS5 RS232C/RS485 選択 ............................................... 141４-４-４ ADコンバータ ............................................................................... 141

５エラータ ........................................................................................................ 143５-１ソフトウェアアップデート .................................................................... 144

６著作権表示 ..................................................................................................... 145

1

１はじめに

本書は、ルネサス社 SUPER-H マイクロプロセッサ R8A77850BA(SH7785)

コアスピード 600MHz(1080MIPS)を採用した１ボードコンピュータ SH-2009

について説明するものです。

特長

SH7785 は、Linux などのオペレーティングシステムを動作させる上で SUPER-H マ

イクロプロセッサの弱点であった主記憶の最大容量が大きくなりました。SH-2009（以

下、本ボード）では 512MB の DDR2 メモリを搭載しています。これにより Xwindowを無理無く動作できるようになりました。その他、本ボードには、VGA インターフェース（DVI-I、LVDS、DVO サポート）、

G ビット LAN、USB2.0、タッチパネルインターフェース（GUNZE４線／８線式）、

多チャンネルシリアルインターフェースなどを搭載しています。本ボードには、40 万ゲート相当の FPGA（xilinx 社 XC3S400A）を搭載しており、

一部の固定された部分（回路）を除き、ユーザーが FPGA 内に別の回路を組み込むこ

とを可能にしています。本書について

本書は、SH7785 をはじめ、使用しているデバイスの仕様を熟知されているものとし

て記述していますので、あらかじめ本ボードで使用しているデバイスのデータシート/ユーザーズガイドを準備されることをお勧めします。本ボードが採用している Linux は、x86 ベースの Linux と本質的に同じものです。

本書は、x86 ベースの Linux について熟知されていることを前提に記述しています。免責事項

本書および配布しているソフトウェアのご利用の結果については、いかなる動作も保

証しない完全無保証です。また、配布しているソフトウェアは GNU GPL など、それ

ぞれのパッケージで採用されたライセンス条項に基づきソースコードを公開していま

す。

２ハードウェア

本章は、本ボードのハードウェアについての説明です。

2

２-１ハードウェア仕様

基板サイズ・仕様 CPU ボード約 134×131mm 8層 IVH基板材質FR-4 IO ボード約 134×131mm 4 層基板材質 FR-4 電源電圧・消費電流 DC5V 約 1.3A

(CPU ボード＋IO ボード。SH-Linux、idle 状態) 消費電力は動作状況により増加します。 2.5”ハードディスクや、USB コネクタにデバイスを装着す

る場合は、そのデバイスの消費電力を加味した電源をお使

いください。＊拡張バスに±12V,-5V を供給する場合はそれらの電源が

必要です。＊時計用バックアップには、スーパーキャパシタを搭載。

長時間バックアップが必要な場合は、外部にバックアップ

電池を設けてください。 CPU R8A77850A (SH4A)。リトルエンディアンで使用動作速度 CPU 内部 600MHz DDR2 メモリクロック 300MHz

CKIO 100MHz （原発振 33.333MHz）主記憶 512MB(1Gb DDR2 SDRAM×4 個) オンボード ROM 32MB（NOR 型 Flash ROM）sh-ipl および kernel

8Gb×2 個（SLI NAND 型 Flash ROM）root filesystem LAN 1Gb/100Base-Tx/10Base-T×1CH （Intel 82541）eth0

100Base-Tx/10Base-T×1CH （SMSC LAN9218）eth1 VGA XGI 社 Z9s+32MB DDR2SDRAM DVI，LVDS，DVO，

アナログ RGB(DVI-I 端子)をサポート USB2.0 μPD720101 TypeA コネクタ 4 ポート実装周辺ロジック使用 FPGA XC3S400A-4FGG320

出荷時は、活電挿抜 CF インターフェース、シリアルイン

ターフェース×8CH、その他にプログラム済みです。一部の固定部分を除きユーザーが任意の回路に変更可能で

す。 CF カードスロット活電挿抜対応 CF ソケット×１（3.3V 駆動）

コンパクトフラッシュメモリカード専用です。 IDE－I/F 2.5”パラレル HDD×1 ポート (マスター・スレーブで 2

台接続可能です。) 動作モード PIO IO ボードに搭載。タッチパネル-I/F GUNZE AHL-71N シリアル-I/F SCIF0（ttySC1 に割り当て）起動コンソールとして使用

3

RS232C SCIF1（ttySC0 に割り当て) ttyS0～ttyS7（IO ボードに搭載。ttyS0～ttyS5 は RS485と排他的使用）

シリアル-I/F RS485

ttyS0～ttyS5（IO ボードに搭載 RS232C と排他的使用）

AD コンバータ 12 ビット 8CH IO ボードに搭載。外部バス PC-104 サブセット動作環境温度範囲０～４０℃

湿度範囲２０％～８０％（結露不可）シリアルインターフェース ttyS0 から ttyS7 は、FPGA 内に 16550 相当の UART を組

み込んでいます。

4

２-２システムブロック図

5

２-３CPUボード配置図

6

２-４IOボード配置図

7

２-５接続コネクタ

２-５-１CN1

機能メーカ名品番外部 LED 接続日圧 B8B-ZR-SM4-TF(LF)(SN)

ピン番号信号名 1 CPU の GPIO PN6 に接続されています。 2 eth1 led1 3 eth1 led2 4 eth0 led0 5 eth0 led1 6 eth0 led2 7 eth0 led3 8 +3.3V

２-５-２CN2

機能メーカ名品番 CPU JTAG 日圧 B10B-ZR-SM4-TF(LF)(SN)

ピン番号信号名 1 TCK 2 nTRST 3 MPMD 4 TDO 5 GND 6 nASEBRK/BRKACK 7 +3.3V 8 TMS 9 TDI 10 このボードの nRESET 出力

8

２-５-３CN3

機能メーカ名品番 CF スロット航空電子 JC26A-BB16E

ピン番号信号名信号名ピン番号 1 GND nCD1 26 2 CD3 CD11 27 3 CD4 CD12 28 4 CD5 CD13 29 5 CD6 CD14 30 6 CD7 CD15 31 7 nCE1 nCE2 32 8 CA10 NC 33 9 nMRD nIORD 34 10 CA9 nIOWR 35 11 CA8 nMWR 36 12 CA7 nIRQ 37 13 Switchd +3.3V Switchd +3.3V 38 14 CA6 GND 39 15 CA5 NC 40 16 CA4 RESET 41 17 CA3 nWAIT 42 18 CA2 nDMARQ 43 19 CA1 nREG 44 20 CA0 Pullup 45 21 CD0 nSTSCHG 46 22 CD1 CD8 47 23 CD2 CD9 48 24 nIOIS16 CD10 49 25 nCD2 GND 50

9

２-５-４CN4・CN5

外部バス PC-104 サブセット

CN4 No 信号信号 No A1 Pull Hi GND B1 A2 XD7 RESET B2 A3 XD 6 VCC(+5V) B3 A4 XD 5 SIRQ9 B4 A5 XD 4 -5V(CN10-pin4 へ接続) B5 A6 XD 3 NC B6 A7 XD 2 -12V(CN10-pin5 へ接続) B7 A8 XD 1 nNOWAIT B8 A9 XD 0 +12V(CN10-pin6 へ接続) B9 A10 IOCHRDY GND B10 A11 AEN nSMEMW nMEMW と同じ B11 A12 XA19 nSMEMR nMEMR と同じ。 B12 A13 XA18 nIOWR B13 A14 XA17 nIORD B14 A15 XA16 Pull Hi B15 A16 XA15 NC B16 A17 XA14 nDACK1 B17 A18 XA13 DRQ1 B18 A19 XA12 Pull Hi B19 A20 XA11 SYSCLK(8.33MHz) B20 A21 XA10 SIRQ7 B21 A22 XA9 SIRQ6 B22 A23 XA8 SIRQ5 B23 A24 XA7 SIRQ4 B24 A25 XA6 SIRQ3 B25 A26 XA5 Pull Hi B26 A27 XA4 Pull Down B27 A28 XA3 BALE B28 A29 XA2 VCC(+5V) B29 A30 XA1 OSC(12.5MHz) B30

10

A31 XA0 GND B31 A32 GND GND B32 CN5 No 信号信号 No C0 GND GND D0 C1 nBHE Pull Hi D1 C2 XA23 nIOIS16 D2 C3 XA22 SIRQ10 D3 C4 XA21 SIRQ11 D4 C5 XA20 SIRQ12 D5 C6 XA19 SIRQ15 D6 C7 XA18 SIRQ14 D7 C8 XA17 nDACK0 D8 C9 nMEMR DRQ0 D9 C10 nMEMW Pull Hi D10 C11 XD8 NC D11 C12 XD9 Pull Hi D12 C13 XD10 NC D13 C14 XD11 Pull Hi D14 C15 XD12 NC D15 C16 XD13 VCC(+5V) D16 C17 XD14 Pull Hi D17 C18 XD15 GND D18 C19 GND GND D19

注意：バスタイミングは PC104 の規格と異なります。 XA[23:0]は出力です。外部バスにバスマスタは接続できません。

11

２-５-５CN6

機能メーカ名品番 IO ボード接続用ヒロセ FX8C-140S-SV5(91)

Default 信号名は、SH2009-IO ボードでの信号です。独自 IO ボードを作成し、SH2009 に

搭載された FPGA を独自 IO ボードで使用可能です。 A 列 Default 信号名 FPGA ピン FPGA ピン Default 信号名 B 列 1 TxD0 D12 C12 TxD1 1 2 TxD2 F4 J6 TxD3 2 3 TxD4 K16 T2 TxD5 3 4 TxD6 N12 E1 TxD7 4 5 GND --- --- GND 5 6 Tx485ENB0 B12 F15 Tx485ENB1 6 7 Tx485ENB2 E16 T14 Tx485ENB3 7 8 Tx485ENB4 P18 T12 Tx485ENB5 8 9 Tx485ENB6 V8 F18 Tx485ENB7 9 10 RxD485_0 G13 K15 RxD485_1 10 11 RxD485_2 G16 P9 RxD485_3 11 12 RxD485_4 M16 P15 RxD485_5 12 13 RxD485_6 N7 L18 RxD485_7 13 14 GND --- --- GND 14 15 RxD232_0 E15 K17 RxD232_1 15 16 RxD232_2 K12 P7 RxD232_3 16 17 RxD232_4 M17 N14 RxD232_5 17 18 RxD232_6 P14 R6 RxD232_7 18 19 nCTS0 G15 J13 nCTS1 19 20 nCTS2 H16 L14 nCTS3 20 21 nCTS4 K14 P5 nCTS5 21 22 nCTS6 M12 H17 nCTS7 22 23 GND --- --- GND 23 24 nRTS0 B2 L12 nRTS1 24 25 nRTS2 G17 V3 nRTS3 25 26 nRTS4 N17 U11 nRTS5 26 27 nRTS6 U12 R18 nRTS7 27

12

28 nDCD0 M4 G14 nDCD1 28 29 nDCD2 U8 U9 nDCD3 29 30 nDCD4 K13 H2 nDCD5 30 31 nDCD6 M8 V9 nDCD7 31 32 GND --- --- GND 32 33 nDSR0 H12 H13 nDSR1 33 34 nDSR2 J16 P6 nDSR3 34 35 nDSR4 K18 P4 nDSR5 35 36 nDSR6 M11 H18 nDSR7 36 37 nRI0 G9 F16 nRI1 37 38 nRI2 D1 G4 nRI3 38 39 nRI4 L17 G3 nRI5 39 40 nRI6 N9 F3 nRI7 40 41 GND --- C1 RD_nWR 41 42 ADC_SDO F7 A4 ADC_SCK 42 43 ADC_SDI C6 G8 nADC_BUSY 43 44 AD_START C15 B4 nAD_RD 44 45 GND --- E7 nIORD 45 46 DD0 --- --- DD1 46 47 DD2 --- --- DD3 47 48 DD4 --- --- DD5 48 49 DD6 --- --- DD7 49 50 DD8 --- --- DD9 50 51 DD10 --- --- DD11 51 52 DD12 --- --- DD13 52 53 DD14 --- --- DD15 53 54 GND --- A3 nIOWR 54 55 nIDE_IOW --- --- nIDE_IOR 55 56 DA0 --- --- DA1 56 57 DA2 --- --- nIDE_DEN 57 58 nIDE_CS0 --- --- nIDE_CS1 58 59 IDE_IOCHRDY --- --- CPU RD_nWR 59 60 nRESET --- --- nIRL0 60 61 GND --- --- DA15 61 62 --- A2 B3 GPIO1 62

13

63 GPIO2 B17 D2 --- 63 64 +3.3V --- --- +3.3V 64 65 +3.3V --- --- +3.3V 65 66 +5V --- --- +5V 66 67 +5V --- --- +5V 67 68 GND --- --- GND 68 69 GND --- --- GND 69 70 GND --- --- GND 70

２-５-６CN7

機能メーカ名品番 FPGA･CPLD JTAG 日圧 B7B-ZR-SM4-TF(LF)(SN)

ピン番号信号名 1 +3.3V 2 GND 3 NC 4 FPGA の TDO 5 CPLD の TDI 6 TCK 7 TMS

FPGA と CPLD の JTAG はチェーン接続されています。 CPLD の TDO が FPGA の TDI に接続されています。

２-５-７CN8

機能メーカ名品番 G ビット LAN ヒロセ TM11R-5L-88

ピン番号信号名 1 TXD+_0 2 TXD-_0 3 TXD+_1 4 TXD+_2 5 TXD-_2 6 TXD-_1

14

7 TXD+_3 8 TXD-_3 9,F LAN_FG

２-５-８CN9

機能メーカ名品番 LAN ヒロセ TM11R-5L-88

ピン番号信号名 1 TPO+ 2 TPO- 3 TPI+ 4 ターミネーション 5 ターミネーション 6 TPI- 7 ターミネーション 8 ターミネーション 9,F LAN_FG

２-５-９CN10・CN11

機能メーカ名品番電源コネクタ日圧 B2P-VH(LF)(SN)

CN10 ピン番号信号名 1 +5V 入力 2 GND

CN11

機能メーカ名品番電源コネクタ日圧 B7B-XH-A(LF)(SN)

ピン番号信号名 1 +5V 入力 2 GND 3 GND

15

4 -5V 入力（PC-104BUS） 5 -12V 入力（PC-104BUS 6 +12V 入力（PC-104BUS 7 +2V～+5V RTC バックアップ電源

２-５-１０CN12

機能メーカ名品番 ttySC0(RS232C) 日圧 B9B-ZR-SM4-TF(LF)(SN)

CPU の SCIF0

ピン番号信号名 1 NC 2 RxD 3 TxD 4 DTR(6 番とボード上で接続) 5 -GND 6 DSR(4 番とボード上で接続) 7 RTS 8 CTS 9 NC

２-５-１１CN13

機能メーカ名品番起動コンソール ttySC1(RS232C)

日圧 B3B-ZR-SM4-TF(LF)(SN)

CPU の SCIF1

ピン番号信号名 1 TxD 2 GND 3 RxD

２-５-１２CN14


CPU の SCIF2

16


２-５-１３CN15


CPU の SCIF5


２-５-１４CN16

機能メーカ名品番タッチパネル日圧 B8B-ZR-SM4-TF(LF)(SN)

CPU の SCIF3 TP interface GUNZE AHL-71N

ピン番号信号名 1 YL 2 YLref 3 YUref 4 YU 5 XR 6 XL 7 XLref 8 XRref

２-５-１５CN17

機能メーカ名品番 USB2.0 TypeA 日圧 UBA-4RS-D14T-4D(LF)(SN)

ピン番号信号名

17

1 VBus（下側） 2 D-（下側） 3 D+（下側） 4 GND（下側） 5 VBus（上側） 6 D-（上側） 7 D+（上側） 8 GND（上側） 9 GND(シールド) 10 GND(Foot) 11 GND(Foot)

２-５-１６CN18

機能メーカ名品番 USB2.0 TypeA 日圧 UBA-4RS-D14T-4D(LF)(SN)

ピン番号信号名 1 VBus（下側） 2 D-（下側） 3 D+（下側） 4 GND（下側） 5 VBus（上側） 6 D-（上側） 7 D+（上側） 8 GND（上側） 9 GND(シールド) 10 GND(Foot) 11 GND(Foot)

２-５-１７CN19

機能メーカ名品番 VGA DVI-I オムロン XM4M-2932-1312

ピン番号信号名 1 TMDS2-

18

2 TMDS2+ 3 GND(TMDS2,4 SHIELD) 4 NC 5 NC 6 DDC_Clock 7 DDC_Data 8 Analog VSYNC 9 TMDS1- 10 TMDS1+ 11 GND(TMDS1,3 SHIELD) 12 NC 13 NC 14 100Ωを介して+5V に接続 15 GND 16 HotPlugDetect 17 TMDS0- 18 TMDS0+ 19 GND(TMDS0,5 SHIELD) 20 NC 21 NC 22 GND(TMDS ClockSHIELD 23 TMDS Clock+ 24 TMDS Clock- C1 Analog RED C2 Analog GREEN C3 Analog BLUE C4 Analog HSYNC C5 Analog GND

２-５-１８CN20

機能メーカ名品番 VGA LVDS ヒロセ DF13A-20DP-1.25(26)

ピン番号信号名 1 Y0M

19

2 Y0P 3 GND 4 10KΩPullup +3.3V 5 Y1M 6 Y1P 7 GND 8 GPIO2 9 Y2M 10 Y2P 11 GND 12 GPIO1 13 Y3M 14 Y3P 15 GND 16 GPIO0 with MOS Tr 17 CLOCK OUT M 18 CLOCK OUT P 19 HotPlugDetect 20 +3.3V

２-５-１９CN21

機能メーカ名品番 VGA DVO ヒロセ DF13A-30DP-1.25(26)

ピン番号 Z9s 信号名 DVO 信号名 1 DBH/TC3 B5 2 DE/TC0 B2 3 VSYNC/TC2 B4 4 GND 5 HSYNC/TC1 B3 6 +3.3V 7 D0/TB6 B1 8 D1/TB5 B0 9 D2/TB3 G4 10 D3/TB2 G3

20

11 IDCK-/TB0 G1 12 GND 13 IDCK+/TA6 G0 14 +3.3V 15 D4/TB1 G2 16 GND 17 D5/TB4 G5 18 D6/TA5 R5 19 D10/TA1 R1 20 D7/TA4 R4 21 D8/TA3 R3 22 D11/TA0 R0 23 D9/TA2 R2 24 HotPlugDetect 25 GPIOF/PDnPDWN nPDWN 26 GPIOG PullDown 27 GPIOD/TC6 DE 28 GPIOI/TC5 VSYNC 29 GPIOC/CLK_IN CLK 30 GPIOH/TC4 HSYNC

２-５-２０SH2009IO-CN1

SH2009 の CN6 と同じです。

２-５-２１SH2009IO-CN2

機能メーカ名品番 AD コンバータ入力日圧 S9B-ZR-SM4A-TF(LF)(SN)

ピン番号信号名備考 1 ADC-CH0 各 CH 間、CPU 部との間は非絶縁

です。 2 ADC-CH1 3 ADC-CH2 4 ADC-CH3 5 ADC-CH4 6 ADC-CH5

21

7 ADC-CH6 8 ADC-CH7 9 ADC-COM ADC 入力のコモンです

２-５-２２SH2009IO-CN3

機能メーカ名品番 2.5”HDD 接続ヒロセ A3A-44PA-2SV(71)

No 信号信号 No 1 nRESET GND 2 3 D7 D8 4 5 D6 D9 6 7 D5 D10 8 9 D4 D11 10 11 D3 D12 12 13 D2 D13 14 15 D1 D14 16 17 D0 D15 18 19 GND KEY 20 21 DMARQ(not use) GND 22 23 nIOW GND 24 25 nIOR GND 26 27 IOCHKRDY CSEL 28 29 nDACK1(not use) GND 30 31 IRQ nIOIS16 32 33 A1 nPDIAG 34 35 A0 A2 36 37 nCS0 nCS1 38 39 nIDEACT GND 40 41 +5V LOGIC +5V MOTER 42 43 GND Resv 44

２-５-２３SH2009IO-CN4(ttyS0)～CN11(ttyS7)

機能メーカ名品番 RS232C 日圧 S9B-ZR-SM4A-TF(LF)(SN)

22

ピン番号信号名備考 1 DCD 2 RxD 3 TxD 4 DTR 6 番ピンと接続 5 GND 6 DSR 4 番ピンと接続 7 RTS 8 CTS 9 RI

ttyS0～ttyS5 は、RS485 と供用になっており、ソフトウェアで切り換え（シリアル制御信

号の DTR で選択）ができます。なお、送信データは、常に RS232-TxD/RS485 両方に出力

します。

２-５-２４SH2009IO-CN12

機能メーカ名品番 RS485 Phoenix Contact 1844375

ピン番号信号名備考 1 ttyS0-A SH2009IO:SW1-1 を ON すると

100Ωで AB 間をターミネートし

ます。 2 ttyS0-B 3 ttyS0-FG 4 ttyS1-A SH2009IO:SW1-2 を ON すると









23

17 ttyS5-B 100Ωで AB 間をターミネートし

ます。 18 ttyS5-FG

２-６ディップスイッチ

SW2 SW ビット番号接続先機能 1 CPU GPIO FPGA プログラムデータ選択 2 CPU GPIO 未定義 3 CPU GPIO 未定義 4 CPU GPIO ブートデバイスセレクト 5 FPGA-IO 6 FPGA-IO 7 FPGA-IO ・NOR Flash nWP ON で書き込み禁止 8 FPGA-IO DVI-D、DVO の切り換え

OFF=DVI ON=DVO

２-６-１SW2-1 FPGAプログラムデータの選択

CPU はリセットが解除されると、NOR Flash ROM の先頭（0 番地）から実行を開始し

ます。ここに sh-ipl があります。OFF（default）の場合、FPGA プログラムデータは、sh-ipl自身が持っているものを FPGA にロードします。 ON にすると sh-ipl は、FPGA プログラムデータだけを NOR Flash ROM の別の領域か

らをロードします。 FPGA が正常にプログラムされないと本ボードは動作しませんが、一部の固定された部

分（回路）を除き、ユーザーが FPGA 内に別の回路を組み込むことを可能にしています。

これにより、本来の FPGA プログラムデータの消滅を恐れずにユーザー独自の回路を本ボ

ードに組み込めます。 NOR Flash ROM は、Linux の mtd デバイス（メモリテクノロジデバイス）でサポート

しています。領域内容 mtd0 sh-ipl サイズ：512KB mtd1 別の FPGA プログラムデータサイズ：256KB mtd2 Linux kernal サイズ 3MB mtd3 未使用サイズ：28.25MB

24

２-６-２SW2-4,5,6 ブートデバイス選択

本ボードは、SH-Linux をオンボード ROM,CF カード、2.5”ハードディスクおよびイー

サネット(eth1 側。NFS ブート)からブートすることができます。 SW2-6 SW2-5 SW2-4 ブートデバイス自動起動 ON OFF OFF CF カード ON ON OFF ON オンボード ROM ON ON ON OFF HDD ON ON ON ON イーサーブート ON

SW2-6 が OFF の場合は、sh-ipl のコマンド待ちになります。 sh-ipl のコマンド（抜粋） ? --- Show this message (HELP) b --- Boot the system c --- Boot the system from device 0 d --- Boot the system from device 1 e --- Ether Boot r --- Boot from ROM m --- Memory test

２-７メモリ・IOマップ・割り込み

本ボードは、SH4A コアが持つ 32 ビット拡張アドレスモードで動作しています。（リセットが解除され、sh-ipl が起動すると 32 ビット拡張アドレスモードに移行しま

す）

２-７-１物理アドレスマップ

アドレスデバイス io/mem バス幅/BUS 0x00000000-0x01ffffff NOR Flash ROM mem 16bit 0x04000000-0x040000ff LAN9218 （eth1） io 32bit 0x04000200-0x0400021f FPGA 内部の割込みコントローラ io 0x04000220-0x04000223 CF スロットステータス io 0x04000224-0x04000227 ディップ SW2-5～SW2-8 io 0x04000228-0x0400022b FPGA デバイス ID io 0x0400022c-0x0400022f I2C コントローラ io 0x04000234-0x04000237 CF スロット電源制御 io 0x04000238-0x0400023b CF スロットリセット制御 io 0x04000300-0x040003ff AD コンバータ io 0x14000000-0x140fffff CF スロットメモリ空間 mem 8/16

dynamic 0x14100000-0x141fffff CF スロット IO 空間 io 0x14200000-0x142fffff CF スロットレジスタ空間 mem

25

0x17000000-0x177fffff PC-104BUS メモリ空間 mem 0x17800000-0x17ffffff PC-104BUS IO 空間 io 0x18000000-0x1800001f NAND Flash ROM mem 8bit 0x18000200-0x18000207 UART(FPGA 内) ttyS0 io 0x18000210-0x18000217 UART(FPGA 内) ttyS1 io 0x18000220-0x18000227 UART(FPGA 内) ttyS2 io 0x18000230-0x18000237 UART(FPGA 内) ttyS3 io 0x18000240-0x18000247 UART(FPGA 内) ttyS4 io 0x18000250-0x18000257 UART(FPGA 内) ttyS5 io 0x18000260-0x18000267 UART(FPGA 内) ttyS6 io 0x18000270-0x18000277 UART(FPGA 内) ttyS7 io 0x1a800170-0x1a80017f IDE HDD io 16bit 0x1a800376-0x1a80037f IDE HDD io 0x40000000-0x5fffffff 512MB DDR2 SDRAM mem 32bit 0xc0000000-0xc1ffffff VGA VRAM(Z9s) mem PCI 0xfd000000-0xfd000fff USB OHCI(μPD720101) mem 0xfd001000-0xfd001fff USB OHCI(μPD720101) mem 0xfd002000-0xfd0020ff USB EHCI(μPD720101) mem 0xfd040000-0xfd07ffff VGA REG(Z9s) memio 0xfd080000-0xfd09ffff GbitLAN(e1000) mem 0xfe0401c0-0xfe0401c7 PCI configration REGS io 0xfe210000-0xfe21003f GbitLAN(e1000) io

注意：論理アドレスは物理アドレスと異なります。本書の 4-4-2、kernel ソース

およびルネサス社の R8A77850(SH7785)ユーザーズガイドを参照してくだ

さい。

CPU内部要因以外の割り込み

割り込み線要因備考 CPU nIRQ0 IDE HDD CPU nIRQ1 LAN9218(eth1) CPU nIRQ2 RTC CPU nIRQ3 未使用プルアップ CPU nIRQ4 CF スロット CPU nIRQ5 PC104BUS SIRQ 各 SIRQ の OR IRQ5 は、要因レジスタ 0x04000210(FPGA 内)を read で割り込み要因を判別します。

26

0x0000--03 pc104bus SIRQ3 0x04000210 の下位 8 ビット 0x0000--04 pc104bus SIRQ 0x0000--05 pc104bus SIRQ 0x0000--06 pc104bus SIRQ 0x0000--07 pc104bus SIRQ 0x0000--09 pc104bus SIRQ 0x0000--0a pc104bus SIRQ 0x0000--0b pc104bus SIRQ 0x0000--0c pc104bus SIRQ 0x0000--0e pc104bus SIRQ 0x0000--0f pc104bus SIRQ

CPU nIRQ6 UART IRQ 各 IRQ の OR IRQ6 は、要因レジスタ 0x04000210(FPGA 内)を read で割り込み要因を判別します。

0x000080-- UART0 0x04000210 の bit15..8 0x000081-- UART1 0x000082-- UART2 0x000083-- UART3 0x000084-- UART4 0x000085-- UART5 0x000086-- UART6 0x000087-- UART7

CPU nIRQ7 未使用 FPGA 内で’H’に固定 CPU nINTA USB(μPD720101) PCIBUS intA CPU nINTB VGA(Z9s) PCIBUS intB CPU nINTC GbitLAN(e1000) PCIBUS intC

27

２-８CPUボード回路図

１-１-１トップページ

28

１-１-２CPU-A

29

１-１-３CF スロット

30

１-１-４DDR2 メモリ

31

１-１-５PC104BUS

32

１-１-６FPGA/CPLD

33

１-１-７Gbit LAN

34

１-１-８LAN

35

１-１-９NAND Flash ROM

36

１-１-１０電源

37

１-１-１１RS232C

１-１-１２RTC

１-１-１３タッチパネル

38

１-１-１４USB

39

１-１-１５VGA

40

２-９IOボード回路図

１-１-１６トップ

41

１-１-１７ADC

１-１-１８IDE

42

１-１-１９RS232C

43

１-１-２０RS485

44

２-１０CPLDソース

２-１０-１VHDL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity syscon is port( CKIO : in std_logic; -- 100.000MHz nCPU_CS0 : in std_logic; nCPU_CS1 : in std_logic; nCPU_CS4 : in std_logic; nCPU_CS6 : in std_logic; CPU_RDY : out std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; nCPU_WE0 : in std_logic; SA : in std_logic_vector(25 downto 0); SD : inout std_logic; nIRL : out std_logic_vector(7 downto 4); -- [4]:MODE0, [5]:MODE1, [6]:MODE2, [7]:MODE3 nCPU_CE2B : inout std_logic; -- MODE12 nCPU_IOIS16 : out std_logic; -- MODE13 nIRLIN : in std_logic_vector(7 downto 4); nIDE_CS0 : out std_logic; nIDE_CS1 : out std_logic; nIDE_DEN : out std_logic; nIDE_IOR : out std_logic; nIDE_IOW : out std_logic; IDE_IOCHRDY : in std_logic; nLAN_CS : out std_logic; nIOIS16in : in std_logic; FPGACCLK : out std_logic; nFPGA_PROG : in std_logic; nNANDCS0 : out std_logic; nNANDCS1 : out std_logic; nNANDCS2 : out std_logic;

45

nNANDCS3 : out std_logic; R_nB0 : in std_logic; R_nB1 : in std_logic; R_nB2 : in std_logic; R_nB3 : in std_logic; nWP0 : out std_logic; nWP1 : out std_logic; RxDOUT : out std_logic; RxDIN : in std_logic; nRESET : in std_logic); end syscon; architecture syscon_arch of syscon is constant CPUMODE : std_logic_vector(14 downto 0) := "100001111010000"; --"100001111010000" -- cpu core:x18 ram:x18 GDTA:x4.5 DU:STOP IO:x1.5 DDR:x9 BUS:x3(4 downto 0) -- CS0 16bit SRAM mode (7 downto 5) -- Little endian (8) -- Master (9) -- Extal osc (20) -- PCI host moode (12 downto 11) -- 32-bit address extended mode (13) -- Normal operation(14) signal init_state : std_logic := '1'; signal nand_cs : std_logic; signal nand_sts : std_logic; signal init_cnt : std_logic_vector(2 downto 0) := "000"; signal nand_rdy : std_logic; signal ide_cs : std_logic; signal nand_wait : std_logic := '0'; signal nand_data_wait_cnt : integer range 0 to 31 := 0; -- nIORD rising to nIOWR falling : 100ns minimum signal nand_write_wait_cnt : integer range 0 to 31 := 0; -- nIORD rising to nIOWR falling : 100ns minimum signal nand_data_inhibit : std_logic := '0'; signal nand_write_inhibit : std_logic := '0'; signal nand_data_wait : std_logic := '0'; signal nand_write_wait : std_logic := '0'; signal nand_busy : std_logic := '0'; signal cpu_iowr : std_logic; signal cpu_rdy_s : std_logic := '1'; begin

46

nIRL <= CPUMODE(3 downto 0) when init_state='1' else nIRLIN; RxDOUT <= CPUMODE(7) when init_state='1' else RxDIN; nCPU_CE2B <= CPUMODE(12) when init_state='1' else 'Z'; nCPU_IOIS16 <= CPUMODE(13) when init_state='1' else nIOIS16in; CPU_RDY <= cpu_rdy_s; nWP0 <= nRESET; nWP1 <= nRESET; FPGACCLK <= '0' when nCPU_CS1='0' and SA(25 downto 23)="111" and nCPU_WE0='0' else '1'; nLAN_CS <= '0' when nCPU_CS1='0' and SA(25 downto 23)="000" and SA(9)='0' else '1'; ide_cs <= '1' when init_state='0' and nCPU_CS6='0' and SA(25 downto 23)="101" else '0'; nIDE_CS0 <= '0' when ide_cs='1' and SA(9)='0' else '1'; nIDE_CS1 <= '0' when ide_cs='1' and SA(9)='1' else '1'; nIDE_DEN <= '0' when ide_cs='1' and (nCPU_IORD='0' or nCPU_IOWR='0') else '1'; nIDE_IOR <= '0' when (ide_cs='1' and nCPU_IORD='0') or (nand_cs='1' and nCPU_IORD='0' and (SA(1 downto 0)/="00" or nand_data_inhibit='0')) else '1'; nIDE_IOW <= '0' when (ide_cs='1' and nCPU_IOWR='0') or (nand_cs='1' and nCPU_IOWR='0' and (SA(1 downto 0)/="00" or nand_data_inhibit='0') and nand_write_inhibit='0') else '1'; nand_wait <= '1' when nand_cs='1' and ((SA(1 downto 0)="00" and nand_data_wait='1') or (nand_write_wait='1' and cpu_iowr='1')) else '0'; nand_cs <= '1' when init_state='0' and nCPU_CS6='0' and SA(25 downto 23)="000" and SA(9)='0' and SA(2)='0' else '0'; nand_sts <= '1' when nCPU_CS6='0' and SA(25 downto 23)="000" and SA(9)='0' and SA(2)='1' else '0'; nNANDCS0 <= '0' when nand_cs='1' and SA(4 downto 3)="00" else '1'; nNANDCS1 <= '0' when nand_cs='1' and SA(4 downto 3)="01" else '1'; nNANDCS2 <= '0' when nand_cs='1' and SA(4 downto 3)="10" else '1'; nNANDCS3 <= '0' when nand_cs='1' and SA(4 downto 3)="11" else '1'; nand_rdy <= '1' when R_nB0='1' and R_nB1='1' and R_nB2='1' and R_nB3='1' else '0'; SD <= nand_rdy when nand_sts='1' and nCPU_IORD='0' and SA(2)='1' else 'Z'; process (nRESET,CKIO) begin if nRESET='0' then init_state <= '1'; cpu_rdy_s <= '1'; init_cnt <= "000"; elsif rising_edge(CKIO) then if init_cnt/="111" then init_cnt <= init_cnt + 1; end if; if nCPU_CS0='0' or init_cnt="111" then init_state <= '0'; end if;

47

if (ide_cs='1' and IDE_IOCHRDY='0') or nand_wait='1' then cpu_rdy_s <= '0'; else cpu_rdy_s <= '1'; end if; end if; end process; process (nRESET, CKIO) begin if nRESET='0' then nand_data_wait_cnt <= 0; nand_write_wait_cnt <= 0; nand_data_inhibit <= '0'; nand_write_inhibit <= '0'; nand_data_wait <= '0'; nand_write_wait <= '0'; nand_busy <= '0'; cpu_iowr <= '0'; elsif rising_edge(CKIO) then cpu_iowr <= not nCPU_IOWR; if nand_cs='1' and cpu_iowr='1' and SA(1 downto 0)/="00" then -- NAND write cycle (ALE=1 or CLE=1) nand_data_wait_cnt <= 18; nand_data_inhibit <= '1'; nand_data_wait <= '1'; nand_busy <= '1'; else if nand_data_wait_cnt/=0 then nand_data_wait_cnt <= nand_data_wait_cnt - 1; else nand_data_wait <= '0'; nand_busy <= '0'; end if; if nand_data_wait_cnt < 4 then nand_data_inhibit <= '0'; end if; end if; if nand_cs='1' and nCPU_IORD='0' then nand_write_wait_cnt <= 16;

48

nand_write_inhibit <= '1'; nand_write_wait <= '1'; else if nand_write_wait_cnt/=0 then nand_write_wait_cnt <= nand_write_wait_cnt - 1; else nand_write_wait <= '0'; end if; if nand_write_wait_cnt < 4 then nand_write_inhibit <= '0'; end if; end if; end if; end process; end syscon_arch;

２-１０-２UCF NET "CKIO" PERIOD = 10 ns; #PINLOCK_BEGIN NET "nIRLIN<5>" LOC = "S:PIN1"; NET "nIRLIN<7>" LOC = "S:PIN2"; NET "nIDE_CS0" LOC = "S:PIN3"; NET "nIDE_IOR" LOC = "S:PIN6"; NET "nIDE_CS1" LOC = "S:PIN7"; NET "nFPGA_PROG" LOC = "S:PIN8"; NET "nIRLIN<6>" LOC = "S:PIN12"; NET "nIRLIN<4>" LOC = "S:PIN13"; NET "nLAN_CS" LOC = "S:PIN14"; NET "nCPU_IORD" LOC = "S:PIN16"; NET "CPU_RDY" LOC = "S:PIN18"; NET "nCPU_WE0" LOC = "S:PIN19"; NET "nIDE_IOW" LOC = "S:PIN20"; NET "nCPU_CS1" LOC = "S:PIN21"; NET "nCPU_CS0" LOC = "S:PIN22"; NET "nIRL<7>" LOC = "S:PIN23"; NET "nCPU_IOWR" LOC = "S:PIN27"; NET "SA<24>" LOC = "S:PIN28";

49

NET "nIRL<6>" LOC = "S:PIN29"; NET "IDE_IOCHRDY" LOC = "S:PIN30"; NET "SA9" LOC = "S:PIN31"; NET "nIRL<5>" LOC = "S:PIN32"; NET "nRESET" LOC = "S:PIN33"; NET "SA<25>" LOC = "S:PIN34"; NET "nCPU_CE2B" LOC = "S:PIN36"; NET "nIRL<4>" LOC = "S:PIN37"; NET "nCPU_CS4" LOC = "S:PIN38"; NET "nCPU_IOIS16" LOC = "S:PIN39"; NET "nCPU_CS6" LOC = "S:PIN40"; NET "nIDE_DEN" LOC = "S:PIN41"; NET "FPGACCLK" LOC = "S:PIN42"; NET "CKIO" LOC = "S:PIN43"; NET "nIOIS16in" LOC = "S:PIN44"; #PINLOCK_END

２-１１FPGAソースファイル

２-１１-１トップsh2009.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sh2009 is port ( -- CPU signal CKIO : in std_logic; -- 100MHz SA : in std_logic_vector(25 downto 0); SD : inout std_logic_vector(31 downto 0); CPU_RD_nWR : in std_logic; nCPU_CS1 : in std_logic; nCPU_CS2 : in std_logic; nCPU_CS4 : in std_logic; nCPU_CE1A : in std_logic;

50

nCPU_CE2A : in std_logic; nCPU_CE1B : in std_logic; nCPU_CE2B : in std_logic; nCPU_RD : in std_logic; nCPU_WE0 : in std_logic; nCPU_WE1 : in std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; nCPU_BS : in std_logic; CPU_RDY : out std_logic; nCPU_IOIS16 : out std_logic; nCPU_DRQ0 : out std_logic; nCPU_DACK0 : in std_logic; nCPU_DRQ1 : out std_logic; nCPU_DACK1 : in std_logic; nIRL : out std_logic_vector(7 downto 4); -- CF CD : inout std_logic_vector(15 downto 0); CA : out std_logic_vector(10 downto 0); nCFCE1 : out std_logic; nCFCE2 : out std_logic; nCFMRD : out std_logic; nCFMWR : out std_logic; nCFIORD : out std_logic; nCFIOWR : out std_logic; nCFWAIT : in std_logic; CFRESET : out std_logic; nCD1 : in std_logic; nCD2 : in std_logic; nCFSTSCHG : in std_logic; nCFDRQ : in std_logic; nCFIOIS16 : in std_logic; nREG : out std_logic; nVCCD1 : out std_logic; nCFIRQ : in std_logic; -- local bus RD_nWR : out std_logic; nIORD : out std_logic;

51

nIOWR : out std_logic; -- external bus nXDEN : out std_logic; EXT_RESET : out std_logic; nEXT_MEMR : out std_logic; nEXT_MEMW : out std_logic; nEXT_SMEMR : out std_logic; nEXT_SMEMW : out std_logic; nEXT_IORD : out std_logic; nEXT_IOWR : out std_logic; nEXT_IOIS16 : in std_logic; EXT_AEN : out std_logic; nEXT_SBHE : out std_logic; EXT_BALE : out std_logic; EXT_SYSCLK : out std_logic; EXT_OSC : out std_logic; EXT_IOCHRDY : in std_logic; nEXT_NOWAIT : in std_logic; EXT_SIRQ : in std_logic_vector(15 downto 3); nEXT_DRQ0 : in std_logic; nEXT_DRQ1 : in std_logic; EXT_DACK0 : out std_logic; EXT_DACK1 : out std_logic; -- ADC ADC_SDO : in std_logic; ADC_SCK : out std_logic; nADC_BUSY : in std_logic; ADC_SDI : out std_logic; AD_START : out std_logic; nAD_RD : out std_logic; -- I2C bus SDA : inout std_logic; SCL : inout std_logic; -- SIO TxD : out std_logic_vector(7 downto 0); RxD485 : in std_logic_vector(7 downto 0);

52

RxD232 : in std_logic_vector(7 downto 0); nRTS : out std_logic_vector(7 downto 0); nCTS : in std_logic_vector(7 downto 0); -- nDTR : out std_logic_vector(7 downto 0); nDSR : in std_logic_vector(7 downto 0); nDCD : in std_logic_vector(7 downto 0); nRI : in std_logic_vector(7 downto 0); Tx485ENB : out std_logic_vector(7 downto 0); -- VGA DVI_nDVO : out std_logic; -- DUMMY TMP00 : out std_logic; -- System Control DIPSW : in std_logic_vector(7 downto 4); nRESET_OUT : out std_logic; nRESET : in std_logic); end sh2009; architecture rtl of sh2009 is component sh2009_sys port ( -- CPU signal CKIO : in std_logic; -- 96MHz SA : in std_logic_vector(25 downto 0); SD_in : in std_logic_vector(7 downto 0); nCPU_CS1 : in std_logic; nCPU_CS2 : in std_logic; nCPU_CS4 : in std_logic; nCPU_CE1A : in std_logic; nCPU_CE2A : in std_logic; nCPU_CE1B : in std_logic; nCPU_CE2B : in std_logic; nCPU_RD : in std_logic; nCPU_WE0 : in std_logic; nCPU_WE1 : in std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; nCPU_BS : in std_logic;

53

CPU_RD_nWR : in std_logic; CPU_RDY : out std_logic; nCPU_IOIS16 : out std_logic; nCFIOIS16 : in std_logic; nCFWAIT : in std_logic; cf_power_is_on : in std_logic; -- local bus RD_nWR : out std_logic; nIORD : out std_logic; nIOWR : out std_logic; rd : out std_logic; wr : out std_logic_vector(1 downto 0); -- address decode cf_cs : out std_logic; cf_io_cs : out std_logic; cf_mem_cs : out std_logic; cf_reg_n : out std_logic; cfsts_cs : out std_logic; cfctlset_cs : out std_logic; cfctlclr_cs : out std_logic; uart_cs : out std_logic_vector(7 downto 0); intr_cs : out std_logic; adc_cs : out std_logic; i2c_cs : out std_logic; dipsw_cs : out std_logic; dev_id_cs : out std_logic; -- PC104 nXDEN : out std_logic; EXT_RESET : out std_logic; nEXT_MEMR : out std_logic; nEXT_MEMW : out std_logic; nEXT_SMEMR : out std_logic; nEXT_SMEMW : out std_logic; nEXT_IORD : out std_logic; nEXT_IOWR : out std_logic; EXT_AEN : out std_logic; nEXT_SBHE : out std_logic;

54

EXT_BALE : out std_logic; nEXT_IOIS16 : in std_logic; EXT_SYSCLK : out std_logic; EXT_OSC : out std_logic; EXT_IOCHRDY : in std_logic; nEXT_NOWAIT : in std_logic; -- DUMMY TMP00 : out std_logic; -- System control bus_mode : in std_logic; nRESET_OUT : out std_logic; reset : in std_logic); end component; -- sh2009_sys component compact_flash port ( -- Host I/F CKIO : in std_logic; SA : in std_logic_vector(25 downto 0); SD_in : in std_logic_vector(15 downto 0); SD_out : out std_logic_vector(15 downto 0); RD_nWR : in std_logic; nCPU_CE1 : in std_logic; nCPU_CE2 : in std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; -- internal signals cf_irq : out std_logic; cf_cs : in std_logic; cf_io_cs : in std_logic; cf_mem_cs : in std_logic; cf_reg_n : in std_logic; cfsts_cs : in std_logic; cfctlset_cs : in std_logic; cfctlclr_cs : in std_logic; cf_status : out std_logic_vector(7 downto 0); cf_power_is_on : out std_logic; wr : in std_logic;

55

-- Compact Flash I/F CA : out std_logic_vector(10 downto 0); CD : inout std_logic_vector(15 downto 0); nCFCE1 : out std_logic; nCFCE2 : out std_logic; nCFMRD : out std_logic; nCFMWR : out std_logic; nCFIORD : out std_logic; nCFIOWR : out std_logic; nCD1 : in std_logic; nCD2 : in std_logic; nCFSTSCHG : in std_logic; nCFDRQ : in std_logic; nCFIOIS16 : in std_logic; CFRESET : out std_logic; nREG : out std_logic; nVCCD1 : out std_logic; nCFIRQ : in std_logic); end component; component uart port ( TxD : out std_logic; RxD : in std_logic; TxENB485 : out std_logic; IRQ : out std_logic; nRTS : out std_logic; nCTS : in std_logic; nDTR : out std_logic; nDSR : in std_logic; nDCD : in std_logic; nRI : in std_logic; OUT1 : out std_logic; OUT2 : out std_logic; thre : out std_logic; tsre : out std_logic; addr : in std_logic_vector(2 downto 0); -- system address bus data_in : in std_logic_vector(7 downto 0); -- system data bus data_out : out std_logic_vector(7 downto 0); -- system data bus cs : in std_logic; -- chip select

56

rd_n : in std_logic; -- read command wr_n : in std_logic; -- write command clk : in std_logic; -- system clock reset : in std_logic); end component; component irqcont is port ( CKIO : in std_logic; SD_in : in std_logic_vector(31 downto 0); SD_out : out std_logic_vector(31 downto 0); SA : in std_logic_vector(4 downto 0); EXT_SIRQ : in std_logic_vector(15 downto 3); UART_IRQ : in std_logic_vector(7 downto 0); CF_IRQ : in std_logic; nIRL : out std_logic_vector(7 downto 4); CS : in std_logic; nRD : in std_logic; WR : in std_logic; reset : in std_logic); end component; component adc port ( SDI : out std_logic; SDO : in std_logic; SCK : out std_logic; START : out std_logic; nBUSY : in std_logic; nRD : out std_logic; addr : in std_logic_vector(7 downto 0); -- system address bus sd_in : in std_logic_vector(15 downto 0); -- system data bus sd_out : out std_logic_vector(15 downto 0); -- system data bus cs : in std_logic; -- chip select rd : in std_logic; -- read pulse (1 clk) wr : in std_logic_vector(1 downto 0); -- write pulse (1 clk) clk : in std_logic; -- system clock (96MHz) reset : in std_logic); end component; component i2c port ( SDA : inout std_logic; SCL : inout std_logic;

57

data_in : in std_logic_vector(15 downto 0); -- system data bus data_out : out std_logic_vector(7 downto 0); -- system data bus cs : in std_logic; -- chip select wr : in std_logic_vector(1 downto 0); -- write pulse (1 clk) clk : in std_logic; -- system clock reset : in std_logic); -- system reset end component; constant deviceid : std_logic_vector(31 downto 0) := x"49544F40"; --ITO@ signal gnd : std_logic := '0'; signal vcc : std_logic := '1'; signal RxD : std_logic_vector(7 downto 0); signal nDTR : std_logic_vector(7 downto 0); signal txenb485 : std_logic_vector(7 downto 0); signal uart_out2: std_logic_vector(7 downto 0); signal sd_in : std_logic_vector(31 downto 0); signal uart_sd_out : std_logic_vector(63 downto 0); signal uart_irq : std_logic_vector(7 downto 0) := (others => '0'); signal uart_out1: std_logic_vector(7 downto 0); signal cf_sd_out : std_logic_vector(15 downto 0); signal rd : std_logic; signal wr : std_logic_vector(1 downto 0); signal dipsw_cs : std_logic; signal uart_cs : std_logic_vector(7 downto 0); signal reset : std_logic; signal cf_cs : std_logic; signal cf_io_cs : std_logic; signal cf_mem_cs : std_logic; signal cf_reg_n : std_logic; signal cfsts_cs : std_logic; signal cfctlset_cs : std_logic; signal cfctlclr_cs : std_logic; signal cf_status : std_logic_vector(7 downto 0); signal cf_power_is_on : std_logic; signal reset_cnt : std_logic_vector(15 downto 0) := (others => '0'); signal thre : std_logic; signal tsre : std_logic; signal intrc_out : std_logic_vector(31 downto 0); signal intr_cs : std_logic; signal cf_irq : std_logic;

58

signal bus_mode : std_logic; signal cmd_mask : std_logic; signal dev_id_cs : std_logic; signal adc_cs : std_logic; signal i2c_cs : std_logic; signal i2c_sd_out : std_logic_vector(7 downto 0); signal adc_sd_out : std_logic_vector(15 downto 0); attribute ASYNC_REG : string; attribute ASYNC_REG of fd1 : label is "TRUE"; begin bus_mode <= '0'; DVI_nDVO <= DIPSW(7); -- PC-104 nCPU_DRQ0 <= nEXT_DRQ0; nCPU_DRQ1 <= nEXT_DRQ1; EXT_DACK0 <= '1' when nCPU_DACK0='0' else '0'; EXT_DACK1 <= '1' when nCPU_DACK1='0' else '0'; RxD(0) <= RxD485(0) when nDTR(0)='1' else RxD232(0); RxD(1) <= RxD485(1) when nDTR(1)='1' else RxD232(1); RxD(2) <= RxD485(2) when nDTR(2)='1' else RxD232(2); RxD(3) <= RxD485(3) when nDTR(3)='1' else RxD232(3); RxD(4) <= RxD485(4) when nDTR(4)='1' else RxD232(4); RxD(5) <= RxD485(5) when nDTR(5)='1' else RxD232(5); RxD(6) <= RxD485(6) when nDTR(6)='1' else RxD232(6); RxD(7) <= RxD485(7) when nDTR(7)='1' else RxD232(7); Tx485ENB(0) <= '1' when uart_out2(0)='1' and txenb485(0)='1' else '0'; Tx485ENB(1) <= '1' when uart_out2(1)='1' and txenb485(1)='1' else '0'; Tx485ENB(2) <= '1' when uart_out2(2)='1' and txenb485(2)='1' else '0'; Tx485ENB(3) <= '1' when uart_out2(3)='1' and txenb485(3)='1' else '0'; Tx485ENB(4) <= '1' when uart_out2(4)='1' and txenb485(4)='1' else '0'; Tx485ENB(5) <= '1' when uart_out2(5)='1' and txenb485(5)='1' else '0'; Tx485ENB(6) <= '1' when uart_out2(6)='1' and txenb485(6)='1' else '0'; Tx485ENB(7) <= '1' when uart_out2(7)='1' and txenb485(7)='1' else '0'; sd_in <= SD;

59

SD(7 downto 0) <= (not DIPSW)&"0000" when dipsw_cs='1' and nCPU_RD='0' else uart_sd_out(7 downto 0) when uart_cs(0)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(15 downto 8) when uart_cs(1)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(23 downto 16) when uart_cs(2)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(31 downto 24) when uart_cs(3)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(39 downto 32) when uart_cs(4)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(47 downto 40) when uart_cs(5)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(55 downto 48) when uart_cs(6)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else uart_sd_out(63 downto 56) when uart_cs(7)='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else cf_status when cfsts_cs='1' and nCPU_RD='0' else cf_sd_out(7 downto 0) when cf_cs='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else intrc_out(7 downto 0) when intr_cs='1' and nCPU_RD='0' else i2c_sd_out(7 downto 0) when i2c_cs='1' and nCPU_RD='0' else adc_sd_out(7 downto 0) when adc_cs='1' and nCPU_RD='0' else deviceid(7 downto 0) when dev_id_cs='1' and nCPU_RD='0' else "ZZZZZZZZ"; SD(15 downto 8) <= cf_sd_out(15 downto 8) when cf_cs='1' and nCPU_IORD='0' and CPU_RD_nWR='1' else intrc_out(15 downto 8) when intr_cs='1' and nCPU_RD='0' else adc_sd_out(15 downto 8) when adc_cs='1' and nCPU_RD='0' else deviceid(15 downto 8) when dev_id_cs='1' and nCPU_RD='0' else "ZZZZZZZZ"; SD(31 downto 16) <= intrc_out(31 downto 16) when intr_cs='1' and nCPU_RD='0' else deviceid(31 downto 16) when dev_id_cs='1' and nCPU_RD='0' else "ZZZZZZZZZZZZZZZZ"; process(CKIO) begin if rising_edge(CKIO) then if nRESET='0' then reset_cnt(15 downto 1) <= (others => '0'); else reset_cnt(15 downto 1) <= reset_cnt(14 downto 0); end if; reset <= not reset_cnt(15); end if; end process; fd1 : fd port map (c=>CKIO, d=>nRESET, q=>reset_cnt(0));

60

sys1 : sh2009_sys port map ( CKIO => CKIO, SA => SA, SD_in => sd_in(7 downto 0), nCPU_CS1 => nCPU_CS1, nCPU_CS2 => nCPU_CS2, nCPU_CS4 => nCPU_CS4, nCPU_CE1A => nCPU_CE1A, nCPU_CE2A => nCPU_CE2A, nCPU_CE1B => nCPU_CE1B, nCPU_CE2B => nCPU_CE2B, nCPU_RD => nCPU_RD, nCPU_WE0 => nCPU_WE0, nCPU_WE1 => nCPU_WE1, nCPU_IORD => nCPU_IORD, nCPU_IOWR => nCPU_IOWR, nCPU_BS => nCPU_BS, CPU_RD_nWR => CPU_RD_nWR, CPU_RDY => CPU_RDY, nCFWAIT => nCFWAIT, cf_power_is_on => cf_power_is_on, RD_nWR => RD_nWR, nIORD => nIORD, nIOWR => nIOWR, rd => rd, wr => wr, cf_cs => cf_cs, cf_io_cs => cf_io_cs, cf_mem_cs => cf_mem_cs, cf_reg_n => cf_reg_n, cfsts_cs => cfsts_cs, cfctlset_cs => cfctlset_cs, cfctlclr_cs => cfctlclr_cs, bus_mode => bus_mode, nXDEN => nXDEN, EXT_RESET => EXT_RESET, nEXT_MEMR => nEXT_MEMR, nEXT_MEMW => nEXT_MEMW, nEXT_SMEMR => nEXT_SMEMR,

61

nEXT_SMEMW => nEXT_SMEMW, nEXT_IORD => nEXT_IORD, nEXT_IOWR => nEXT_IOWR, EXT_AEN => EXT_AEN, nEXT_SBHE => nEXT_SBHE, EXT_BALE => EXT_BALE, EXT_SYSCLK => EXT_SYSCLK, EXT_OSC => EXT_OSC, nEXT_IOIS16 => nEXT_IOIS16, nCFIOIS16 => nCFIOIS16, nCPU_IOIS16 => nCPU_IOIS16, EXT_IOCHRDY => EXT_IOCHRDY, nEXT_NOWAIT => nEXT_NOWAIT, adc_cs => adc_cs, i2c_cs => i2c_cs, dev_id_cs => dev_id_cs, dipsw_cs => dipsw_cs, uart_cs => uart_cs, intr_cs => intr_cs, nRESET_OUT => nRESET_OUT, TMP00 => TMP00, reset => reset); cf1 : compact_flash port map ( CKIO => CKIO, SA => SA, SD_in => sd_in(15 downto 0), SD_out => cf_sd_out, RD_nWR => CPU_RD_nWR, nCPU_CE1 => nCPU_CE1A, nCPU_CE2 => nCPU_CE2A, nCPU_IORD => nCPU_IORD, nCPU_IOWR => nCPU_IOWR, cf_irq => cf_irq, cf_cs => cf_cs, cf_io_cs => cf_io_cs, cf_mem_cs => cf_mem_cs, cf_reg_n => cf_reg_n, cfsts_cs => cfsts_cs, cfctlset_cs => cfctlset_cs,

62

cfctlclr_cs => cfctlclr_cs, cf_status => cf_status, cf_power_is_on => cf_power_is_on, wr => wr(0), CA => CA, CD => CD, nCFCE1 => nCFCE1, nCFCE2 => nCFCE2, nCFMRD => nCFMRD, nCFMWR => nCFMWR, nCFIORD => nCFIORD, nCFIOWR => nCFIOWR, nCD1 => nCD1, nCD2 => nCD2, nCFSTSCHG => nCFSTSCHG, nCFDRQ => nCFDRQ, nCFIOIS16 => nCFIOIS16, CFRESET => CFRESET, nREG => nREG, nVCCD1 => nVCCD1, nCFIRQ => nCFIRQ); generate1 : for i in 0 to 7 generate begin uart_i : uart port map ( TxD => TxD(i), RxD => RxD(i), TxENB485 => txenb485(i), IRQ => uart_irq(i), nRTS => nRTS(i), nCTS => nCTS(i), nDTR => nDTR(i), nDSR => nDSR(i), nDCD => nDCD(i), nRI => nRI(i), OUT1 => uart_out1(i), OUT2 => uart_out2(i), thre => open, tsre => open,

63

addr => SA(2 downto 0), data_in => sd_in(7 downto 0), data_out => uart_sd_out(7+i*8 downto i*8), cs => uart_cs(i), rd_n => nCPU_IORD, wr_n => nCPU_IOWR, clk => CKIO, reset => reset); end generate; intr1 : irqcont port map ( CKIO => CKIO, SD_in => sd_in, SD_out => intrc_out, SA => SA(4 downto 0), EXT_SIRQ => EXT_SIRQ, UART_IRQ => uart_irq, CF_IRQ => cf_irq, nIRL => nIRL, CS => intr_cs, nRD => nCPU_RD, WR => wr(0), reset => reset); adc1 : adc port map ( SDI => ADC_SDI, SDO => ADC_SDO, SCK => ADC_SCK, START => AD_START, nBUSY => nADC_BUSY, nRD => nAD_RD, addr => SA(7 downto 0), sd_in => sd_in(15 downto 0), sd_out => adc_sd_out, cs => adc_cs, rd => rd, wr => wr, clk => CKIO, reset => reset);

64

i2c1 : i2c port map ( SDA => SDA, SCL => SCL, data_in => sd_in(15 downto 0), data_out => i2c_sd_out, cs => i2c_cs, wr => wr, clk => CKIO, reset => reset); end rtl;

２-１１-２sh2009_sys.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all; entity sh2009_sys is port ( -- CPU signal CKIO : in std_logic; -- 100MHz SA : in std_logic_vector(25 downto 0); SD_in : in std_logic_vector(7 downto 0); nCPU_CS1 : in std_logic; nCPU_CS2 : in std_logic; nCPU_CS4 : in std_logic; nCPU_CE1A : in std_logic; nCPU_CE2A : in std_logic; nCPU_CE1B : in std_logic; nCPU_CE2B : in std_logic; nCPU_RD : in std_logic; nCPU_WE0 : in std_logic; nCPU_WE1 : in std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; nCPU_BS : in std_logic; CPU_RD_nWR : in std_logic;

65

CPU_RDY : out std_logic; nCPU_IOIS16 : out std_logic; nCFIOIS16 : in std_logic; nCFWAIT : in std_logic; cf_power_is_on : in std_logic; -- local bus RD_nWR : out std_logic; nIORD : out std_logic; -- not used nIOWR : out std_logic; -- not used rd : out std_logic; -- read command (1 clk) wr : out std_logic_vector(1 downto 0); -- write command (1 clk, byte0,1) -- address decode cf_cs : out std_logic; cf_io_cs : out std_logic; cf_mem_cs : out std_logic; cf_reg_n : out std_logic; cfsts_cs : out std_logic; cfctlset_cs : out std_logic; cfctlclr_cs : out std_logic; uart_cs : out std_logic_vector(7 downto 0); intr_cs : out std_logic; adc_cs : out std_logic; i2c_cs : out std_logic; dipsw_cs : out std_logic; dev_id_cs : out std_logic; -- PC104 nXDEN : out std_logic; EXT_RESET : out std_logic; nEXT_MEMR : out std_logic; nEXT_MEMW : out std_logic; nEXT_SMEMR : out std_logic; nEXT_SMEMW : out std_logic; nEXT_IORD : out std_logic; nEXT_IOWR : out std_logic; EXT_AEN : out std_logic; nEXT_SBHE : out std_logic; EXT_BALE : out std_logic;

66

EXT_SYSCLK : out std_logic; EXT_OSC : out std_logic; nEXT_IOIS16 : in std_logic; EXT_IOCHRDY : in std_logic; nEXT_NOWAIT : in std_logic; -- DUMMY TMP00 : out std_logic; -- System control bus_mode : in std_logic; nRESET_OUT : out std_logic; reset : in std_logic); end sh2009_sys; architecture sh2009_arch of sh2009_sys is signal iowr : std_logic_vector(1 downto 0); signal re : std_logic := '0'; signal we : std_logic_vector(2 downto 0) := (others => '0'); signal wr_s : std_logic_vector(1 downto 0) := (others => '0'); signal rdy : std_logic := '1'; signal cf_rdy : std_logic_vector(1 downto 0) := (others => '1'); signal cmd_cnt : integer range 0 to 7 := 0; signal cf_cs_s : std_logic; signal cf_io_cs_s : std_logic; signal busclk : std_logic := '0'; signal osc : std_logic_vector(2 downto 0) := "000"; signal ckcnt : std_logic_vector(2 downto 0) := (others => '0'); signal ext_wait : std_logic; signal pc104_mcs : std_logic; signal pc104_iocs : std_logic; signal cpu_rdy_s : std_logic := '1'; type bus_state_type is (bus_idle, bus_data_read, bus_data_write, bus_end); signal bus_state : bus_state_type := bus_idle; attribute ASYNC_REG : string; attribute ASYNC_REG of fd1 : label is "TRUE"; begin

67

fd1 : fd port map (c=>CKIO, d=>nCFWAIT, q=>cf_rdy(0)); -- I/O map -- CS0 0x00000000 - 0x03ffffff 16bit 95ns NOR Flash ROM (boot memory) -- CS1 0x04000000 - 0x047fffff 32bit LAN9218 -- 0x04000200 32bit 50ns interrupt mode register -- SD(7 downto 6) EXT SIRQ3 00:falling, 01:rising, 10:low level, 11:high level -- SD(9 downto 8) EXT SIRQ4 00:falling, 01:rising, 10:low level, 11:high level -- SD(11 downto 10) EXT SIRQ5 00:falling, 01:rising, 10:low level, 11:high level -- SD(13 downto 12) EXT SIRQ6 00:falling, 01:rising, 10:low level, 11:high level -- SD(15 downto 14) EXT SIRQ7 00:falling, 01:rising, 10:low level, 11:high level -- SD(19 downto 18) EXT SIRQ9 00:falling, 01:rising, 10:low level, 11:high level -- SD(21 downto 20) EXT SIRQ10 00:falling, 01:rising, 10:low level, 11:high level -- SD(23 downto 22) EXT SIRQ11 00:falling, 01:rising, 10:low level, 11:high level -- SD(25 downto 24) EXT SIRQ12 00:falling, 01:rising, 10:low level, 11:high level -- SD(29 downto 28) EXT SIRQ14 00:falling, 01:rising, 10:low level, 11:high level -- SD(31 downto 30) EXT SIRQ15 00:falling, 01:rising, 10:low level, 11:high level -- 0x04000204 32bit 50ns interrupt mask set register -- 0x04000208 32bit 50ns interrupt mask clear register -- 0x0400020c 16bit 50ns interrupt ack register -- SD(3) =1 int ack 3(EXT SIRQ3) -- SD(4) =1 int ack 4(EXT SIRQ4) -- SD(5) =1 int ack 5(EXT SIRQ5) -- SD(6) =1 int ack 6(EXT SIRQ6) -- SD(7) =1 int ack 7(EXT SIRQ7) -- SD(9) =1 int ack 9(EXT SIRQ9) -- SD(10)=1 int ack 10(EXT SIRQ10) -- SD(11)=1 int ack 11(EXT SIRQ11) -- SD(12)=1 int ack 12(EXT SIRQ12) -- SD(14)=1 int ack 14(EXT SIRQ14) -- SD(15)=1 int ack 15(EXT SIRQ15) -- 0x04000210 8bit 50ns interrupt vector register -- 0 UART0 -- 1 UART1 -- 2 UART2 -- 3 UART3 -- 4 UART4 -- 5 UART5 -- 6 UART6 -- 7 UART7 -- 0x04000220 8bit 50ns CF Status (bit0,1 00=CARD Detect, bit2 0=Status changed, bit3 1=READY) read only

68

-- 0x04000224 8bit 50ns DIPSW(7 downto 4) -- 0x04000228 32bit 50ns device ID -- 0x0400022c 8bit 50ns 50ns i2c -- 0x04000230 32bit 50ns 50ns ADC -- 0x04000234 8bit 50ns CF control bit set. CF_RESET(bit0), CF_POWER(bit1) -- 0x04000238 8bit 50ns CF control bit clear. CF_RESET(bit0), CF_POWER(bit1) -- 0x07800000 8bit 50ns FPGA Program (when DONE='0') -- CS2 0x08000000 - 0x0bffffff 32bit DDR2 -- CS3 0x0c000000 - 0x0fffffff 32bit DDR2 -- CS4 0x10000000 - 0x13ffffff 32bit PCI -- CS5 0x14000000 - 0x15ffffff 16bit Dynamic I/O -- 0x14000000 - 0x140fffff(1MB) 16bit 360ns CF slot Attribute Memory (IOIS16=16bit) -- 0x14100000 - 0x141fffff(1MB) 16bit 160ns CF slot I/O (Dynamic I/O) -- 0x14200000 - 0x142fffff(1MB) 16bit 360ns CF slot Common Memory (IOIS16=16bit) -- CS5 0x16000000 - 0x17ffffff 16bit Dynamic I/O -- 0x17000000 - 0x173fffff(4MB) 16bit 360ns PC-104 memory SLOW (IOIS16=16bit) -- 0x17400000 - 0x177fffff(4MB) 16bit 40ns PC-104 memory FAST (IOIS16=16bit) -- 0x17800000 - 0x1780ffff(64kB) 16bit 360ns PC-104 I/O SLOW (Dynamic I/O) -- 0x17c00000 - 0x17c0ffff(64kB) 16bit 40ns PC-104 I/O FAST (Dynamic I/O) -- CS6 (0x18000000 - 0x19ffffff) CS6PCR setting 8-bit I/O space -- 0x18000000 - 0x1800000f 8bit 40ns NAND(Decoder is CPLD. can decode SA25..SA23,SA9) -- 0x18000200 - 0x18000207 8bit 40ns UART0 -- 0x18000210 - 0x18000217 8bit 40ns UART1 -- 0x18000220 - 0x18000227 8bit 40ns UART2 -- 0x18000230 - 0x18000237 8bit 40ns UART3 -- 0x18000240 - 0x18000247 8bit 40ns UART4 -- 0x18000250 - 0x18000257 8bit 40ns UART5 -- 0x18000260 - 0x18000267 8bit 40ns UART6 -- 0x18000270 - 0x18000277 8bit 40ns UART7 -- CS6 (0x1a000000 - 0x1bffffff) CS6PCR setting Dynamic I/O bus sizing -- 0x1a800000 - 0x1affffff(8MB) 16bit 160ns IDE(Decoder is CPLD. can decode SA25..SA23) (Dynamic I/O) -- CPUIRN0(CPUIRQ0) IDE I/F -- CPUIRN1(CPUIRQ1) LAN9218 -- CPUIRN2(CPUIRQ2) not used -- CPUIRN3(CPUIRQ3) not used -- nIRL(7 downto 4) -- 0(0b0000) not used -- 1(0b0001) UART0-UART7,CF (see interrupt vector register)

69

-- 2(0b0010) EXT SIRQ3 -- 3(0b0011) EXT SIRQ4 -- 4(0b0100) EXT SIRQ5 -- 5(0b0101) EXT SIRQ6 -- 6(0b0110) EXT SIRQ7 -- 7(0b0111) not used -- 8(0b1000) EXT SIRQ9 -- 9(0b1001) EXT SIRQ10 -- 10(0b1010) EXT SIRQ11 -- 11(0b1011) EXT SIRQ12 -- 12(0b1100) not used -- 13(0b1101) EXT SIRQ14 -- 14(0b1110) EXT SIRQ15 -- 15(0b1111) no interrupt request -- interrupt vector register -- 0 UART0 -- 1 UART1 -- 2 UART2 -- 3 UART3 -- 4 UART4 -- 5 UART5 -- 6 UART6 -- 7 UART7 -- 8 CF -- 15 no interrupt TMP00 <= nCPU_CS2 or nEXT_NOWAIT or nCPU_WE1 or nCPU_CE1A or nCPU_CE2A or nCPU_CS4; nRESET_OUT <= 'Z'; wr <= wr_s; CPU_RDY <= cpu_rdy_s; -- CS1(32bit SRAM I/F) intr_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5)='0' else '0'; cfsts_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1000" else '0'; dipsw_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1001" else '0'; dev_id_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1010" else '0'; i2c_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1011" else '0'; cfctlset_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1101" else '0';

70

cfctlclr_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="10" and SA(5 downto 2)="1110" else '0'; adc_cs <= '1' when nCPU_CS1 ='0' and SA(25 downto 23)="000" and SA(9 downto 8)="11" else '0'; -- CS5A(PCMCIA DYNAMIC I/O) cf_cs_s <= '1' when (nCPU_CE1A='0' or nCPU_CE2A='0') and SA(25)='0' else '0'; cf_io_cs_s <= '1' when cf_cs_s='1' and nCPU_CE1A='0' and SA(20)='1' else '0'; cf_mem_cs <= '1' when cf_cs_s='1' and SA(20)='0' else '0'; cf_reg_n <= SA(21); cf_cs <= cf_cs_s; cf_io_cs <= cf_io_cs_s; -- CS5B(PCMCIA DYNAMIC I/O) -- PC-104 pc104_mcs <= '1' when (nCPU_CE1A='0' or nCPU_CE2A='0') and SA(25 downto 23)="110" else '0'; pc104_iocs <= '1' when (nCPU_CE1A='0' or nCPU_CE2A='0') and SA(25 downto 23)="111" else '0'; EXT_RESET <= reset; nXDEN <= '0' when (pc104_mcs='1' or pc104_iocs='1') and (CPU_RD_nWR='0' or nCPU_IORD='0') else '1'; nEXT_SBHE <= '0' when nCPU_CE2A='0' else '1'; EXT_AEN <= '0' when (pc104_mcs='1' or pc104_iocs='1') else '1'; EXT_BALE <= '1' when (pc104_mcs='1' or pc104_iocs='1') else '0'; nEXT_SMEMR <= '0' when pc104_mcs='1' and nCPU_IORD='0' else '1'; nEXT_SMEMW <= '0' when pc104_mcs='1' and nCPU_IOWR='0' else '1'; nEXT_MEMR <= '0' when pc104_mcs='1' and nCPU_IORD='0' else '1'; nEXT_MEMW <= '0' when pc104_mcs='1' and nCPU_IOWR='0' else '1'; nEXT_IORD <= '0' when pc104_iocs='1' and (nCPU_CE1A='0' or (nEXT_IOIS16='0' and nCPU_CE2A='0')) and nCPU_IORD='0' else '1'; nEXT_IOWR <= '0' when pc104_iocs='1' and (nCPU_CE1A='0' or (nEXT_IOIS16='0' and nCPU_CE2A='0')) and nCPU_IOWR='0' else '1'; -- CS6A(PCMCIA 8bit I/O) uart_cs(0) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="000" else '0'; uart_cs(1) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="001" else '0'; uart_cs(2) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="010" else '0'; uart_cs(3) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="011" else '0'; uart_cs(4) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="100" else '0'; uart_cs(5) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="101" else '0'; uart_cs(6) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="110" else '0'; uart_cs(7) <= '1' when nCPU_CE1B='0' and SA(25 downto 23)="000" and SA(9)='1' and SA(6 downto 4)="111" else '0'; -- Local BUS nCPU_IOIS16 <= '1' when (nCPU_CE1A='1' and nCPU_CE2A='0' and SA(25)='0' and SA(20)='1') -- invalid CF access or (nCPU_CE1B='1' and nCPU_CE2B='0' and SA(25)='1') -- invalid IDE access

71

or (cf_io_cs_s='1' and nCFIOIS16='1') or (pc104_iocs='1' and nEXT_IOIS16='1') else '0'; nIORD <= '0' when nCPU_RD='0' else '1'; -- not used nIOWR <= '0' when nCPU_WE0='0' else '1'; -- not used EXT_SYSCLK <= busclk when bus_mode='0' else CKIO; EXT_OSC <= osc(2); process (CKIO) begin if rising_edge(CKIO) then osc <= osc + 1; if ckcnt="101" then ckcnt <= "000"; busclk <= not busclk; else ckcnt <= ckcnt+1; end if; end if; end process; process (reset, CKIO) begin if reset='1' then ext_wait <= '0'; cpu_rdy_s <= '1'; elsif rising_edge(CKIO) then if (pc104_mcs='1' or pc104_iocs='1') and EXT_IOCHRDY='0' then ext_wait <= '1'; else ext_wait <= '0'; end if; if cf_cs_s='1' and cf_rdy(0)='0' and cf_power_is_on='1' then cf_rdy(1) <= '0'; else cf_rdy(1) <= '1'; end if; if rdy='0' or cf_rdy(1)='0' or ext_wait='1' then cpu_rdy_s <= '0'; else cpu_rdy_s <= '1';

72

end if; end if; end process; process (CKIO) begin if rising_edge(CKIO) then iowr(1) <= iowr(0); if (nCPU_CS1='0' or nCPU_CE1A='0' or nCPU_CE2A='0' or nCPU_CE1B='0' or nCPU_CE2B='0') and CPU_RD_nWR='0' and nCPU_BS='0' then iowr(0) <= '1'; else iowr(0) <= '0'; end if; if (nCPU_CS1='0' or nCPU_CE1A='0' or nCPU_CE2A='0' or nCPU_CE1B='0' or nCPU_CE2B='0') and CPU_RD_nWR='1' and nCPU_BS='0' then rd <= '1'; else rd <= '0'; end if; wr_s <= (others => '0'); if ((nCPU_CS1='0' and nCPU_WE0='0') or nCPU_CE1A='0' or nCPU_CE1B='0') and iowr(1)='1' then wr_s(0) <= '1'; end if; if ((nCPU_CS1='0' and nCPU_WE1='0') or nCPU_CE2A='0' or nCPU_CE2B='0') and iowr(1)='1' then wr_s(1) <= '1'; end if; end if; end process; end sh2009_arch;

２-１１-３conpact_flash.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; library unisim; use unisim.vcomponents.all;

73

entity compact_flash is port ( -- Host I/F CKIO : in std_logic; SA : in std_logic_vector(25 downto 0); SD_in : in std_logic_vector(15 downto 0); SD_out : out std_logic_vector(15 downto 0); RD_nWR : in std_logic; nCPU_CE1 : in std_logic; nCPU_CE2 : in std_logic; nCPU_IORD : in std_logic; nCPU_IOWR : in std_logic; -- internal signals cf_irq : out std_logic; cf_cs : in std_logic; cf_io_cs : in std_logic; cf_mem_cs : in std_logic; cf_reg_n : in std_logic; cfsts_cs : in std_logic; cfctlset_cs : in std_logic; cfctlclr_cs : in std_logic; cf_status : out std_logic_vector(7 downto 0); cf_power_is_on : out std_logic; wr : in std_logic; -- Compact Flash I/F CD : inout std_logic_vector(15 downto 0); CA : out std_logic_vector(10 downto 0); nCFCE1 : out std_logic; nCFCE2 : out std_logic; nCFMRD : out std_logic; nCFMWR : out std_logic; nCFIORD : out std_logic; nCFIOWR : out std_logic; nCD1 : in std_logic; nCD2 : in std_logic; nCFSTSCHG : in std_logic; nCFDRQ : in std_logic; nCFIOIS16 : in std_logic; CFRESET : out std_logic;

74

nREG : out std_logic; nVCCD1 : out std_logic; nCFIRQ : in std_logic); end compact_flash; architecture compact_flash_arch of compact_flash is signal cf_det : std_logic_vector(1 downto 0); signal power_is_on : std_logic; signal cf_power : std_logic := '0'; signal cf_reset_s : std_logic := '0'; attribute ASYNC_REG : string; attribute ASYNC_REG of fd1 : label is "TRUE"; begin cf_power_is_on <= power_is_on; cf_status <= "00" & cf_power & '0' & nCFIRQ & nCFSTSCHG & nCD1 & nCD2; CFRESET <= '1' when cf_power='1' and cf_det(1)='1' and cf_reset_s='1' else '0'; power_is_on <= '1' when cf_power='1' and cf_det="11" else '0'; nREG <= cf_reg_n when power_is_on='1' else 'Z'; CA <= SA(10 downto 0) when power_is_on='1' else (others => 'Z'); CD <= SD_in when power_is_on='1' and RD_nWR='0' and cf_cs='1' else (others => 'Z'); nCFCE1 <= 'Z' when power_is_on='0' else '0' when nCPU_CE1='0' and cf_cs='1' else '1'; nCFCE2 <= 'Z' when power_is_on='0' else '0' when nCPU_CE2='0' and cf_cs='1' else '1'; nCFMRD <= 'Z' when power_is_on='0' else '0' when cf_mem_cs='1' and nCPU_IORD='0' else '1'; nCFMWR <= 'Z' when power_is_on='0' else '0' when cf_mem_cs='1' and nCPU_IOWR='0' else '1'; nCFIORD <= 'Z' when power_is_on='0' else

75

'0' when (nCPU_CE1='0' or (nCPU_CE2='0' and nCFIOIS16='0')) and cf_io_cs='1' and nCPU_IORD='0' else '1'; nCFIOWR <= 'Z' when power_is_on='0' else '0' when (nCPU_CE1='0' or (nCPU_CE2='0' and nCFIOIS16='0')) and cf_io_cs='1' and nCPU_IOWR='0' else '1'; SD_out <= CD; nVCCD1 <= '0' when power_is_on='1' else -- 3.3V '1'; cf_irq <= '1' when power_is_on='1' and nCFIRQ='0' else '0' ; cf_det(0) <= '1' when nCD1='0' and nCD2='0' else '0'; fd1 : fd port map (c=>CKIO, d=>cf_det(0), q=>cf_det(1)); process(CKIO) begin if rising_edge(CKIO) then if cfctlset_cs='1' and wr='1' then if SD_in(0)='1' then cf_reset_s <= '1'; end if; if SD_in(1)='1' then cf_power <= '1'; end if; end if; if cfctlclr_cs='1' and wr='1' then if SD_in(0)='1' then cf_reset_s <= '0'; end if; if SD_in(1)='1' then cf_power <= '0'; end if; end if; end if; end process;

76

end compact_flash_arch;

２-１１-４uart.vhd -- -- UART transmitter with integral 16 byte FIFO buffer -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity uart_tx is port ( data : in std_logic_vector(7 downto 0); we : in std_logic; -- write pulse (1 clk) reset : in std_logic; fifo_reset : in std_logic; baud_clk : in std_logic; txd : out std_logic := '1'; thre : out std_logic; tsre : out std_logic; tx_irq : out std_logic := '0'; tx_enb : out std_logic := '0'; clr_irq : in std_logic; fifo_en : in std_logic; parity_en : in std_logic; parity_evn : in std_logic; parity_stick : in std_logic; chrlen : in std_logic_vector(1 downto 0); stopbit : in std_logic; afe : in std_logic; cts : in std_logic; clk : in std_logic); end uart_tx; architecture rtl of uart_tx is component fifo8bitx16 port ( clk : in std_logic; din : in std_logic_vector(7 downto 0);

77

rd_en : in std_logic; rst : in std_logic; wr_en : in std_logic; dout : out std_logic_vector(7 downto 0); empty : out std_logic; full : out std_logic); end component; signal fifo_rd : std_logic := '0'; signal fifo_dout : std_logic_vector(7 downto 0); signal fifo_empty : std_logic_vector(1 downto 0) := "11"; signal fifo_full : std_logic; signal sft_reg : std_logic_vector(7 downto 0); signal sft_cnt : std_logic_vector(2 downto 0); signal baud_cnt : std_logic_vector(4 downto 0) := (others => '0'); signal bitlen : std_logic_vector(2 downto 0); signal stop_len : std_logic_vector(4 downto 0); signal parity_dat : std_logic; type txstate_type is (st_idle, st_start, st_data, st_parity, st_stop); signal txstate : txstate_type := st_idle; begin txfifo : fifo8bitx16 port map ( clk => clk, din => data, rd_en => fifo_rd, rst => fifo_reset, wr_en => we, dout => fifo_dout, empty => fifo_empty(0), full => fifo_full); thre <= fifo_empty(0); process(clk) begin if rising_edge(clk) then if reset='1' then txstate <= st_idle; txd <= '1'; sft_cnt <= (others => '0'); tsre <= '1';

78

tx_irq <= '0'; tx_enb <= '0'; baud_cnt <= (others => '0'); else fifo_empty(1) <= fifo_empty(0); if fifo_empty(0)='1' and (txstate=st_idle or txstate=st_stop) then tsre <= '1'; else tsre <= '0'; end if; if fifo_empty="01" then tx_irq <= '1'; elsif clr_irq='1' or we='1' then tx_irq <= '0'; end if; case txstate is when st_idle => txd <= '1'; when st_start => txd <= '0'; when st_data => txd <= sft_reg(0); when st_parity=> txd <= not parity_dat; when st_stop => txd <= '1'; when others => txd <= '1'; end case; bitlen <= ('0' & chrlen) + "100"; if stopbit='0' then stop_len <= "01111"; elsif chrlen="00" then stop_len <= "10111"; else stop_len <= "11111"; end if; fifo_rd <= '0'; if baud_clk='1' then baud_cnt <= baud_cnt + 1; case txstate is when st_idle => tx_enb <= '0'; if fifo_empty(0)='0' and (cts='1' or afe='0') then sft_reg <= fifo_dout;

79

parity_dat <= parity_evn; fifo_rd <= '1'; txstate <= st_start; tx_enb <= '1'; baud_cnt <= (others => '0'); end if; when st_start => if baud_cnt(3 downto 0)="1111" then txstate <= st_data; sft_cnt <= (others => '0'); end if; when st_data => if baud_cnt(3 downto 0)="1111" then baud_cnt(4) <= '0'; if sft_cnt=bitlen then if parity_en='1' then txstate <= st_parity; else txstate <= st_stop; end if; end if; parity_dat <= parity_dat xor (not parity_stick and sft_reg(0)); sft_reg(6 downto 0) <= sft_reg(7 downto 1); sft_cnt <= sft_cnt + 1; end if; when st_parity => if baud_cnt(3 downto 0)="1111" then txstate <= st_stop; end if; when st_stop => if baud_cnt=stop_len then if fifo_empty(0)='0' and (cts='1' or afe='0') then sft_reg <= fifo_dout; parity_dat <= parity_evn; fifo_rd <= '1'; txstate <= st_start; baud_cnt <= (others => '0'); else txstate <= st_idle; end if;

80

end if; when others => txstate <= st_idle; end case; end if; end if; end if; end process; end rtl; ---------------------------------------------------------------------------------------------------- -- -- UART Receiver with integral 16 byte FIFO buffer -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity uart_rx is port ( rxd : in std_logic; rx_data_irq : out std_logic; rx_timeout_irq : out std_logic; data : out std_logic_vector(7 downto 0); rd : in std_logic; -- read pulse (1 clk) clr_err : in std_logic; reset : in std_logic; fifo_reset : in std_logic; fifo_err : out std_logic := '0'; baud_clk : in std_logic; rx_rdy : out std_logic := '0'; rx_ovr : out std_logic := '0'; rx_perr : out std_logic := '0'; rx_ferr : out std_logic := '0'; rx_brk : out std_logic := '0'; fifo_thresh : in std_logic_vector(3 downto 0); parity_en : in std_logic; parity_evn : in std_logic; parity_stick : in std_logic;

81

chrlen : in std_logic_vector(1 downto 0); stopbit : in std_logic; clk : in std_logic); end uart_rx; architecture rtl of uart_rx is component fifo11bitx16 port ( clk : in std_logic; din : in std_logic_vector(10 downto 0); rd_en : in std_logic; rst : in std_logic; wr_en : in std_logic; data_count : out std_logic_vector(4 downto 0); dout : out std_logic_vector(10 downto 0); empty : out std_logic; full : out std_logic); end component; signal fifo_we : std_logic; signal fifo_empty : std_logic; signal fifo_full : std_logic; signal sft_reg : std_logic_vector(10 downto 0); signal fifo_dout : std_logic_vector(10 downto 0); signal sft_cnt : std_logic_vector(2 downto 0); signal baud_cnt : std_logic_vector(3 downto 0) := (others => '0'); signal bitlen : std_logic_vector(2 downto 0); signal parity_dat : std_logic; signal brk_det : std_logic; signal rd1 : std_logic := '0'; signal rx_timer : std_logic_vector(5 downto 0); signal rx_timeout : std_logic_vector(5 downto 0); signal data_count : std_logic_vector(4 downto 0); signal rx_timeout_irq_s : std_logic := '0'; type rxstate_type is (st_idle, st_start, st_data, st_parity, st_stop, st_break); signal rxstate : rxstate_type := st_idle; begin rxfifo : fifo11bitx16 port map ( clk => clk, din => sft_reg,

82

rd_en => rd, rst => fifo_reset, wr_en => fifo_we, data_count => data_count, dout => fifo_dout, empty => fifo_empty, full => fifo_full); data <= fifo_dout(7 downto 0); rx_rdy <= not fifo_empty; rx_timeout <= ("00" & chrlen & "00") + "011100" + (stopbit & "00"); rx_timeout_irq <= rx_timeout_irq_s; process(clk) begin if rising_edge(clk) then if reset='1' then rxstate <= st_idle; rx_ovr <= '0'; rx_perr <= '0'; rx_ferr <= '0'; rx_brk <= '0'; rd1 <= '0'; fifo_err <= '0'; rx_timeout_irq_s <= '0'; rx_data_irq <= '0'; baud_cnt <= (others => '0'); else if data_count>=('0' & fifo_thresh) and rx_timeout_irq_s='0' then rx_data_irq <= '1'; else rx_data_irq <= '0'; end if; if rd='1' or fifo_empty='1' or (rx_timeout_irq_s='0' and rxstate/=st_idle) then rx_timer <= (others => '0'); rx_timeout_irq_s <= '0'; elsif rx_timer=rx_timeout then rx_timeout_irq_s <= '1'; elsif baud_clk='1' then rx_timer <= rx_timer + 1;

83

end if; if fifo_empty='1' and rd='1' then fifo_err <= '1'; end if; if rd1='1' then rx_perr <= fifo_dout(8); rx_ferr <= fifo_dout(9); rx_brk <= fifo_dout(10); end if; if clr_err='1' then rx_perr <= '0'; rx_ferr <= '0'; rx_brk <= '0'; rx_ovr <= '0'; fifo_err <= '0'; end if; rd1 <= rd; bitlen <= ('0' & chrlen) + "100"; fifo_we <= '0'; if baud_clk='1' then baud_cnt <= baud_cnt + 1; case rxstate is when st_idle => if RxD='0' then baud_cnt <= (others => '0'); rxstate <= st_start; sft_reg <= (others => '0'); end if; when st_start => if baud_cnt="0111" and RxD/='0' then rxstate <= st_idle; end if; if baud_cnt="1111" then rxstate <= st_data; sft_cnt <= (others => '0'); parity_dat <= parity_evn; brk_det <= '0'; end if; when st_data => if baud_cnt="0111" then

84

case chrlen is when "00" => -- 5bit sft_reg(4 downto 0) <= RxD & sft_reg(4 downto 1); when "01" => -- 6bit sft_reg(5 downto 0) <= RxD & sft_reg(5 downto 1); when "10" => -- 7bit sft_reg(6 downto 0) <= RxD & sft_reg(6 downto 1); when others => -- 8bit sft_reg(7 downto 0) <= RxD & sft_reg(7 downto 1); end case; parity_dat <= parity_dat xor (not parity_stick and RxD); brk_det <= brk_det or RxD; end if; if baud_cnt="1111" and sft_cnt=bitlen then if parity_en='1' then rxstate <= st_parity; else rxstate <= st_stop; sft_reg(8) <= '0'; -- no parity error end if; end if; if baud_cnt="1111" then sft_cnt <= sft_cnt + 1; end if; when st_parity => if baud_cnt="0111" then sft_reg(8) <= (not parity_dat) xor (not parity_stick and RxD); -- parity error brk_det <= brk_det or RxD; end if; if baud_cnt="1111" then rxstate <= st_stop; end if; when st_stop => if baud_cnt="0111" then sft_reg(9) <= not RxD; -- framing error sft_reg(10) <= not (brk_det or RxD); -- break indicator brk_det <= brk_det or RxD; end if; if baud_cnt="1000" then if brk_det='0' then

85

rxstate <= st_break; else rxstate <= st_idle; end if; if fifo_full='1' then rx_ovr <= '1'; else fifo_we <= '1'; end if; end if; when st_break => if RxD='1' and brk_det='1' then rxstate <= st_idle; end if; brk_det <= RxD; when others => rxstate <= st_idle; end case; end if; end if; end if; end process; end rtl; ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity uart is port ( TxD : out std_logic; RxD : in std_logic; TxENB485 : out std_logic; IRQ : out std_logic; nRTS : out std_logic; nCTS : in std_logic; nDTR : out std_logic; nDSR : in std_logic;

86

nDCD : in std_logic; nRI : in std_logic; OUT1 : out std_logic; OUT2 : out std_logic; thre : out std_logic; tsre : out std_logic; addr : in std_logic_vector(2 downto 0); -- system address bus data_in : in std_logic_vector(7 downto 0); -- system data bus data_out : out std_logic_vector(7 downto 0); -- system data bus cs : in std_logic; -- chip select rd_n : in std_logic; -- read command wr_n : in std_logic; -- write command clk : in std_logic; -- system clock reset : in std_logic); end uart; architecture rtl of uart is -- -- declaration of UART transmitter with integral 16 byte FIFO buffer -- component uart_tx port ( data : in std_logic_vector(7 downto 0); we : in std_logic; reset : in std_logic; fifo_reset : in std_logic; baud_clk : in std_logic; txd : out std_logic; thre : out std_logic; tsre : out std_logic; tx_irq : out std_logic; tx_enb : out std_logic; clr_irq : in std_logic; fifo_en : in std_logic; parity_en : in std_logic; parity_evn : in std_logic; parity_stick : in std_logic; chrlen : in std_logic_vector(1 downto 0); stopbit : in std_logic; afe : in std_logic; cts : in std_logic;

87

clk : in std_logic); end component; -- -- declaration of UART Receiver with integral 16 byte FIFO buffer -- component uart_rx port ( rxd : in std_logic; rx_data_irq : out std_logic; rx_timeout_irq : out std_logic; data : out std_logic_vector(7 downto 0); rd : in std_logic; clr_err : in std_logic; reset : in std_logic; fifo_reset : in std_logic; fifo_err : out std_logic; baud_clk : in std_logic; rx_rdy : out std_logic; rx_ovr : out std_logic; rx_perr : out std_logic; rx_ferr : out std_logic; rx_brk : out std_logic; fifo_thresh : in std_logic_vector(3 downto 0); parity_en : in std_logic; parity_evn : in std_logic; parity_stick : in std_logic; chrlen : in std_logic_vector(1 downto 0); stopbit : in std_logic; clk : in std_logic); end component; signal baud_cnt : std_logic_vector(15 downto 0) := (others => '0'); signal baud_clk : std_logic := '0'; signal wr_txdata : std_logic; signal rd_rxdata : std_logic; signal rd : std_logic; signal wr : std_logic; signal rd1 : std_logic; signal wr1 : std_logic; signal rx_data : std_logic_vector(7 downto 0); signal rx_fifo_thresh : std_logic_vector(3 downto 0) := "0001";

88

signal rxirq_timer : std_logic_vector(7 downto 0); signal rx_rdy : std_logic; signal rx_ovr : std_logic; signal rx_perr : std_logic; signal rx_ferr : std_logic; signal rx_brk : std_logic; signal thre_s : std_logic; signal tsre_s : std_logic; signal rx_fifo_err : std_logic; signal rd_lsr : std_logic; signal tx_fifo_reset : std_logic; signal rx_fifo_reset : std_logic; signal rx_data_irq : std_logic; signal rx_line_irq : std_logic; signal rx_timeout_irq : std_logic; signal fifo_en_chg : std_logic := '0'; signal tx_irq : std_logic := '0'; signal clr_tx_irq : std_logic := '0'; signal msr_irq : std_logic := '0'; signal clr_msr_irq : std_logic := '0'; signal last_msr : std_logic_vector(3 downto 0) := "0000"; signal ri : std_logic; signal afe : std_logic; signal tx_enb : std_logic; signal load_dl : std_logic := '1'; signal ier : std_logic_vector(3 downto 0) := (others => '0'); signal iir : std_logic_vector(7 downto 0) := x"01"; signal fcr : std_logic_vector(7 downto 0) := (others => '0'); signal lcr : std_logic_vector(7 downto 0) := (others => '0'); signal mcr : std_logic_vector(7 downto 0) := (others => '0'); signal lsr : std_logic_vector(7 downto 0) := (others => '0'); signal msr : std_logic_vector(7 downto 0) := (others => '0'); signal scr : std_logic_vector(7 downto 0) := (others => '0'); signal dl : std_logic_vector(15 downto 0) := (others => '0'); begin wr_txdata <= '1' when cs='1' and wr1='0' and wr='1' and lcr(7)='0' and addr(2 downto 0)="000" else '0'; rd_rxdata <= '1' when cs='1' and rd1='0' and rd='1' and lcr(7)='0' and addr(2 downto 0)="000" else '0'; rd_lsr <= '1' when cs='1' and rd1='0' and rd='1' and addr(2 downto 0)="101" else '0';

89

iir(0) <= '0' when rx_data_irq='1' or rx_line_irq='1' or rx_timeout_irq='1' or tx_irq='1' or msr_irq='1' else '1'; iir(3 downto 1) <= "011" when rx_line_irq='1' else "010" when rx_data_irq='1' else "110" when rx_timeout_irq='1' else "001" when tx_irq='1' else "000"; iir(7 downto 6) <= "11" when fcr(0)='1' else "00"; lsr(0) <= rx_rdy; lsr(1) <= rx_ovr; lsr(2) <= rx_perr; lsr(3) <= rx_ferr; lsr(4) <= rx_brk; lsr(5) <= thre_s; lsr(6) <= tsre_s; lsr(7) <= rx_fifo_err; thre <= thre_s; tsre <= tsre_s; nDTR <= not mcr(0); nRTS <= not mcr(1); TxENB485 <= tx_enb; afe <= mcr(5); OUT1 <= mcr(2); OUT2 <= mcr(3); transmit: uart_tx port map ( data => data_in, we => wr_txdata, reset => reset, fifo_reset => tx_fifo_reset, baud_clk => baud_clk, txd => TxD, thre => thre_s, tsre => tsre_s, tx_irq => tx_irq, tx_enb => tx_enb, clr_irq => clr_tx_irq, fifo_en => fcr(0), parity_en => lcr(3),

90

parity_evn => lcr(4), parity_stick => lcr(5), chrlen => lcr(1 downto 0), stopbit => lcr(2), afe => afe, cts => msr(4), clk => clk); receive: uart_rx port map ( rxd => RxD, rx_data_irq => rx_data_irq, rx_timeout_irq => rx_timeout_irq, data => rx_data, rd => rd_rxdata, clr_err => rd_lsr, reset => reset, fifo_reset => rx_fifo_reset, fifo_err => rx_fifo_err, baud_clk => baud_clk, rx_rdy => rx_rdy, rx_ovr => rx_ovr, rx_perr => rx_perr, rx_ferr => rx_ferr, rx_brk => rx_brk, fifo_thresh => rx_fifo_thresh, parity_en => lcr(3), parity_evn => lcr(4), parity_stick => lcr(5), chrlen => lcr(1 downto 0), stopbit => lcr(2), clk => clk); cmd_gen : process(clk) begin if rising_edge(clk) then rd <= not rd_n; wr <= not wr_n; rd1 <= rd; wr1 <= wr; end if;

91

end process; irq_gen : process(clk) begin if rising_edge(clk) then rx_line_irq <= rx_perr or rx_ferr or rx_ovr or rx_fifo_err; if ((rx_data_irq='1' or rx_timeout_irq='1') and ier(0)='1') or (tx_irq='1' and ier(1)='1') or (rx_line_irq='1' and ier(2)='1') or (msr_irq='1' and ier(3)='1') then IRQ <= '1'; else IRQ <= '0'; end if; end if; end process; baud_gen : process(clk) begin if rising_edge(clk) then if baud_cnt=dl or load_dl='1' then baud_cnt <= x"0001"; baud_clk <= '1'; else baud_cnt <= baud_cnt + 1; baud_clk <= '0'; end if; end if; end process; -- register write operation write_reg : process(reset, clk) begin if reset='1' then rxirq_timer <= (others => '0'); ier <= (others => '0'); fcr <= (others => '0'); lcr <= (others => '0'); mcr <= (others => '0'); rx_fifo_thresh <= "0001";

92

load_dl <= '1'; tx_fifo_reset <= '1'; rx_fifo_reset <= '1'; elsif rising_edge(clk) then load_dl <= '0'; tx_fifo_reset <= '0'; rx_fifo_reset <= '0'; if fcr(0)='0' then -- fifo disabled rx_fifo_thresh <= "0001"; else case fcr(7 downto 6) is when "00" => rx_fifo_thresh <= "0001"; when "01" => rx_fifo_thresh <= "0100"; when "10" => rx_fifo_thresh <= "1000"; when "11" => rx_fifo_thresh <= "1110"; when others => null; end case; end if; if cs='1' and wr1='0' and wr='1' then case addr(2 downto 0) is when "000" => if lcr(7)='1' then dl(7 downto 0) <= data_in; load_dl <= '1'; end if; when "001" => if lcr(7)='1' then dl(15 downto 8) <= data_in; load_dl <= '1'; else ier <= data_in(3 downto 0); end if; when "010" => tx_fifo_reset <= (fcr(0) xor data_in(0)) or data_in(2); rx_fifo_reset <= (fcr(0) xor data_in(0)) or data_in(1); fcr <= data_in(7 downto 3) & "00" & data_in(0); when "011" => lcr <= data_in; when "100" => mcr <= data_in;

93

when "111" => scr <= data_in; when others => null; end case; end if; end if; end process; -- register read operation read_reg : process(clk) begin if rising_edge(clk) then if reset='1' then last_msr <= msr(7 downto 4); end if; clr_tx_irq <= '0'; clr_msr_irq <= '0'; if cs='1' and rd1='0' and rd='1' then case addr(2 downto 0) is when "000" => if lcr(7)='1' then data_out <= dl(7 downto 0); else data_out <= rx_data; end if; when "001" => if lcr(7)='1' then data_out <= dl(15 downto 8); else data_out <= "0000" & ier; end if; when "010" => data_out <= iir; if iir(3 downto 1)="001" then clr_tx_irq <= '1'; end if; when "011" => data_out <= lcr; when "100" => data_out <= mcr; when "101" => data_out <= lsr; when "110" => data_out <= msr;

94

clr_msr_irq <= '1'; last_msr <= msr(7 downto 4); when "111" => data_out <= scr; when others => null; end case; end if; end if; end process; modem_proc : process(clk) begin if rising_edge(clk) then if mcr(4)='1' then -- loop mode msr(4) <= mcr(1); -- RTS -> CTS msr(5) <= mcr(0); -- DTR -> DSR msr(6) <= mcr(2); -- OUT1 -> RI msr(7) <= mcr(3); -- OUT2 -> DCD else msr(4) <= not nCTS; msr(5) <= not nDSR; msr(6) <= ri; msr(7) <= not nDCD; end if; ri <= not nRI; msr(0) <= not afe and (last_msr(0) xor msr(4)); -- delta cts msr(1) <= last_msr(1) xor msr(5); -- delta dsr if clr_msr_irq='1' then msr(2) <= '0'; elsif ri='1' and msr(6)='0' then msr(2) <= '1'; -- ri edge end if; msr(3) <= last_msr(3) xor msr(7); -- delta dcd if msr(3 downto 0)/="0000" then msr_irq <= '1'; else msr_irq <= '0'; end if; end if; end process; end rtl;

95

２-１１-５intr_cont.vhd --Interrupt controller library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity irqcont is port ( CKIO : in std_logic; SD_in : in std_logic_vector(31 downto 0); SD_out : out std_logic_vector(31 downto 0); SA : in std_logic_vector(4 downto 0); EXT_SIRQ : in std_logic_vector(15 downto 3); UART_IRQ : in std_logic_vector(7 downto 0); CF_IRQ : in std_logic; nIRL : out std_logic_vector(7 downto 4); CS : in std_logic; nRD : in std_logic; WR : in std_logic; reset : in std_logic); end irqcont; architecture irqcont_arch of irqcont is signal intmask : std_logic_vector(23 downto 0) := (others => '1'); signal irq : std_logic_vector(15 downto 0) := (others => '0'); signal irq0 : std_logic_vector(15 downto 0) := (others => '1'); signal irq1 : std_logic_vector(15 downto 0) := (others => '1'); signal irq2 : std_logic_vector(15 downto 0) := (others => '1'); signal irq_out : std_logic_vector(23 downto 0) := (others => '0'); signal irq_ack : std_logic_vector(15 downto 0) := (others => '0'); signal irq_mode : std_logic_vector(31 downto 0) := (others => '0'); signal irq_edge : std_logic_vector(15 downto 0); signal irq_pol : std_logic_vector(15 downto 0); signal intevt : std_logic_vector(15 downto 0) := x"0000"; signal intevt_latch : std_logic_vector(15 downto 0) := x"0000"; signal intmaskcs : std_logic; signal intmaskclrcs : std_logic; signal irqackcs : std_logic; signal irqmodecs : std_logic;

96

signal intevtcs : std_logic; signal wr1 : std_logic; begin irqmodecs <= '1' when CS='1' and SA(4 downto 2)="000" else '0'; intmaskcs <= '1' when CS='1' and SA(4 downto 2)="001" else '0'; intmaskclrcs <= '1' when CS='1' and SA(4 downto 2)="010" else '0'; irqackcs <= '1' when CS='1' and SA(4 downto 2)="011" else '0'; intevtcs <= '1' when CS='1' and SA(4 downto 2)="100" else '0'; SD_out <= irq_mode when irqmodecs='1' else x"00" & intmask when intmaskcs='1' else x"00" & irq_out when irqackcs='1' else x"0000" & intevt_latch when intevtcs='1' else x"00000000"; process (reset, CKIO) begin if reset='1' then irq_ack <= (others => '0'); intmask <= (others => '1'); irq_mode <= (others => '0'); wr1 <= '0'; elsif rising_edge(CKIO) then wr1 <= WR; irq_ack <= (others => '0'); if WR='1' and wr1='0' and intmaskcs='1' then intmask <= SD_in(23 downto 0); end if; if WR='1' and wr1='0' and irqmodecs='1' then irq_mode <= SD_in; end if; if WR='1' and wr1='0' and irqackcs='1' then for i in 15 downto 3 loop if SD_in(i)='1' then irq_ack(i) <= '1'; end if; end loop;

97

end if; end if; end process; irq_edge <= not (irq_mode(31) & irq_mode(29) & irq_mode(27) & irq_mode(25) & irq_mode(23) & irq_mode(21) & irq_mode(19) & irq_mode(17) & irq_mode(15) & irq_mode(13) & irq_mode(11) & irq_mode(9) & irq_mode(7) & irq_mode(5) & irq_mode(3) & irq_mode(1)); irq_pol <= (irq_mode(30) & irq_mode(28) & irq_mode(26) & irq_mode(24) & irq_mode(22) & irq_mode(20) & irq_mode(18) & irq_mode(16) & irq_mode(14) & irq_mode(12) & irq_mode(10) & irq_mode(8) & irq_mode(6) & irq_mode(4) & irq_mode(2) & irq_mode(0)); process (reset, CKIO) begin if reset='1' then irq <= (others => '0'); irq0(15 downto 3) <= EXT_SIRQ(15 downto 3); irq1 <= (others => '1'); irq2 <= (others => '1'); irq_out <= (others => '0'); elsif rising_edge(CKIO) then irq0(15 downto 3) <= EXT_SIRQ(15 downto 3); irq1 <= irq0; irq2 <= irq1; irq_out(15 downto 0) <= (not intmask(15 downto 0)) and irq; irq_out(23 downto 16) <= (not intmask(23 downto 16)) and UART_IRQ(7 downto 0); irq <= irq and ((not irq_ack) or (not irq_edge)); for n in 15 downto 3 loop if irq_edge(n)='1' and irq_ack(n)='1' then irq(n) <= '0'; elsif irq_edge(n)='1' and irq_pol(n)='0' then -- falling edge if irq2(n)='1' and irq1(n)='0' then irq(n) <= '1'; end if; elsif irq_edge(n)='1' and irq_pol(n)='1' then -- rising edge

98

if irq2(n)='0' and irq1(n)='1' then irq(n) <= '1'; end if; elsif irq_edge(n)='0' then -- level trigger irq(n) <= irq2(n) xor (not irq_pol(n)); end if; end loop; end if; end process; nIRL(4) <= '0' when CF_IRQ='1' else '1'; nIRL(5) <= '0' when irq_out(15 downto 3)/=0 else '1'; nIRL(6) <= '0' when UART_IRQ/=0 else '1'; nIRL(7) <= '1'; intevt(7 downto 0) <= x"03" when irq_out(3) = '1' else -- EXT SIRQ3 x"04" when irq_out(4) = '1' else -- EXT SIRQ4 x"05" when irq_out(5) = '1' else -- EXT SIRQ5 x"06" when irq_out(6) = '1' else -- EXT SIRQ6 x"07" when irq_out(7) = '1' else -- EXT SIRQ7 x"09" when irq_out(9) = '1' else -- EXT SIRQ9 x"0a" when irq_out(10) = '1' else -- EXT SIRQ10 x"0b" when irq_out(11) = '1' else -- EXT SIRQ11 x"0c" when irq_out(12) = '1' else -- EXT SIRQ12 x"0e" when irq_out(14) = '1' else -- EXT SIRQ14 x"0f" when irq_out(15) = '1' else -- EXT SIRQ15 x"00"; intevt(15 downto 8) <= x"80" when irq_out(16) = '1' else -- UART0 x"81" when irq_out(17) = '1' else -- UART1 x"82" when irq_out(18) = '1' else -- UART2 x"83" when irq_out(19) = '1' else -- UART3 x"84" when irq_out(20) = '1' else -- UART4 x"85" when irq_out(21) = '1' else -- UART5 x"86" when irq_out(22) = '1' else -- UART6 x"87" when irq_out(23) = '1' else -- UART7 x"00"; process (CKIO)

99

begin if nRD='1' or intevtcs='0' then intevt_latch <= intevt; end if; end process; end irqcont_arch;

２-１１-６adc.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity adc is port ( SDI : out std_logic; SDO : in std_logic; SCK : out std_logic; START : out std_logic; nBUSY : in std_logic; nRD : out std_logic; addr : in std_logic_vector(7 downto 0); -- system address bus sd_in : in std_logic_vector(15 downto 0); -- system data bus sd_out : out std_logic_vector(15 downto 0); -- system data bus cs : in std_logic; -- chip select rd : in std_logic; -- read pulse (1 clk) wr : in std_logic_vector(1 downto 0); -- write pulse (1 clk) clk : in std_logic; -- system clock (96MHz) reset : in std_logic); end adc; architecture rtl of adc is -- ctl_reg bit assign -- bit0-7:ch0, bit8-15:ch1, ... bit56-63:ch7 -- bit0 : 1=sleep -- bit1 : 1=nap -- bit2 : gain -- bit3 : uni -- bit4,5 : select

100

-- bit6 : odd sign -- bit7 : 0=differencial, 1=single ended -- case bit(1 downto 0) is -- when "00" => Power On -- when "10" => Nap -- when "-1" => Sleep -- case bit(3 downto 2) is -- when "00" => -5V to +5V -- when "01" => -10V to +10V -- when "10" => 0V to +5V -- when "11" => 0V to +10V -- case bit(7 downto 4) is -- when "0000" => +:0, -:1 -- when "0001" => +:2, -:3 -- when "0010" => +:4, -:5 -- when "0011" => +:6, -:7 -- when "0100" => +:1, -:0 -- when "0101" => +:3, -:2 -- when "0110" => +:5, -:4 -- when "0111" => +:7, -:6 -- when "1000" => +:0, -:com -- when "1001" => +:2, -:com -- when "1010" => +:4, -:com -- when "1011" => +:6, -:com -- when "1100" => +:1, -:com -- when "1101" => +:3, -:com -- when "1110" => +:5, -:com -- when "1111" => +:7, -:com constant init_ctl_reg : std_logic_vector(63 downto 0) := x"88c898d8a8e8b8f8"; -- single ended, 0V to +5V signal status : std_logic_vector(7 downto 0) := (others => '0'); signal bitcnt : std_logic_vector(6 downto 0) := (others => '0'); signal ctl_reg : std_logic_vector(63 downto 0) := init_ctl_reg; signal out_reg : std_logic_vector(63 downto 0) := (others => '0'); signal in_reg : std_logic_vector(127 downto 0); signal val : std_logic_vector(127 downto 0); signal clk_div : std_logic_vector(1 downto 0) := (others => '0'); signal busy_s : std_logic_vector(1 downto 0) := (others => '0');

101

signal sdo_s : std_logic_vector(1 downto 0) := (others => '0'); signal ad_start : std_logic := '1'; signal settle_cnt : std_logic_vector(5 downto 0) := (others => '0'); type adc_st_type is (st_idle, st_start, st_wait_settling, st_wait_busy, st_wait_rdy, st_tfer_1, st_tfer_2, st_tfer_3); signal st : adc_st_type := st_start; begin nRD <= '0'; process(clk) begin if rising_edge(clk) then if reset='1' then ad_start <= '1'; ctl_reg <= init_ctl_reg; sd_out <= (others => '0'); end if; if cs='1' and wr(0)='1' then case addr(7 downto 4) is when "0000" => ctl_reg(63 downto 56) <= sd_in(7 downto 0); -- CH 0 when "0001" => ctl_reg(55 downto 48) <= sd_in(7 downto 0); -- CH 1 when "0010" => ctl_reg(47 downto 40) <= sd_in(7 downto 0); -- CH 2 when "0011" => ctl_reg(39 downto 32) <= sd_in(7 downto 0); -- CH 3 when "0100" => ctl_reg(31 downto 24) <= sd_in(7 downto 0); -- CH 4 when "0101" => ctl_reg(23 downto 16) <= sd_in(7 downto 0); -- CH 5 when "0110" => ctl_reg(15 downto 8) <= sd_in(7 downto 0); -- CH 6 when "0111" => ctl_reg( 7 downto 0) <= sd_in(7 downto 0); -- CH 7 when "1000" => ad_start <= sd_in(0); when others => null; end case; end if; if cs='1' and rd='1' then case addr(7 downto 4) is when "0000" => sd_out <= ctl_reg(55 downto 48) & ctl_reg(63 downto 56); when "0001" => sd_out <= ctl_reg(39 downto 32) & ctl_reg(47 downto 40); when "0010" => sd_out <= ctl_reg(23 downto 16) & ctl_reg(31 downto 24); when "0011" => sd_out <= ctl_reg( 7 downto 0) & ctl_reg(15 downto 8); when "0100" => sd_out <= "000000000000000" & ad_start; when "1000" => sd_out <= val(127 downto 112); when "1001" => sd_out <= val(111 downto 96); when "1010" => sd_out <= val(95 downto 80);

102

when "1011" => sd_out <= val(79 downto 64); when "1100" => sd_out <= val(63 downto 48); when "1101" => sd_out <= val(47 downto 32); when "1110" => sd_out <= val(31 downto 16); when "1111" => sd_out <= val(15 downto 0); when others => null; end case; end if; end if; end process; process(clk) begin if rising_edge(clk) then clk_div <= clk_div + 1; busy_s <= busy_s(0) & not nBUSY; sdo_s <= sdo_s(0) & SDO; if reset='1' then START <= '0'; SCK <= '0'; SDI <= '0'; clk_div <= (others => '0'); bitcnt <= (others => '0'); out_reg <= ctl_reg; in_reg <= (others => '0'); val <= (others => '0'); st <= st_idle; elsif clk_div=0 then settle_cnt <= settle_cnt + 1; case st is when st_idle => START <= '0'; SCK <= '0'; SDI <= '0'; bitcnt <= (others => '0'); if ad_start='1' then st <= st_start; end if; when st_start => if bitcnt(6 downto 4)="000" then

103

val <= in_reg(111 downto 0) & in_reg(127 downto 112); out_reg <= ctl_reg; end if; st <= st_wait_settling; settle_cnt <= (others => '0'); when st_wait_settling => if settle_cnt="111111" then START <= '1'; st <= st_wait_busy; end if; when st_wait_busy => if busy_s(1)='1' then st <= st_wait_rdy; end if; when st_wait_rdy => START <= '0'; if busy_s(1)='0' then st <= st_tfer_1; end if; when st_tfer_1 => if bitcnt(3)='0' then SDI <= out_reg(63); out_reg(63 downto 1) <= out_reg(62 downto 0); else SDI <= '0'; end if; st <= st_tfer_2; when st_tfer_2 => SCK <= '1'; st <= st_tfer_3; when st_tfer_3 => SCK <= '0'; in_reg <= in_reg(126 downto 0) & sdo_s(1); if bitcnt(3 downto 0)="1111" then if ad_start='1' then st <= st_start; else st <= st_idle; end if; else

104

st <= st_tfer_1; end if; bitcnt <= bitcnt + 1; when others => st <= st_idle; end case; end if; end if; end process; end rtl;

２-１１-７i2c.vhd library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- address dir description -- 0 w bit set (bit0:SDA, bit1:SCL) -- 1 w bit clear (bit0:SDA, bit1:SCL) -- 0 r bit read (bit0:SDA, bit1:SCL) entity i2c is port ( SDA : inout std_logic; SCL : inout std_logic; -- minimum period = 2.5us data_in : in std_logic_vector(15 downto 0); -- system data bus data_out : out std_logic_vector(7 downto 0); -- system data bus cs : in std_logic; -- chip select wr : in std_logic_vector(1 downto 0); -- write pulse (1 clk) clk : in std_logic; -- system clock reset : in std_logic); -- system reset end i2c; architecture rtl of i2c is signal sda_in : std_logic; signal sda_out : std_logic := '1'; signal scl_in : std_logic; signal scl_out : std_logic := '1'; begin

105

data_out(7 downto 0) <= "000000" & scl_in & sda_in; sda_in <= SDA; scl_in <= SCL; SDA <= '0' when sda_out='0' else 'Z'; SCL <= '0' when scl_out='0' else 'Z'; process(clk) begin if rising_edge(clk) then if reset='1' then sda_out <= '1'; scl_out <= '1'; else if cs='1' and wr(0)='1' then if data_in(0)='1' then sda_out <= '1'; end if; if data_in(1)='1' then scl_out <= '1'; end if; end if; if cs='1' and wr(1)='1' then if data_in(8)='1' then sda_out <= '0'; end if; if data_in(9)='1' then scl_out <= '0'; end if; end if; end if; end if; end process; end rtl;

２-１１-８sh2009.ucf NET "CKIO" PERIOD = 10 ns;

106

NET "SD<*>" SLEW = "FAST"; NET "CPU_RDY" SLEW = "FAST"; NET "nCPU_IOIS16" SLEW = "FAST"; NET "nRESET_OUT" PULLUP; NET "DIPSW<*>" PULLUP; NET "SD<*>" DRIVE = 4; NET "CPU_RDY" DRIVE = 8; NET "nCPU_IOIS16" DRIVE = 4; NET "nCPU_DRQ0" DRIVE = 4; NET "nCPU_DRQ1" DRIVE = 4; NET "CD<*>" DRIVE = 4; NET "CA<*>" DRIVE = 4; NET "nCFCE1" DRIVE = 4; NET "nCFCE2" DRIVE = 4; NET "nCFMRD" DRIVE = 4; NET "nCFMWR" DRIVE = 4; NET "nCFIORD" DRIVE = 4; NET "nCFIOWR" DRIVE = 4; NET "CFRESET" DRIVE = 4; NET "nREG" DRIVE = 4; NET "nVCCD1" DRIVE = 4; NET "RD_nWR" DRIVE = 4; ##### CPU NET "CKIO" IOSTANDARD = LVTTL; NET "CPU_RDY" IOSTANDARD = LVTTL; NET "CPU_RD_nWR" IOSTANDARD = LVTTL; NET "nCPU_BS" IOSTANDARD = LVTTL; NET "nCPU_CE1A" IOSTANDARD = LVTTL; NET "nCPU_CE1B" IOSTANDARD = LVTTL; NET "nCPU_CE2A" IOSTANDARD = LVTTL; NET "nCPU_CE2B" IOSTANDARD = LVTTL; NET "nCPU_CS1" IOSTANDARD = LVTTL; NET "nCPU_CS2" IOSTANDARD = LVTTL; NET "nCPU_CS4" IOSTANDARD = LVTTL; NET "nCPU_DACK0" IOSTANDARD = LVTTL; NET "nCPU_DACK1" IOSTANDARD = LVTTL; NET "nCPU_DRQ0" IOSTANDARD = LVTTL;

107

NET "nCPU_DRQ1" IOSTANDARD = LVTTL; NET "nCPU_IOIS16" IOSTANDARD = LVTTL; NET "nCPU_IORD" IOSTANDARD = LVTTL; NET "nCPU_IOWR" IOSTANDARD = LVTTL; NET "nCPU_RD" IOSTANDARD = LVTTL; NET "nCPU_WE0" IOSTANDARD = LVTTL; NET "nCPU_WE1" IOSTANDARD = LVTTL; NET "nIRL<4>" IOSTANDARD = LVTTL; NET "nIRL<5>" IOSTANDARD = LVTTL; NET "nIRL<6>" IOSTANDARD = LVTTL; NET "nIRL<7>" IOSTANDARD = LVTTL; NET "SA<0>" IOSTANDARD = LVTTL; NET "SA<1>" IOSTANDARD = LVTTL; NET "SA<2>" IOSTANDARD = LVTTL; NET "SA<3>" IOSTANDARD = LVTTL; NET "SA<4>" IOSTANDARD = LVTTL; NET "SA<5>" IOSTANDARD = LVTTL; NET "SA<6>" IOSTANDARD = LVTTL; NET "SA<7>" IOSTANDARD = LVTTL; NET "SA<8>" IOSTANDARD = LVTTL; NET "SA<9>" IOSTANDARD = LVTTL; NET "SA<10>" IOSTANDARD = LVTTL; NET "SA<11>" IOSTANDARD = LVTTL; NET "SA<12>" IOSTANDARD = LVTTL; NET "SA<20>" IOSTANDARD = LVTTL; NET "SA<21>" IOSTANDARD = LVTTL; NET "SA<22>" IOSTANDARD = LVTTL; NET "SA<23>" IOSTANDARD = LVTTL; NET "SA<24>" IOSTANDARD = LVTTL; NET "SA<25>" IOSTANDARD = LVTTL; NET "SD<0>" IOSTANDARD = LVTTL; NET "SD<1>" IOSTANDARD = LVTTL; NET "SD<2>" IOSTANDARD = LVTTL; NET "SD<3>" IOSTANDARD = LVTTL; NET "SD<4>" IOSTANDARD = LVTTL; NET "SD<5>" IOSTANDARD = LVTTL; NET "SD<6>" IOSTANDARD = LVTTL;

108

NET "SD<7>" IOSTANDARD = LVTTL; NET "SD<8>" IOSTANDARD = LVTTL; NET "SD<9>" IOSTANDARD = LVTTL; NET "SD<10>" IOSTANDARD = LVTTL; NET "SD<11>" IOSTANDARD = LVTTL; NET "SD<12>" IOSTANDARD = LVTTL; NET "SD<13>" IOSTANDARD = LVTTL; NET "SD<14>" IOSTANDARD = LVTTL; NET "SD<15>" IOSTANDARD = LVTTL; NET "SD<16>" IOSTANDARD = LVTTL; NET "SD<17>" IOSTANDARD = LVTTL; NET "SD<18>" IOSTANDARD = LVTTL; NET "SD<19>" IOSTANDARD = LVTTL; NET "SD<20>" IOSTANDARD = LVTTL; NET "SD<21>" IOSTANDARD = LVTTL; NET "SD<22>" IOSTANDARD = LVTTL; NET "SD<23>" IOSTANDARD = LVTTL; NET "SD<24>" IOSTANDARD = LVTTL; NET "SD<25>" IOSTANDARD = LVTTL; NET "SD<26>" IOSTANDARD = LVTTL; NET "SD<27>" IOSTANDARD = LVTTL; NET "SD<28>" IOSTANDARD = LVTTL; NET "SD<29>" IOSTANDARD = LVTTL; NET "SD<30>" IOSTANDARD = LVTTL; NET "SD<31>" IOSTANDARD = LVTTL; ##### CF IF NET "CA<0>" IOSTANDARD = LVTTL; NET "CA<1>" IOSTANDARD = LVTTL; NET "CA<2>" IOSTANDARD = LVTTL; NET "CA<3>" IOSTANDARD = LVTTL; NET "CA<4>" IOSTANDARD = LVTTL; NET "CA<5>" IOSTANDARD = LVTTL; NET "CA<6>" IOSTANDARD = LVTTL; NET "CA<7>" IOSTANDARD = LVTTL; NET "CA<8>" IOSTANDARD = LVTTL; NET "CA<9>" IOSTANDARD = LVTTL; NET "CA<10>" IOSTANDARD = LVTTL; NET "CD<0>" IOSTANDARD = LVTTL; NET "CD<1>" IOSTANDARD = LVTTL;

109

NET "CD<2>" IOSTANDARD = LVTTL; NET "CD<3>" IOSTANDARD = LVTTL; NET "CD<4>" IOSTANDARD = LVTTL; NET "CD<5>" IOSTANDARD = LVTTL; NET "CD<6>" IOSTANDARD = LVTTL; NET "CD<7>" IOSTANDARD = LVTTL; NET "CD<8>" IOSTANDARD = LVTTL; NET "CD<9>" IOSTANDARD = LVTTL; NET "CD<10>" IOSTANDARD = LVTTL; NET "CD<11>" IOSTANDARD = LVTTL; NET "CD<12>" IOSTANDARD = LVTTL; NET "CD<13>" IOSTANDARD = LVTTL; NET "CD<14>" IOSTANDARD = LVTTL; NET "CD<15>" IOSTANDARD = LVTTL; NET "CFRESET" IOSTANDARD = LVTTL; NET "nCD1" IOSTANDARD = LVTTL; NET "nCD2" IOSTANDARD = LVTTL; NET "nCFCE1" IOSTANDARD = LVTTL; NET "nCFCE2" IOSTANDARD = LVTTL; NET "nCFIOIS16" IOSTANDARD = LVTTL; NET "nCFIORD" IOSTANDARD = LVTTL; NET "nCFIOWR" IOSTANDARD = LVTTL; NET "nCFIRQ" IOSTANDARD = LVTTL; NET "nCFMRD" IOSTANDARD = LVTTL; NET "nCFMWR" IOSTANDARD = LVTTL; NET "nCFSTSCHG" IOSTANDARD = LVTTL; NET "nCFWAIT" IOSTANDARD = LVTTL; NET "nVCCD1" IOSTANDARD = LVTTL; ##### Local BUS NET "RD_nWR" IOSTANDARD = LVTTL; NET "nIORD" IOSTANDARD = LVTTL; NET "nIOWR" IOSTANDARD = LVTTL; NET "nREG" IOSTANDARD = LVTTL; NET "nRESET" IOSTANDARD = LVTTL; NET "nRESET_OUT" IOSTANDARD = LVTTL; ##### PC-104 BUS NET "nXDEN" IOSTANDARD = LVTTL;

110

NET "nEXT_IORD" IOSTANDARD = LVTTL; NET "nEXT_IOWR" IOSTANDARD = LVTTL; NET "nEXT_MEMR" IOSTANDARD = LVTTL; NET "nEXT_MEMW" IOSTANDARD = LVTTL; NET "nEXT_SBHE" IOSTANDARD = LVTTL; NET "nEXT_SMEMR" IOSTANDARD = LVTTL; NET "nEXT_SMEMW" IOSTANDARD = LVTTL; NET "nEXT_IOIS16" IOSTANDARD = LVTTL; NET "EXT_AEN" IOSTANDARD = LVTTL; NET "EXT_BALE" IOSTANDARD = LVTTL; NET "EXT_IOCHRDY" IOSTANDARD = LVTTL; NET "EXT_OSC" IOSTANDARD = LVTTL; NET "EXT_SYSCLK" IOSTANDARD = LVTTL; NET "EXT_RESET" IOSTANDARD = LVTTL; NET "EXT_SIRQ<3>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<4>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<5>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<6>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<7>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<9>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<10>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<11>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<12>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<14>" IOSTANDARD = LVTTL; NET "EXT_SIRQ<15>" IOSTANDARD = LVTTL; NET "nEXT_DRQ0" IOSTANDARD = LVTTL; NET "nEXT_DRQ1" IOSTANDARD = LVTTL; NET "EXT_DACK0" IOSTANDARD = LVTTL; NET "EXT_DACK1" IOSTANDARD = LVTTL; NET "nEXT_NOWAIT" IOSTANDARD = LVTTL; ##### SERIAL NET "TxD<0>" IOSTANDARD = LVTTL; NET "TxD<1>" IOSTANDARD = LVTTL; NET "TxD<2>" IOSTANDARD = LVTTL; NET "TxD<3>" IOSTANDARD = LVTTL; NET "TxD<4>" IOSTANDARD = LVTTL; NET "TxD<5>" IOSTANDARD = LVTTL; NET "TxD<6>" IOSTANDARD = LVTTL; NET "TxD<7>" IOSTANDARD = LVTTL;

111

NET "RxD232<0>" IOSTANDARD = LVTTL; NET "RxD232<1>" IOSTANDARD = LVTTL; NET "RxD232<2>" IOSTANDARD = LVTTL; NET "RxD232<3>" IOSTANDARD = LVTTL; NET "RxD232<4>" IOSTANDARD = LVTTL; NET "RxD232<5>" IOSTANDARD = LVTTL; NET "RxD232<6>" IOSTANDARD = LVTTL; NET "RxD232<7>" IOSTANDARD = LVTTL; NET "RxD485<0>" IOSTANDARD = LVTTL; NET "RxD485<1>" IOSTANDARD = LVTTL; NET "RxD485<2>" IOSTANDARD = LVTTL; NET "RxD485<3>" IOSTANDARD = LVTTL; NET "RxD485<4>" IOSTANDARD = LVTTL; NET "RxD485<5>" IOSTANDARD = LVTTL; NET "RxD485<6>" IOSTANDARD = LVTTL; NET "RxD485<7>" IOSTANDARD = LVTTL; NET "Tx485ENB<0>" IOSTANDARD = LVTTL; NET "Tx485ENB<1>" IOSTANDARD = LVTTL; NET "Tx485ENB<2>" IOSTANDARD = LVTTL; NET "Tx485ENB<3>" IOSTANDARD = LVTTL; NET "Tx485ENB<4>" IOSTANDARD = LVTTL; NET "Tx485ENB<5>" IOSTANDARD = LVTTL; NET "Tx485ENB<6>" IOSTANDARD = LVTTL; NET "Tx485ENB<7>" IOSTANDARD = LVTTL; NET "nCTS<0>" IOSTANDARD = LVTTL; NET "nCTS<1>" IOSTANDARD = LVTTL; NET "nCTS<2>" IOSTANDARD = LVTTL; NET "nCTS<3>" IOSTANDARD = LVTTL; NET "nCTS<4>" IOSTANDARD = LVTTL; NET "nCTS<5>" IOSTANDARD = LVTTL; NET "nCTS<6>" IOSTANDARD = LVTTL; NET "nCTS<7>" IOSTANDARD = LVTTL; NET "nRTS<0>" IOSTANDARD = LVTTL; NET "nRTS<1>" IOSTANDARD = LVTTL; NET "nRTS<2>" IOSTANDARD = LVTTL; NET "nRTS<3>" IOSTANDARD = LVTTL; NET "nRTS<4>" IOSTANDARD = LVTTL; NET "nRTS<5>" IOSTANDARD = LVTTL; NET "nRTS<6>" IOSTANDARD = LVTTL; NET "nRTS<7>" IOSTANDARD = LVTTL;

112

NET "nDCD<0>" IOSTANDARD = LVTTL; NET "nDCD<1>" IOSTANDARD = LVTTL; NET "nDCD<2>" IOSTANDARD = LVTTL; NET "nDCD<3>" IOSTANDARD = LVTTL; NET "nDCD<4>" IOSTANDARD = LVTTL; NET "nDCD<5>" IOSTANDARD = LVTTL; NET "nDCD<6>" IOSTANDARD = LVTTL; NET "nDCD<7>" IOSTANDARD = LVTTL; NET "nDSR<0>" IOSTANDARD = LVTTL; NET "nDSR<1>" IOSTANDARD = LVTTL; NET "nDSR<2>" IOSTANDARD = LVTTL; NET "nDSR<3>" IOSTANDARD = LVTTL; NET "nDSR<4>" IOSTANDARD = LVTTL; NET "nDSR<5>" IOSTANDARD = LVTTL; NET "nDSR<6>" IOSTANDARD = LVTTL; NET "nDSR<7>" IOSTANDARD = LVTTL; NET "nRI<0>" IOSTANDARD = LVTTL; NET "nRI<1>" IOSTANDARD = LVTTL; NET "nRI<2>" IOSTANDARD = LVTTL; NET "nRI<3>" IOSTANDARD = LVTTL; NET "nRI<4>" IOSTANDARD = LVTTL; NET "nRI<5>" IOSTANDARD = LVTTL; NET "nRI<6>" IOSTANDARD = LVTTL; NET "nRI<7>" IOSTANDARD = LVTTL; NET "DIPSW<4>" IOSTANDARD = LVTTL; NET "DIPSW<5>" IOSTANDARD = LVTTL; NET "DIPSW<6>" IOSTANDARD = LVTTL; NET "DIPSW<7>" IOSTANDARD = LVTTL; ##### ADC NET "nADC_BUSY" IOSTANDARD = LVTTL; NET "nAD_RD" IOSTANDARD = LVTTL; NET "AD_START" IOSTANDARD = LVTTL; NET "ADC_SCK" IOSTANDARD = LVTTL; NET "ADC_SDI" IOSTANDARD = LVTTL; NET "ADC_SDO" IOSTANDARD = LVTTL; ##### I2C NET "SDA" IOSTANDARD = LVTTL;

113

NET "SCL" IOSTANDARD = LVTTL; NET "TMP00" IOSTANDARD = LVTTL; NET "DVI_nDVO" IOSTANDARD = LVTTL; ##### CPU NET "CKIO" LOC = A8; NET "CPU_RDY" LOC = A13; NET "CPU_RD_nWR" LOC = T4; NET "nCPU_BS" LOC = C7; NET "nCPU_CE1A" LOC = P16; NET "nCPU_CE1B" LOC = D14; NET "nCPU_CE2A" LOC = M13; NET "nCPU_CE2B" LOC = F9; NET "nCPU_CS1" LOC = T11; NET "nCPU_CS2" LOC = D13; NET "nCPU_CS4" LOC = B6; NET "nCPU_DACK0" LOC = N15; NET "nCPU_DACK1" LOC = G5; NET "nCPU_DRQ0" LOC = A6; NET "nCPU_DRQ1" LOC = A5; NET "nCPU_IOIS16" LOC = C17; NET "nCPU_IORD" LOC = F12; NET "nCPU_IOWR" LOC = A16; NET "nCPU_RD" LOC = H6; NET "nCPU_WE0" LOC = C8; NET "nCPU_WE1" LOC = D17; NET "nIRL<4>" LOC = F1; NET "nIRL<5>" LOC = J7; NET "nIRL<6>" LOC = F2; NET "nIRL<7>" LOC = J3; NET "SA<0>" LOC = H7; NET "SA<1>" LOC = G6; NET "SA<2>" LOC = D8; NET "SA<3>" LOC = F14; NET "SA<4>" LOC = N11; NET "SA<5>" LOC = P8;

114

NET "SA<6>" LOC = M9; NET "SA<7>" LOC = R10; NET "SA<8>" LOC = N10; NET "SA<9>" LOC = C18; NET "SA<10>" LOC = L7; NET "SA<11>" LOC = E12; NET "SA<12>" LOC = T10; NET "SA<20>" LOC = B9; NET "SA<21>" LOC = E13; NET "SA<22>" LOC = C14; NET "SA<23>" LOC = D10; NET "SA<24>" LOC = A15; NET "SA<25>" LOC = G11; NET "SD<0>" LOC = "V16"; NET "SD<1>" LOC = "U15"; NET "SD<2>" LOC = "V15"; NET "SD<3>" LOC = "R13"; NET "SD<4>" LOC = "V6"; NET "SD<5>" LOC = "U7"; NET "SD<6>" LOC = "T7"; NET "SD<7>" LOC = "R7"; NET "SD<8>" LOC = R5; NET "SD<9>" LOC = T8; NET "SD<10>" LOC = L2; NET "SD<11>" LOC = N3; NET "SD<12>" LOC = R1; NET "SD<13>" LOC = M2; NET "SD<14>" LOC = L3; NET "SD<15>" LOC = N6; NET "SD<16>" LOC = N8; NET "SD<17>" LOC = T6; NET "SD<18>" LOC = V4; NET "SD<19>" LOC = V5; NET "SD<20>" LOC = K3; NET "SD<21>" LOC = L1; NET "SD<22>" LOC = J1; NET "SD<23>" LOC = K2; NET "SD<24>" LOC = K5; NET "SD<25>" LOC = J4;

115

NET "SD<26>" LOC = P3; NET "SD<27>" LOC = N5; NET "SD<28>" LOC = C2; NET "SD<29>" LOC = R3; NET "SD<30>" LOC = N2; NET "SD<31>" LOC = P1; ##### CF IF NET "CA<0>" LOC = T17; NET "CA<1>" LOC = U13; NET "CA<2>" LOC = V14; NET "CA<3>" LOC = R17; NET "CA<4>" LOC = T18; NET "CA<5>" LOC = U18; NET "CA<6>" LOC = T15; NET "CA<7>" LOC = R14; NET "CA<8>" LOC = P12; NET "CA<9>" LOC = B18; NET "CA<10>" LOC = P10; NET "CD<0>" LOC = R11; NET "CD<1>" LOC = U4; NET "CD<2>" LOC = V13; NET "CD<3>" LOC = E9; NET "CD<4>" LOC = U1; NET "CD<5>" LOC = V11; NET "CD<6>" LOC = R9; NET "CD<7>" LOC = U10; NET "CD<8>" LOC = T5; NET "CD<9>" LOC = U6; NET "CD<10>" LOC = N1; NET "CD<11>" LOC = N4; NET "CD<12>" LOC = R2; NET "CD<13>" LOC = T1; NET "CD<14>" LOC = L4; NET "CD<15>" LOC = B1; NET "CFRESET" LOC = L13; NET "nCD1" LOC = L16; NET "nCD2" LOC = M15; NET "nCFCE1" LOC = U17; NET "nCFCE2" LOC = N16;

116

NET "nCFIOIS16" LOC = B16; NET "nCFIORD" LOC = H15; NET "nCFIOWR" LOC = F17; NET "nCFIRQ" LOC = N18; NET "nCFMRD" LOC = J17; NET "nCFMWR" LOC = E18; NET "nCFSTSCHG" LOC = D18; NET "nCFWAIT" LOC = D16; NET "nVCCD1" LOC = R16; ##### Local BUS NET "RD_nWR" LOC = C1; NET "nIORD" LOC = E7; NET "nIOWR" LOC = A3; NET "nREG" LOC = A14; NET "nRESET" LOC = P13; NET "nRESET_OUT" LOC = F8; ##### PC-104 BUS NET "nXDEN" LOC = C16; NET "nEXT_IORD" LOC = A11; NET "nEXT_IOWR" LOC = C13; NET "nEXT_MEMR" LOC = F11; NET "nEXT_MEMW" LOC = A10; NET "nEXT_SBHE" LOC = D9; NET "nEXT_SMEMR" LOC = E11; NET "nEXT_SMEMW" LOC = B11; NET "nEXT_IOIS16" LOC = B13; NET "EXT_AEN" LOC = J14; NET "EXT_BALE" LOC = B7; NET "EXT_IOCHRDY" LOC = B15; NET "EXT_OSC" LOC = D5; NET "EXT_SYSCLK" LOC = C9; NET "EXT_RESET" LOC = D3; NET "EXT_SIRQ<3>" LOC = L6; NET "EXT_SIRQ<4>" LOC = M6; NET "EXT_SIRQ<5>" LOC = M5; NET "EXT_SIRQ<6>" LOC = J2; NET "EXT_SIRQ<7>" LOC = H1;

117

NET "EXT_SIRQ<9>" LOC = G2; NET "EXT_SIRQ<10>" LOC = H3; NET "EXT_SIRQ<11>" LOC = K6; NET "EXT_SIRQ<12>" LOC = J5; NET "EXT_SIRQ<14>" LOC = G7; NET "EXT_SIRQ<15>" LOC = U2; NET "nEXT_DRQ0" LOC = M3; NET "nEXT_DRQ1" LOC = F13; NET "EXT_DACK0" LOC = M14; NET "EXT_DACK1" LOC = F5; NET "nEXT_NOWAIT" LOC = C11; ##### SERIAL NET "TxD<0>" LOC = D12; NET "TxD<1>" LOC = C12; NET "TxD<2>" LOC = F4; NET "TxD<3>" LOC = J6; NET "TxD<4>" LOC = K16; NET "TxD<5>" LOC = T2; NET "TxD<6>" LOC = N12; NET "TxD<7>" LOC = E1; NET "RxD232<0>" LOC = E15; NET "RxD232<1>" LOC = K17; NET "RxD232<2>" LOC = K12; NET "RxD232<3>" LOC = P7; NET "RxD232<4>" LOC = M17; NET "RxD232<5>" LOC = N14; NET "RxD232<6>" LOC = P14; NET "RxD232<7>" LOC = R6; NET "RxD485<0>" LOC = G13; NET "RxD485<1>" LOC = K15; NET "RxD485<2>" LOC = G16; NET "RxD485<3>" LOC = P9; NET "RxD485<4>" LOC = M16; NET "RxD485<5>" LOC = P15; NET "RxD485<6>" LOC = N7; NET "RxD485<7>" LOC = L18; NET "Tx485ENB<0>" LOC = B12; NET "Tx485ENB<1>" LOC = F15; NET "Tx485ENB<2>" LOC = E16;

118

NET "Tx485ENB<3>" LOC = T14; NET "Tx485ENB<4>" LOC = P18; NET "Tx485ENB<5>" LOC = T12; NET "Tx485ENB<6>" LOC = V8; NET "Tx485ENB<7>" LOC = F18; NET "nCTS<0>" LOC = G15; NET "nCTS<1>" LOC = J13; NET "nCTS<2>" LOC = H16; NET "nCTS<3>" LOC = L14; NET "nCTS<4>" LOC = K14; NET "nCTS<5>" LOC = P5; NET "nCTS<6>" LOC = M12; NET "nCTS<7>" LOC = H17; NET "nRTS<0>" LOC = B2; NET "nRTS<1>" LOC = L12; NET "nRTS<2>" LOC = G17; NET "nRTS<3>" LOC = V3; NET "nRTS<4>" LOC = N17; NET "nRTS<5>" LOC = U11; NET "nRTS<6>" LOC = U12; NET "nRTS<7>" LOC = R18; NET "nDCD<0>" LOC = M4; NET "nDCD<1>" LOC = G14; NET "nDCD<2>" LOC = U8; NET "nDCD<3>" LOC = U9; NET "nDCD<4>" LOC = K13; NET "nDCD<5>" LOC = H2; NET "nDCD<6>" LOC = M8; NET "nDCD<7>" LOC = V9; NET "nDSR<0>" LOC = H12; NET "nDSR<1>" LOC = H13; NET "nDSR<2>" LOC = J16; NET "nDSR<3>" LOC = P6; NET "nDSR<4>" LOC = K18; NET "nDSR<5>" LOC = P4; NET "nDSR<6>" LOC = M11; NET "nDSR<7>" LOC = H18; NET "nRI<0>" LOC = G9; NET "nRI<1>" LOC = F16; NET "nRI<2>" LOC = D1;

119

NET "nRI<3>" LOC = G4; NET "nRI<4>" LOC = L17; NET "nRI<5>" LOC = G3; NET "nRI<6>" LOC = N9; NET "nRI<7>" LOC = F3; NET "DIPSW<4>" LOC = F10; NET "DIPSW<5>" LOC = E10; NET "DIPSW<6>" LOC = H5; NET "DIPSW<7>" LOC = B8; ##### ADC NET "nADC_BUSY" LOC = G8; NET "nAD_RD" LOC = B4; NET "AD_START" LOC = C15; NET "ADC_SCK" LOC = A4; NET "ADC_SDI" LOC = C6; NET "ADC_SDO" LOC = F7; ##### I2C NET "SDA" LOC = C5; NET "SCL" LOC = D6; ### CF IRQ for TEST NET "DVI_nDVO" LOC = T3; NET "TMP00" LOC = T13;

120

３SH2009 の起動

本ボードに 5V±0.2V 出力電流 3A 以上の電源を接続します。 CN13 に付属の変換ケーブルを接続し、起動コンソールとして RS232C ターミナルをボーレート

115.2kbps、ノンパリティに設定し接続します。(WindowsPC と Teraterm などで OK です)

３-１-１ファーストライト

ディップ SW(SW2)を全て OFF にし、電源を入れると次のようなメッセージが表示されます。（説

明に使用している SH2009 は IO ボードに HDD も装着しています） ?コマンドを入力するとヘルプ（コマンド一覧）を表示します。

r コマンドでオンボード Flash ROM から sh-linux が起動します。

３-１-２ネットワーク・ユーザ名の出荷時設定

本ボードのオンボード Flash ROM では、次のように初期化してあります。 root のパスワード root 一般ユーザとしてユーザ名 shlinux が登録されています。初期パスワードも shlinux です。ネットワーク

eth0(CN8 側) 192.168.0.40/24 G ビット LAN 側です。 eth1(CN9 側) 192.168.9.40/24 100Mase-Tx 側です。ゲートウェイ 192.168.0.1

121

ネームサーバー 192.168.0.5 起動後、お使いの環境に合わせて修正してください。IP アドレスがコンフリクトしないなら、LAN

ケーブルを接続して起動してください。

３-１-３起動メッセージ

r コマンドでオンボード Flash ROM から sh-linux を起動 > rUncompressing Linux... Ok, booting the kernel. Linux version 2.6.29.4 ([email protected]) (gcc version 4.3.2 20081105 (Red Hat 4.3.2-7.1) (GCC) ) #57 Wed Jun 3 10:13:02 JST 2009 Boot params: ... MOUNT_ROOT_RDONLY - 00000000 ... RAMDISK_FLAGS - 00000000 ... ORIG_ROOT_DEV - 00000000 ... LOADER_TYPE - 00000000 ... INITRD_START - 00000000 ... INITRD_SIZE - 00000000 console [sercon0] enabled Booting machvec: sh2009 SH-2009 Setup...done. Node 0: start_pfn = 0x20000, low = 0x30000 Zone PFN ranges: Normal 0x00020000 -> 0x00030000 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x00020000 -> 0x00030000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65280 Kernel command line: mem=512M console=ttySC1,115200 ubi.mtd=4 root=ubi0:rootfs ro rootfstype=ubifs earlyprintk=serial Setting GDB trap vector to 0xe55f0100 PID hash table entries: 2048 (order: 11, 8192 bytes) Using tmu for system timer Using 12.500 MHz high precision timer. Console: colour dummy device 80x25 Dentry cache hash table entries: 65536 (order: 5, 262144 bytes) Inode-cache hash table entries: 32768 (order: 4, 131072 bytes) Memory: 515328k/524288k available (3801k kernel code, 1327k data, 184k init) PVR=10300700 CVR=71440211 PRR=00000250 I-cache : n_ways=4 n_sets=256 way_incr=8192 I-cache : entry_mask=0x00001fe0 alias_mask=0x00000000 n_aliases=1 D-cache : n_ways=4 n_sets=256 way_incr=8192 D-cache : entry_mask=0x00001fe0 alias_mask=0x00000000 n_aliases=1 Calibrating delay loop (skipped)... 600.00 BogoMIPS PRESET (lpj=3000000) Security Framework initialized SELinux: Initializing. Mount-cache hash table entries: 1024 CPU: SH7785 net_namespace: 1000 bytes PCI: Using configuration type 1 NET: Registered protocol family 16 io_init: misc_base=c0100200 uart_base=c0108200 io_init: pc104_mem_base=c0200000 pc104_fast_mem_base=c0700000 io_init: pc104_io_base=c0120000 pc104_fast_io_base=c0140000 bio: create slab <bio-0> at 0 SCSI subsystem initialized

122

usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb Autoconfig PCI channel 0x804fd724 Scanning bus 00, I/O 0xfe200000:0xfe400000, Mem 0xfd000000:0xfe000000 00:00.0 Class 0c03: 1033:0035 (rev 43) Mem at 0xfd000000 [size=0x1000] 00:00.1 Class 0c03: 1033:0035 (rev 43) Mem at 0xfd001000 [size=0x1000] 00:00.2 Class 0c03: 1033:00e0 (rev 04) Mem at 0xfd002000 [size=0x100] 00:01.0 Class 0300: 18ca:0020 Mem unavailable -- skipping, value fe000000 size 2000000 Mem at 0xfd040000 [size=0x40000] I/O at 0xfe200000 [size=0x80] 00:02.0 Class 0200: 8086:1078 (rev 05) Mem at 0xfd080000 [size=0x20000] I/O at 0xfe200080 [size=0x40] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot pci 0000:00:00.0: PME# disabled pci 0000:00:00.1: PME# supported from D0 D1 D2 D3hot pci 0000:00:00.1: PME# disabled pci 0000:00:00.2: PME# supported from D0 D1 D2 D3hot pci 0000:00:00.2: PME# disabled SH-3/4A Embedded PCMCIA Interface polling interval = 1000 ms interrupt = 10 NET: Registered protocol family 2 IP route cache hash table entries: 4096 (order: 1, 16384 bytes) TCP established hash table entries: 16384 (order: 4, 131072 bytes) TCP bind hash table entries: 16384 (order: 5, 327680 bytes) TCP: Hash tables configured (established 16384 bind 16384) TCP reno registered NET: Registered protocol family 1 attach [client=pcf8563] i2c-pio i2c-pio.0: adapter registered audit: initializing netlink socket (disabled) type=2000 audit(946684800.499:1): initialized VFS: Disk quotas dquot_6.5.2 Dquot-cache hash table entries: 2048 (order 0, 8192 bytes) msgmni has been set to 1007 alg: No test for stdrng (krng) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) XGIfb: Options <NULL> XGIfb: Relocate IO address: fe200000 [fe200030] XGIfb: Video ROM usage disabled XGIfb:VGA init()....XGIfb: SR14=51 DramSzie 2000000 ChannelNum 1 XGIfb: Framebuffer at 0xc0000000, mapped to 0xd0d00000, size 32768k XGIfb: MMIO at 0xfd040000, mapped to 0xfd040000, size 256k OK XGIfb: Memory heap starting at 13312K XGIfb: Using MMIO queue mode XGIfb: No or unknown bridge type detected XGIfb: Default mode is 800x600x16 (60Hz)

123

Console: switching to colour frame buffer device 100x37 XGIfb: Installed XGIFB_GET_INFO ioctl (80046ef8) fb0: frame buffer device, Version 0.8.00 Serial: 8250/16550 driver, 8 ports, IRQ sharing enabled serial8250.0: ttyS0 at MMIO 0x18000200 (irq = 14) is a 16550A serial8250.0: ttyS1 at MMIO 0x18000210 (irq = 14) is a 16550A serial8250.0: ttyS2 at MMIO 0x18000220 (irq = 14) is a 16550A serial8250.0: ttyS3 at MMIO 0x18000230 (irq = 14) is a 16550A serial8250.0: ttyS4 at MMIO 0x18000240 (irq = 14) is a 16550A serial8250.0: ttyS5 at MMIO 0x18000250 (irq = 14) is a 16550A serial8250.0: ttyS6 at MMIO 0x18000260 (irq = 14) is a 16550A serial8250.0: ttyS7 at MMIO 0x18000270 (irq = 14) is a 16550A SuperH SCI(F) driver initialized sh-sci: ttySC0 at MMIO 0xffea0000 (irq = 43) is a scif sh-sci: ttySC1 at MMIO 0xffeb0000 (irq = 47) is a scif console handover: boot [sercon0] -> real [ttySC1] sh-sci sh-sci: Attempting to register port 3 when only 2 are available. sh-sci sh-sci: Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS! brd: module loaded Intel(R) PRO/1000 Network Driver - version 7.3.21-k3-NAPI Copyright (c) 1999-2006 Intel Corporation. e1000: 0000:00:02.0: e1000_probe: (PCI:33MHz:32-bit) 00:10:0c:00:53:bf e1000: eth0: e1000_probe: Intel(R) PRO/1000 Network Connection smsc911x: Driver version 2008-10-21. smsc911x-mdio: probed eth1: attached PHY driver [Generic PHY] (mii_bus:phy_addr=0:01, irq=-1) net eth1: MAC Address: 00:10:0c:00:53:be Driver 'sd' needs updating - please use bus_type methods scsi0 : pata_platform ata1: PATA max PIO0 mmio cmd 0x1a800170 ctl 0x1a800376 irq 2 ata1.00: ATA-8: WDC WD1200BEVE-22WZT0, 01.01A01, max UDMA/100 ata1.00: 234441648 sectors, multi 0: LBA48 ata1.00: configured for PIO scsi 0:0:0:0: Direct-Access ATA WDC WD1200BEVE-2 01.0 PQ: 0 ANSI: 5 sd 0:0:0:0: [sda] 234441648 512-byte hardware sectors: (120 GB/111 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sd 0:0:0:0: [sda] 234441648 512-byte hardware sectors: (120 GB/111 GiB) sd 0:0:0:0: [sda] Write Protect is off sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA sda: sda1 sda2 sda3 sda4 sd 0:0:0:0: [sda] Attached SCSI disk sd 0:0:0:0: Attached scsi generic sg0 type 0 physmap platform flash device: 02000000 at 00000000 physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank Intel/Sharp Extended Query Table at 0x010A Intel/Sharp Extended Query Table at 0x010A Intel/Sharp Extended Query Table at 0x010A Intel/Sharp Extended Query Table at 0x010A Intel/Sharp Extended Query Table at 0x010A Using buffer write method Using auto-unlock on power-up/resume cfi_cmdset_0001: Erase suspend on write enabled cmdlinepart partition parsing not available RedBoot partition parsing not available Using physmap partition information Creating 4 MTD partitions on "physmap-flash.0":

124

0x000000000000-0x000000080000 : "ipl" 0x000000080000-0x0000000c0000 : "alternate fpga data" 0x0000000c0000-0x0000003c0000 : "kernel" 0x0000003c0000-0x000002000000 : "other" NAND device: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron NAND 1GiB 3,3V 8-bit) writesize=4KB erasesize=256KB oobsize=128Byte 2 NAND chips detected Scanning device for bad blocks NAND デバイスには不良ブロックが含まれています。 Bad eraseblock 60 at 0x000000f00000 不良ブロックの数は個体毎に増減があります。 Bad eraseblock 208 at 0x000003400000 Bad eraseblock 427 at 0x000006ac0000 Bad eraseblock 1132 at 0x000011b00000 Bad eraseblock 1490 at 0x000017480000 Bad eraseblock 2479 at 0x000026bc0000 Bad eraseblock 2606 at 0x000028b80000 Bad eraseblock 2733 at 0x00002ab40000 Bad eraseblock 2920 at 0x00002da00000 Bad eraseblock 2950 at 0x00002e180000 Bad eraseblock 3303 at 0x0000339c0000 Bad eraseblock 3835 at 0x00003bec0000 Bad eraseblock 3856 at 0x00003c400000 Bad eraseblock 3991 at 0x00003e5c0000 Bad eraseblock 4487 at 0x0000461c0000 Bad eraseblock 4508 at 0x000046700000 Bad eraseblock 5144 at 0x000050600000 Bad eraseblock 5564 at 0x000056f00000 Bad eraseblock 6241 at 0x000061840000 Bad eraseblock 6453 at 0x000064d40000 Bad eraseblock 7143 at 0x00006f9c0000 Bad eraseblock 7171 at 0x0000700c0000 Bad eraseblock 7507 at 0x0000754c0000 cmdlinepart partition parsing not available Creating 1 MTD partitions on "gen_nand": 0x000000000000-0x000080000000 : "nand-0" UBI: attaching mtd4 to ubi0 ROM のルートファイルシステムは UBIFS です。 UBI: physical eraseblock size: 262144 bytes (256 KiB) UBI: logical eraseblock size: 253952 bytes UBI: smallest flash I/O unit: 4096 UBI: VID header offset: 4096 (aligned 4096) UBI: data offset: 8192 UBI: attached mtd4 to ubi0 UBI: MTD device name: "nand-0" UBI: MTD device size: 2048 MiB UBI: number of good PEBs: 8169 UBI: number of bad PEBs: 23 UBI: max. allowed volumes: 128 UBI: wear-leveling threshold: 4096 UBI: number of internal volumes: 1 UBI: number of user volumes: 1 UBI: available PEBs: 0 UBI: total number of reserved PEBs: 8169 UBI: number of PEBs reserved for bad PEB handling: 81 UBI: max/mean erase counter: 5/1 UBI: background thread "ubi_bgt0d" started, PID 369 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci_hcd 0000:00:00.2: EHCI Host Controller ehci_hcd 0000:00:00.2: new USB bus registered, assigned bus number 1

125

ehci_hcd 0000:00:00.2: Enabling legacy PCI PM ehci_hcd 0000:00:00.2: irq 65, io mem 0xfd002000 ehci_hcd 0000:00:00.2: USB 2.0 started, EHCI 1.00 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 5 ports detected ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver ohci_hcd 0000:00:00.0: OHCI Host Controller ohci_hcd 0000:00:00.0: new USB bus registered, assigned bus number 2 ohci_hcd 0000:00:00.0: irq 65, io mem 0xfd000000 usb usb2: configuration #1 chosen from 1 choice hub 2-0:1.0: USB hub found hub 2-0:1.0: 3 ports detected ohci_hcd 0000:00:00.1: OHCI Host Controller ohci_hcd 0000:00:00.1: new USB bus registered, assigned bus number 3 ohci_hcd 0000:00:00.1: irq 65, io mem 0xfd001000 usb usb3: configuration #1 chosen from 1 choice hub 3-0:1.0: USB hub found hub 3-0:1.0: 2 ports detected mice: PS/2 mouse device common for all mice rtc-pcf8563 0-0051: chip found, driver version 0.4.3 rtc-pcf8563 0-0051: rtc core: registered rtc-pcf8563 as rtc0 usbcore: registered new interface driver hiddev usbcore: registered new interface driver usbhid usbhid: v2.6:USB HID core driver TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 17 RPC: Registered udp transport module. RPC: Registered tcp transport module. rtc-pcf8563 0-0051: setting system clock to 2009-06-05 18:04:33 UTC (1244225073) UBIFS: recovery needed UBIFS: recovery deferred UBIFS: mounted UBI device 0, volume 0, name "rootfs" UBIFS: mounted read-only UBIFS: file system size: 2049646592 bytes (2001608 KiB, 1954 MiB, 8071 LEBs) UBIFS: journal size: 33521664 bytes (32736 KiB, 31 MiB, 132 LEBs) UBIFS: media format: 4 (latest is 4) UBIFS: default compressor: lzo UBIFS: reserved for root: 5182151 bytes (5060 KiB) VFS: Mounted root (ubifs filesystem) readonly on device 252:1. Freeing unused kernel memor usb 2-1: new low speed USB device using ohci_hcd and address 2 Welcome to Fedora Press 'I' to enter interactive startup. Starting udev: [ OK ] Setting hostname sh2009n-rom.itonet.co.jp: [ OK ] Checking filesystems Checking all file systems. [ OK ] Remounting root filesystem in read-write mode: [ OK ] Mounting local filesystems: [ OK ] Enabling /etc/fstab swaps: [ OK ] Entering non-interactive startup Bringing up loopback interface: [ OK ] Bringing up interface eth0: [ OK ] Bringing up interface eth1: [ OK ] Starting rpcbind: [ OK ]

126

Starting NFS statd: [ OK ] Starting RPC idmapd: [ OK ] Mounting other filesystems: [ OK ] Starting system logger: [ OK ] Starting sshd: [ OK ] Starting xinetd: [ OK ] Fedora release 9 (Sulphur) Kernel 2.6.29.4 on an sh4 (/dev/ttySC1) sh2009n-rom.itonet.co.jp login: root ← root または shlinux で login できます。 Password: Last login: Fri Jun 5 09:47:59 on ttySC1 -bash-3.2#

DVI-I コネクタ(CN19)に 1280x1024 ピクセルが表示できるデジタル、またはアナログモニタを接

続し、USB 端子にキーボード、マウスを接続しますと起動後これらを使った login もできます。 startx で xwindow が起動します。ディスクトップは twm が入っています。 xfce4 や gnome（重い）もインストール可

能です。

出荷時＋emacs など多少 rpm パッケージ

を追加しています。

127

本ボードの NAND Flash ROM は 8Gb のデバイス 2 個で構成してあり、デバイス名は mtd4 です。

これを ubifs にアタッチし、ubi0:rootfs が/になっています。 [shlinux@sh2009n-rom ~]$ cat /etc/fstab ubi0:rootfs / ubifs defaults 0 0 proc /proc proc defaults 0 0 tmpfs /dev/shm tmpfs defaults 0 0 devpts /dev/pts devpts gid=5,mode=620 0 0 sunrpc /var/lib/nfs/rpc_pipefs rpc_pipefs defaults 0 0 [shlinux@sh2009n-rom ~]$ df Filesystem 1K-blocks Used Available Use% Mounted on ubi0:rootfs 1878156 525544 1347548 29% / tmpfs 257960 0 257960 0% /dev/shm [shlinux@sh2009n-rom ~]$ /sbin/ifconfig eth0 Link encap:Ethernet HWaddr 00:10:0C:00:54:43 inet addr:192.168.0.40 Bcast:192.168.0.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:585 errors:0 dropped:0 overruns:0 frame:0 TX packets:92 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:100 RX bytes:49426 (48.2 KiB) TX bytes:10866 (10.6 KiB) eth1 Link encap:Ethernet HWaddr 00:10:0C:00:54:42 inet addr:192.168.9.40 Bcast:192.168.9.255 Mask:255.255.255.0 UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1 RX packets:453 errors:0 dropped:0 overruns:0 frame:0 TX packets:5 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:36473 (35.6 KiB) TX bytes:210 (210.0 b) Interrupt:4 lo Link encap:Local Loopback inet addr:127.0.0.1 Mask:255.0.0.0 UP LOOPBACK RUNNING MTU:16436 Metric:1 RX packets:8 errors:0 dropped:0 overruns:0 frame:0 TX packets:8 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0 RX bytes:560 (560.0 b) TX bytes:560 (560.0 b)

３-１-４出荷時にインストールされているパッケージ

[shlinux@sh2009n-rom ~]$ rpm -qa | sort ConsoleKit-0.2.10-3.fc9.sh4 ConsoleKit-libs-0.2.10-3.fc9.sh4 ConsoleKit-x11-0.2.10-3.fc9.sh4 GConf2-2.22.0-1.fc9.sh4 MAKEDEV-3.23-4.sh4 ORBit2-2.14.12-3.fc9.sh4 PolicyKit-0.8-2.fc9.sh4 PolicyKit-gnome-0.8-4.fc9.sh4 PolicyKit-gnome-libs-0.8-4.fc9.sh4 VLGothic-fonts-20081029-1.fc9.noarch VLGothic-fonts-proportional-20081029-1.fc9.noarch acl-2.2.47-1.fc9.sh4 alsa-lib-1.0.16-3.fc9.sh4 alsa-lib-devel-1.0.16-3.fc9.sh4 atk-1.22.0-1.fc9.sh4

libidn-0.6.14-7.sh4 libjpeg-6b-41.fc9.sh4 libnotify-0.4.4-10.fc9.sh4 libpciaccess-0.10.3-2.fc9.sh4 libpng-1.2.29-1.fc9.sh4 libselinux-2.0.64-2.fc9.sh4 libselinux-python-2.0.64-2.fc9.sh4 libsemanage-2.0.25-1.fc9.sh4 libsepol-2.0.26-1.fc9.sh4 libsexy-0.1.11-8.fc9.sh4 libstdc++-4.3.0-8.sh4 libsysfs-2.1.0-3.fc9.sh4 libtasn1-1.3-1.fc9.sh4 libthai-0.1.9-4.fc9.sh4 libtiff-3.8.2-10.fc9.sh4

128

audiofile-0.2.6-8.fc9.sh4 audit-libs-1.7.5-1.fc9.sh4 audit-libs-python-1.7.5-1.fc9.sh4 autoconf-2.61-10.fc9.noarch automake-1.10.1-2.noarch avahi-0.6.22-11.fc9.sh4 avahi-compat-libdns_sd-0.6.22-11.fc9.sh4 avahi-glib-0.6.22-11.fc9.sh4 basesystem-8.1-1.noarch bash-3.2-22.fc9.sh4 beecrypt-4.1.2-17.fc9.sh4 bind-libs-9.5.0-32.rc1.fc9.sh4 bind-utils-9.5.0-32.rc1.fc9.sh4 binutils-2.18.50.0.6-2.sh4 bluecurve-icon-theme-8.0.2-1.fc9.noarch bzip2-1.0.5-1.fc9.sh4 bzip2-libs-1.0.5-1.fc9.sh4 cairo-1.6.4-1.fc9.sh4 checkpolicy-2.0.14-1.fc9.sh4 chkconfig-1.3.37-2.sh4 control-center-filesystem-2.22.2.1-1.fc9.sh4 coreutils-6.10-25.fc9.sh4 cpio-2.9-7.fc9.sh4 cpp-4.3.0-8.sh4 cracklib-2.8.12-2.sh4 cracklib-dicts-2.8.12-2.sh4 crontabs-1.10-19.fc9.noarch cryptsetup-luks-1.0.6-2.fc9.sh4 cups-1.3.7-2.fc9.sh4 cups-libs-1.3.7-2.fc9.sh4 cyrus-sasl-2.1.22-13.fc9.sh4 cyrus-sasl-lib-2.1.22-13.fc9.sh4 db4-4.6.21-5.fc9.sh4 db4-utils-4.6.21-5.fc9.sh4 dbus-1.2.4-2.fc9.sh4 dbus-glib-0.74-8.fc9.sh4 dbus-libs-1.2.4-2.fc9.sh4 dbus-x11-1.2.4-2.fc9.sh4 desktop-file-utils-0.15-1.fc9.sh4 device-mapper-1.02.24-11.fc9.sh4 device-mapper-libs-1.02.24-11.fc9.sh4 diffutils-2.8.1-21.fc9.sh4 e2fsprogs-1.40.8-3.fc9.sh4 e2fsprogs-libs-1.40.8-3.fc9.sh4 elfutils-0.133-3.fc9.sh4 elfutils-libelf-0.133-3.fc9.sh4 elfutils-libs-0.133-3.fc9.sh4 enchant-1.4.2-2.fc9.sh4 esound-libs-0.2.38-7.fc9.sh4 ethtool-6-1.fc9.sh4 eventlog-0.2.5-9.fc9.sh4 expat-2.0.1-5.sh4 fedora-gnome-theme-8.0.0-2.fc9.noarch fedora-icon-theme-1.0.0-1.fc8.noarch fedora-logos-9.0.0-2.fc9.noarch fedora-release-9-2.noarch fedora-release-notes-9.0.1-1.noarch

libtirpc-0.1.7-18.fc9.sh4 libtool-1.5.24-6.fc9.sh4 libtool-ltdl-1.5.24-6.fc9.sh4 libusb-0.1.12-15.fc9.sh4 libuser-0.56.9-1.sh4 libuser-python-0.56.9-1.sh4 libutempter-1.1.5-2.fc9.sh4 libvolume_id-120-5.20080421git.fc9.sh4 libwnck-2.22.3-1.fc9.sh4 libxcb-1.1-4.fc9.sh4 libxkbfile-1.0.4-5.fc9.sh4 libxml-1.8.17-19.fc9.sh4 libxml2-2.6.32-2.fc9.sh4 libxml2-python-2.6.32-2.fc9.sh4 libxslt-1.1.24-2.fc9.sh4 lilo-0.21-10.fc9.sh4 linux-atm-libs-2.5.0-5.sh4 logrotate-3.7.6-5.fc9.sh4 lzo-2.02-5.fc9.sh4 m4-1.4.10-3.fc9.sh4 make-3.81-12.fc9.sh4 metacity-2.22.0-5.fc9.sh4 mingetty-1.08-2.fc9.sh4 module-init-tools-3.4-13.fc9.sh4 mpfr-2.3.0-3.fc9.sh4 mtd-utils-1.2.0-2.fc9.sh4 mtd-utils-ubi-1.2.0-2.fc9.sh4 ncurses-5.6-16.20080301.fc9.sh4 ncurses-base-5.6-16.20080301.fc9.sh4 ncurses-libs-5.6-16.20080301.fc9.sh4 net-tools-1.60-87.fc9.sh4 newt-0.52.10-1.fc9.sh4 newt-python-0.52.10-1.fc9.sh4 nfs-utils-1.1.2-2.fc9.sh4 nfs-utils-lib-1.1.1-3.fc9.sh4 nodoka-metacity-theme-0.3.90-1.fc9.noarch notification-daemon-0.3.7-9.fc9.sh4 nspr-4.7.1-0.9.1.fc9.sh4 nspr-devel-4.7.1-0.9.1.fc9.sh4 nss-3.12.0.3-0.9.1.fc9.sh4 nss-devel-3.12.0.3-0.9.1.fc9.sh4 ntp-4.2.4p4-6.fc9.sh4 openldap-2.4.8-3.fc9.sh4 openldap-clients-2.4.8-3.fc9.sh4 openldap-servers-2.4.8-3.fc9.sh4 openslp-1.2.1-9.fc9.sh4 openssh-5.0p1-3.fc9.sh4 openssh-askpass-5.0p1-3.fc9.sh4 openssh-clients-5.0p1-3.fc9.sh4 openssh-server-5.0p1-3.fc9.sh4 openssl-0.9.8g-9.fc9.sh4 pam-1.0.1-4.fc9.sh4 pango-1.20.1-1.fc9.sh4 paps-0.6.8-6.fc9.sh4 paps-libs-0.6.8-6.fc9.sh4 passwd-0.75-2.fc9.sh4 patch-2.5.4-32.fc9.sh4

129

filesystem-2.4.6-1.fc7.sh4 findutils-4.2.33-3.fc9.sh4 firstboot-1.97-1.fc9.sh4 fontconfig-2.5.0-2.fc9.sh4 fonts-japanese-0.20061016-13.fc9.noarch freetype-2.3.5-6.fc9.sh4 gail-1.22.3-1.fc9.sh4 gamin-0.1.9-5.fc9.sh4 gawk-3.1.5-17.fc9.sh4 gcc-4.3.0-8.sh4 gd-2.0.35-5.fc9.sh4 gdbm-1.8.0-28.fc9.sh4 glib-1.2.10-29.fc9.sh4 glib2-2.16.3-5.fc9.sh4 glibc-2.8-3.sh4 glibc-common-2.8-3.sh4 glibc-devel-2.8-3.sh4 glibc-headers-2.8-3.sh4 glibc-utils-2.8-3.sh4 gmp-4.2.2-7.fc9.sh4 gnome-icon-theme-2.22.0-6.fc9.noarch gnome-keyring-2.22.3-1.fc9.sh4 gnome-mime-data-2.18.0-2.fc7.noarch gnome-mount-0.8-1.fc9.sh4 gnome-python2-2.22.1-2.fc9.sh4 gnome-python2-bonobo-2.22.1-2.fc9.sh4 gnome-python2-canvas-2.22.1-2.fc9.sh4 gnome-python2-gnomevfs-2.22.1-2.fc9.sh4 gnome-terminal-2.22.2-1.fc9.sh4 gnome-themes-2.22.0-1.fc9.noarch gnome-vfs2-2.22.0-1.fc9.sh4 gnutls-2.0.4-3.fc9.sh4 gnutls-utils-2.0.4-3.fc9.sh4 gpm-1.20.1-92.fc9.sh4 grep-2.5.1-59.fc9.sh4 gtk-nodoka-engine-0.7.1-2.fc9.sh4 gtk2-2.12.10-2.fc9.sh4 gtk2-engines-2.14.3-1.fc9.sh4 gzip-1.3.12-6.fc9.sh4 hal-0.5.11-2.fc9.sh4 hal-info-20080607-1.fc9.noarch hal-libs-0.5.11-2.fc9.sh4 hdparm-8.6-1.fc9.sh4 hicolor-icon-theme-0.10-4.noarch hunspell-1.2.1-7.fc9.sh4 hunspell-en-0.20080207-1.fc9.noarch hwdata-0.222-1.fc9.noarch imake-1.0.2-6.fc9.sh4 info-4.11-5.fc9.sh4 initscripts-8.76.2-1.sh4 iproute-2.6.25-1.fc9.sh4 iputils-20071127-2.fc9.sh4 kbd-1.12-31.fc9.sh4 kernel-2.6.28.9-1.noarch kernel-headers-2.6.24-1.sh4 keyutils-1.2-3.fc9.sh4 keyutils-libs-1.2-3.fc9.sh4

patchutils-0.2.31-5.fc9.sh4 pciutils-2.2.10-1.fc9.sh4 pcmciautils-014-12.fc9.sh4 pcre-7.3-3.fc9.sh4 perl-5.10.0-27.fc9.sh4 perl-Config-IniFiles-2.39-6.fc9.noarch perl-Module-Pluggable-3.60-27.fc9.sh4 perl-Pod-Escapes-1.04-27.fc9.sh4 perl-Pod-Simple-3.05-27.fc9.sh4 perl-libs-5.10.0-27.fc9.sh4 perl-version-0.74-27.fc9.sh4 pixman-0.10.0-1.fc9.sh4 pkgconfig-0.23-2.fc9.sh4 pm-utils-1.1.0-7.fc9.sh4 policycoreutils-2.0.47-2.fc9.sh4 policycoreutils-newrole-2.0.47-2.fc9.sh4 popt-1.13-3.fc9.sh4 popt-devel-1.13-3.fc9.sh4 procps-3.2.7-20.fc9.sh4 psmisc-22.6-5.fc9.sh4 pycairo-1.4.12-3.fc9.sh4 pygobject2-2.14.2-1.fc9.sh4 pygtk2-2.12.1-6.fc9.sh4 pygtk2-libglade-2.12.1-6.fc9.sh4 pyorbit-2.14.3-2.fc9.sh4 python-2.5.1-25.fc9.sh4 python-libs-2.5.1-25.fc9.sh4 python-numeric-24.2-11.fc9.sh4 pyxf86config-0.3.37-1.fc9.sh4 radeontool-1.5-3.fc9.sh4 rarian-0.8.0-1.fc9.sh4 rarian-compat-0.8.0-1.fc9.sh4 readline-5.2-13.fc9.sh4 rhpl-0.215-3.sh4 rhpxl-1.9-1.fc9.sh4 rpcbind-0.1.4-14.fc9.sh4 rpm-4.4.2.3-2.fc9.sh4 rpm-libs-4.4.2.3-2.fc9.sh4 rpm-python-4.4.2.3-2.fc9.sh4 rsync-3.0.2-0.fc9.sh4 rsyslog-3.16.1-2.fc9.sh4 ruby-libs-1.8.6.114-1.fc9.sh4 sazanami-fonts-gothic-0.20040629-4.20061016.fc8.noarch sazanami-fonts-mincho-0.20040629-4.20061016.fc8.noarch sed-4.1.5-10.fc9.sh4 selinux-policy-3.3.1-74.fc9.noarch selinux-policy-mls-3.3.1-74.fc9.noarch setup-2.6.14-1.fc9.noarch setuptool-1.19.4-2.fc9.sh4 shadow-utils-4.1.1-2.fc9.sh4 shared-mime-info-0.30-3.fc9.sh4 slang-2.1.3-3.fc9.sh4 sqlite-3.5.6-2.fc9.sh4 startup-notification-0.9-4.fc9.sh4 sudo-1.6.9p13-4.fc9.sh4 system-config-date-1.9.30-2.fc9.noarch

130

krb5-libs-1.6-6.sh4 less-418-3.fc9.sh4 lesstif-0.95.0-26.fc9.sh4 lesstif-mwm-0.95.0-26.fc9.sh4 libICE-1.0.4-3.fc9.sh4 libIDL-0.8.10-2.fc9.sh4 libSM-1.1.0-1.fc9.sh4 libX11-1.1.4-1.fc9.sh4 libXTrap-1.0.0-5.fc9.sh4 libXau-1.0.3-5.fc9.sh4 libXaw-1.0.4-2.fc9.sh4 libXcomposite-0.4.0-4.fc9.sh4 libXcursor-1.1.9-2.fc9.sh4 libXdamage-1.1.1-4.fc9.sh4 libXdmcp-1.0.2-5.fc9.sh4 libXext-1.0.4-1.fc9.sh4 libXfixes-4.0.3-3.fc9.sh4 libXfont-1.3.2-1.fc9.sh4 libXfontcache-1.0.4-5.fc9.sh4 libXft-2.1.12-5.fc9.sh4 libXi-1.1.3-4.fc9.sh4 libXinerama-1.0.3-1.fc9.sh4 libXmu-1.0.4-1.fc9.sh4 libXp-1.0.0-11.fc9.sh4 libXpm-3.5.7-4.fc9.sh4 libXrandr-1.2.2-3.fc9.sh4 libXrender-0.9.4-3.fc9.sh4 libXres-1.0.3-4.fc9.sh4 libXt-1.0.4-5.fc9.sh4 libXxf86misc-1.0.1-5.fc9.sh4 libXxf86vm-1.0.1-5.fc9.sh4 libacl-2.2.47-1.fc9.sh4 libart_lgpl-2.3.20-1.fc9.sh4 libattr-2.4.41-1.fc9.sh4 libbonobo-2.22.0-2.fc9.sh4 libbonoboui-2.22.0-2.fc9.sh4 libcap-2.06-4.fc9.sh4 libdaemon-0.12-3.fc9.sh4 libdrm-2.4.0-0.13.fc9.sh4 libedit-2.10-4.20070831cvs.fc9.sh4 libevent-1.3e-2.fc9.sh4 libfontenc-1.0.4-5.fc9.sh4 libgcc-4.3.0-8.sh4 libgcrypt-1.4.0-3.sh4 libglade2-2.6.2-6.fc9.sh4 libgnome-2.22.0-3.fc9.sh4 libgnomecanvas-2.20.1.1-4.fc9.sh4 libgnomeui-2.22.1-3.fc9.sh4 libgomp-4.3.0-8.sh4 libgpg-error-1.6-2.sh4 libgssapi-0.11-3.fc9.sh4 libgssglue-0.1-5.fc9.sh4

system-config-keyboard-1.2.15-2.fc9.noarch system-config-users-1.2.79-1.fc9.noarch sysvinit-tools-2.86-24.sh4 tar-1.19-4.fc9.sh4 tcp_wrappers-7.6-52.fc9.sh4 tcp_wrappers-libs-7.6-52.fc9.sh4 tmpwatch-2.9.13-2.sh4 tzdata-2008c-1.fc9.noarch udev-120-5.20080421git.fc9.sh4 upstart-0.3.9-19.fc9.sh4 usermode-1.98-1.fc9.sh4 ustr-1.0.4-6.fc9.sh4 util-linux-ng-2.13.1-6.fc9.sh4 vim-common-7.1.291-1.fc9.sh4 vim-enhanced-7.1.291-1.fc9.sh4 vim-minimal-7.1.291-1.fc9.sh4 vsftpd-2.0.7-1.fc10.sh4 vte-0.16.13-1.fc9.sh4 w3c-libwww-5.4.1-0.10.20060206cvs.fc9.sh4 which-2.19-3.fc9.sh4 wireless-tools-29-2.fc9.sh4 xdg-utils-1.0.2-5.20081121cvs.fc9.noarch xinetd-2.3.14-18.fc9.sh4 xkeyboard-config-1.2-4.fc9.noarch xorg-x11-apps-7.3-3.fc9.sh4 xorg-x11-drv-evdev-1.99.1-0.5.fc9.sh4 xorg-x11-drv-fbdev-0.3.1-7.fc9.sh4 xorg-x11-drv-keyboard-1.3.0-3.fc9.sh4 xorg-x11-drv-mouse-1.3.0-2.fc9.sh4 xorg-x11-drv-vesa-1.3.0-15.20080404.fc9.sh4 xorg-x11-drv-void-1.1.1-9.fc9.sh4 xorg-x11-drv-xgi-1.5.0-1.fc9.sh4 xorg-x11-filesystem-7.3-1.fc9.noarch xorg-x11-font-utils-7.2-4.fc9.sh4 xorg-x11-fonts-ISO8859-2-75dpi-7.2-6.fc9.noarch xorg-x11-fonts-misc-7.2-6.fc9.noarch xorg-x11-resutils-7.1-5.fc9.sh4 xorg-x11-server-Xorg-1.4.99.902-3.20080612.fc9.sh4 xorg-x11-server-common-1.4.99.902-3.20080612.fc9.sh4 xorg-x11-server-utils-7.4-1.fc9.sh4 xorg-x11-twm-1.0.3-2.fc9.sh4 xorg-x11-xauth-1.0.2-4.fc9.sh4 xorg-x11-xbitmaps-1.0.1-5.1.sh4 xorg-x11-xfwp-1.0.1-6.fc9.sh4 xorg-x11-xinit-1.0.9-1.fc9.sh4 xorg-x11-xinit-session-1.0.9-1.fc9.sh4 xorg-x11-xkb-utils-7.2-6.fc9.sh4 xterm-238-1.fc9.sh4 zlib-1.2.3-18.fc9.sh4

３-１-５起動しているデーモン [shlinux@sh2009n-rom ~]$ /sbin/chkconfig --list

131

avahi-daemon 0:off 1:off 2:off 3:off 4:off 5:off 6:off cups 0:off 1:off 2:off 3:off 4:off 5:off 6:off firstboot 0:off 1:off 2:off 3:off 4:off 5:off 6:off gpm 0:off 1:off 2:off 3:off 4:off 5:off 6:off haldaemon 0:off 1:off 2:off 3:on 4:on 5:on 6:off ldap 0:off 1:off 2:off 3:off 4:off 5:off 6:off messagebus 0:off 1:off 2:off 3:off 4:off 5:off 6:off netconsole 0:off 1:off 2:off 3:off 4:off 5:off 6:off netfs 0:off 1:off 2:off 3:on 4:on 5:on 6:off netplugd 0:off 1:off 2:off 3:off 4:off 5:off 6:off network 0:off 1:off 2:on 3:on 4:on 5:on 6:off nfs 0:off 1:off 2:off 3:off 4:off 5:off 6:off nfslock 0:off 1:off 2:off 3:on 4:on 5:on 6:off ntpd 0:off 1:off 2:off 3:off 4:off 5:off 6:off ntpdate 0:off 1:off 2:off 3:off 4:off 5:off 6:off rdisc 0:off 1:off 2:off 3:off 4:off 5:off 6:off restorecond 0:off 1:off 2:on 3:on 4:on 5:on 6:off rpcbind 0:off 1:off 2:off 3:on 4:on 5:on 6:off rpcgssd 0:off 1:off 2:off 3:on 4:on 5:on 6:off rpcidmapd 0:off 1:off 2:off 3:on 4:on 5:on 6:off rpcsvcgssd 0:off 1:off 2:off 3:off 4:off 5:off 6:off rsyslog 0:off 1:off 2:on 3:on 4:on 5:on 6:off saslauthd 0:off 1:off 2:off 3:off 4:off 5:off 6:off sshd 0:off 1:off 2:on 3:on 4:on 5:on 6:off udev-post 0:off 1:on 2:on 3:on 4:on 5:on 6:off vsftpd 0:off 1:off 2:off 3:off 4:off 5:off 6:off xinetd 0:off 1:off 2:off 3:on 4:on 5:on 6:off xinetd based services: chargen-dgram: off chargen-stream: off daytime-dgram: off daytime-stream: off discard-dgram: off discard-stream: off echo-dgram: off echo-stream: off rsync: off tcpmux-server: off time-dgram: off time-stream: off

３-１-６コンパイル

vi、gcc、binutiles など最小限の開発ツールもインストールされています。 [nakamura@sh2009n-rom ~]$ vi hello.c #include <stdio.h> main() { printf("SH-2009¥n"); } :wq "hello.c" [New] 7L, 55C written [nakamura@sh2009n-rom ~]$ gcc -O2 -o hello hello.c [nakamura@sh2009n-rom ~]$ ./hello SH-2009 [nakamura@sh2009n-rom ~]$

132

３-２MTDデバイス

本ボードには、32MB の NOR Flash ROM1 個と、8Gb の NAND Flash ROM2 個が搭載されて

います。これらは、Linux の MTD（メモリテクノロジデバイス）でサポートしています。

３-２-１NOR Flash ROM

CPU のリセットが解除されると NOR Flash ROM の 0 番地から起動します。この IPL（イニシ

ャルプログラムローダ）を含めて MTD ツールで書き換えが可能です。 MTD パーティション

パーティション内容ブロックデバイス /dev/mtd0 sh-ipl サイズ：512KB /dev/mtdblock0 /dev/mtd1 別の FPGA プログラムデータサイズ：256KB /dev/mtdblock1 /dev/mtd2 Linux kernal サイズ 3MB /dev/mtdblock2 /dev/mtd3 未使用サイズ：28.25MB /dev/mtdblock3

mtd0,1,2 は常にキャラクタデバイスとしてアクセスしています。mtd3 は、リリースしているデ

ィストリビューションでは未使用です。mtd3 としても jffs2 などを使用し mtdblock3 としても使用

可能です。

３-２-２NOR Flash ROM書き換えの手順

そのブロックを unlock します。そのブロックを erase します。書き込みたいデータを cp で書き込みます。＜実行例＞ /usr/sbin/flash_unlock /dev/mtd2 /usr/sbin/flash_eraseall /dev/mtd2 cp zImage /dev/mtd2 zImage は、ビルドした SH-Linux カーネル（カーネルツリー/artc/sh/boot/Zimage）です。

同様にして、mtd0（sh-ipl）も書き換え可能ですが、sh-ipl を壊すと本ボードが起動できなくな

ります。もし sh-ipl を壊した場合は、JTAG デバッガ（ルネサス社 E10A を推奨）が必要になりま

す。

３-２-３NAND Falsh ROM

NAND Flash ROM は、2 個をまとめて１つの MTD デバイスにしてあり、ROM から起動した本

ボードのルートファイルシステムになっています。本ボードでは、ルートファイルシステムに UBIFS を採用しています。ファイルの圧縮も有効にな

っていますので、ディスク使用量が少なくなっています。ファイルのコピーや消去などは一般のハードディスクと同様です。

133

３-２-４UBIFS初期化方法

UBIFS の初期化と、使用方法は jffs2 や yaffs2 と多少異なります。次のような手順で行います。

ROM のイレース /usr/sbin/flash_eraseall /dev/mtd4

アタッチ /usr/sbin/ubiattach /dev/ubi_ctrl -m 4 -d 0

ボユームの作成 /usr/sbin/ubimkvol /dev/ubi0 -N rootfs --maxavsize

マウント例 mount -t ubifs ubi0:rootfs /mnt/rom （/が抜けている訳ではありません。）

詳しくは、kernel のドキュメントや ubifs（http://www.linux-mtd.infradead.org/）のドキュメン

トを参照してください。 UBIFS をルートファイルシステムに使用するには、kernel の起動オプションが必要です。本ボードでは、sh-ipl ソースツリーの中に kernel コマンドラインの記述があります。 cd sh-ipl cat config/config.h-sh2009 <snip> /* Kernel Command Line for ROM boot (root file system is set to /dev/mtdblock2) */ #define CONFIG_KERNEL_COMMAND_LINE "ubi.mtd=4 ,4096 root=ubi0:rootfs ro rootfstype=ubifs earlyprintk=serial" （実際は 1 行です） <snip> 上記で ubifs に関係する部分は ubi.mtd=4 root=ubi0:rootfs ro rootfstype=ubifs です。

３-３YUM (Yellow dog Updater, Modified)

本ボードのユーザーランドパッケージは FedoraCore9 ベースです。パッケージ管理は rpm です

ので、FedoraCore ベースの x86LinuxPC と同様に yum が使用できます。パッケージは当社のサー

バにあります。

パッケージのupdate

NAND Flash ROMには、yumが入っていませんが、以下のパッケージをインストールすると yumが使えます。（本ボードがインターネットに接続されている必要があります） rpm -ivh yum-3.2.20-5.fc9.noarch.rpm pygpgme-0.1-8.fc9.sh4.rpm python-iniparse-0.2.4-1.fc9.noarch.rpm yum-metadata-parser-1.1.2-8.fc9.sh4.rpm python-urlgrabber-3.0.0-9.fc9.noarch.rpm gpgme-1.1.6-3.fc9.sh4.rpm

134

gnupg2-2.0.9-1.fc9.sh4.rpm pth-2.0.7-6.sh4.rpm pinentry-0.7.4-5.fc9.sh4.rpm dirmngr-1.0.1-2.fc9.sh4.rpm libksba-1.0.3-2.fc9.sh4.rpm libcurl-7.18.1-1.fc9.sh4.rpm （実際は一行に記述します）必要な rpm パッケージは、前もって当社のサイトからダウンロードしてください。ダウンロードサイト http://rpm.sh-linux.org/rpm-fc9/RPMS/sh4/ 次に以下ように/etc/yum.repos.d/以下のファイルを編集します。（ちょっとした理由で rpm パッケ

ージに入れている repo データファイルは x86 用にしています。） rm –rf /etc/yum.repos.d/* vi などで以下のファイルを作成します。 -bash-3.2# cat /etc/yum.repos.d/fedora9.repo [fedora9] name=Fedora 9 - $basearch failovermethod=priority baseurl=http://rpm.sh-linux.org/rpm-fc9/RPMS/sh4 enabled=1 gpgcheck=0

３-３-１アップデートパッケージのチェック

-bash-3.2# yum check-update （多少時間が必要です） -bash-3.2# yum check-update fedora9 | 951 B 00:00 fedora9/ | 2.7 MB 00:03 fedora9 8272/8272 MAKEDEV.sh4 3.23-5.fc9 fedora9 PolicyKit.sh4 0.8-3.fc9 fedora9 <snip> w3c-libwww.sh4 5.4.1-0.13.20060206cvs.fc9 fedora9 xinetd.sh4 2:2.3.14-20.fc9 fedora9 -bash-3.2#

３-３-２パッケージのアップデート

yum –y update でアップデートを実行できます。 -bash-3.2# yum –y update Setting up Update Process Resolving Dependencies --> Running transaction check ---> Package db4-utils.sh4 0:4.6.21-7.fc9 set to be updated ---> Package libpng.sh4 2:1.2.33-1.fc9 set to be updated

http://rpm.sh-linux.org/rpm-fc9/RPMS/sh4/�

135

<snip> --> Finished Dependency Resolution Dependencies Resolved ==================================================================== Package Arch Version Repository Size ==================================================================== Installing: libgssglue sh4 0.1-6.fc9 fedora9 23 k replacing libgssapi.sh4 0.11-3.fc9 ntp-perl sh4 4.2.4p6-1.fc9 fedora9 22 k replacing ntp.sh4 4.2.4p4-6.fc9 Updating: MAKEDEV sh4 3.23-5.fc9 fedora9 141 k PolicyKit sh4 0.8-3.fc9 fedora9 246 k <snip> Transaction Summary ==================================================================== Install 5 Package(s) Update 110 Package(s) Remove 0 Package(s) Total download size: 140 M Downloading Packages: (1/115): eventlog-0.2.7-1.fc9.sh4.rpm | 17 kB 00:00 (2/115): mcstrans-0.2.11-1.fc9.sh4.rpm | 18 kB 00:00 <snip> --------------------------------------------------------------------------------------------------------------------------------------------- Total 456 kB/s | 140 MB 05:14 ======================= Entering rpm code======================== Running rpm_check_debug Running Transaction Test Finished Transaction Test

136

Transaction Test Succeeded Running Transaction Updating : setup 1/227 warning: /etc/passwd created as /etc/passwd.rpmnew Updating : filesystem 2/227 Updating : ncurses-base 3/227 <snip> Updating : vim-enhanced 113/227 Updating : glibc-utils 114/227 Installing : ntp-perl 115/227 Cleanup : ncurses 116/227 Cleanup : vim-minimal 117/227 <snip> Installed: libgssglue.sh4 0:0.1-6.fc9 ntp-perl.sh4 0:4.2.4p6-1.fc9 Dependency Installed: libicu.sh4 0:3.8.1-7.fc9 mcstrans.sh4 0:0.2.11-1.fc9 ntpdate.sh4 0:4.2.4p6-1.fc9 Updated: MAKEDEV.sh4 0:3.23-5.fc9 PolicyKit.sh4 0:0.8-3.fc9 acl.sh4 0:2.2.47-2.fc9 bash.sh4 0:3.2-23.fc9 bind-libs.sh4 32:9.5.1-1.P1.fc9 bind-utils.sh4 32:9.5.1-1.P1.fc9 <snip> Dependency Updated: ntp.sh4 0:4.2.4p6-1.fc9 Replaced: libgssapi.sh4 0:0.11-3.fc9 ntp.sh4 0:4.2.4p4-6.fc9 Complete!

３-３-３パッケージのインストール

本ボードには、apache(http サーバ)がインストールされていませんので、ここでインストールし

てみます。アップデートでインストールされた不要な repo ファイルを削除します。 -bash-3.2# rm /etc/yum.repos.d/fedora-* -bash-3.2# rm /etc/yum.repos.d/fedora.repo

137

-bash-3.2# yum install httpd Setting up Install Process Parsing package install arguments Resolving Dependencies --> Running transaction check ---> Package httpd.sh4 0:2.2.9-1.fc9 set to be updated --> Processing Dependency: httpd-tools = 2.2.9-1.fc9 for package: httpd --> Processing Dependency: libapr-1.so.0 for package: httpd --> Processing Dependency: libaprutil-1.so.0 for package: httpd --> Processing Dependency: /etc/mime.types for package: httpd --> Running transaction check ---> Package apr-util.sh4 0:1.2.12-5.fc9 set to be updated ---> Package httpd-tools.sh4 0:2.2.9-1.fc9 set to be updated ---> Package apr.sh4 0:1.2.12-2.fc9 set to be updated ---> Package mailcap.noarch 0:2.1.28-1.fc9 set to be updated --> Finished Dependency Resolution Dependencies Resolved 依存関係で追加が必要なパッケージがリストされます。 ==================================================================== Package Arch Version Repository Size ==================================================================== Installing: httpd sh4 2.2.9-1.fc9 fedora9 1.1 M Installing for dependencies: apr sh4 1.2.12-2.fc9 fedora9 281 k apr-util sh4 1.2.12-5.fc9 fedora9 180 k httpd-tools sh4 2.2.9-1.fc9 fedora9 80 k mailcap noarch 2.1.28-1.fc9 fedora9 15 k Transaction Summary ==================================================================== Install 5 Package(s) Update 0 Package(s) Remove 0 Package(s) Total download size: 1.7 M

138

Is this ok [y/N]: y ← 肯定応答します。 Downloading Packages: (1/5): mailcap-2.1.28-1.fc9.noarch.rpm | 15 kB 00:00 (2/5): httpd-tools-2.2.9-1.fc9.sh4.rpm | 80 kB 00:00 (3/5): apr-util-1.2.12-5.fc9.sh4.rpm | 180 kB 00:00 (4/5): apr-1.2.12-2.fc9.sh4.rpm | 281 kB 00:00 (5/5): httpd-2.2.9-1.fc9.sh4.rpm | 1.1 MB 00:00 ------------------------------------------------------------------------------------------------------------------------------- Total 1.2 MB/s | 1.7 MB 00:01 ========================== Entering rpm code ============================= Running rpm_check_debug Running Transaction Test Finished Transaction Test Transaction Test Succeeded Running Transaction Installing : apr 1/5 Installing : mailcap 2/5 Installing : apr-util 3/5 Installing : httpd-tools 4/5 Installing : httpd 5/5 ========================== Leaving rpm code =================== Installed: httpd.sh4 0:2.2.9-1.fc9 Dependency Installed: apr.sh4 0:1.2.12-2.fc9 apr-util.sh4 0:1.2.12-5.fc9 httpd-tools.sh4 0:2.2.9-1.fc9

mailcap.noarch 0:2.1.28-1.fc9 Complete! -bash-3.2#

139

４ソフトウェア

本ボードのソフトウェアは、GNU GPL などオープンライセンス条項に基づいたものです。使用

された結果や、使用に際しての問題など、いかなる動作も保証しない完全無保証ですが、目的に応

じてご自身で自由に改変できることが保証されています。

４-１クロスコンパイル環境

sh-linux の kernel や sh-ipl は x86Linux マシン（FedoraCore/RedHat）にクロスコンパイル

環境をインストールし、クロスコンパイルを行います。

４-２FedoraCoreマシンにパッケージをインストール

付属 DVD を x86Linux マシンにセットします。（automount が動作していない場合は、適当な

場所にこの DVD を mount してください）次の順番にパッケージをインストールします。（root 権限で実行してください） # rpm -Uvh /mount_point/cross_tools/binutils-sh-linux-2.18.50.0.6-2.i386.rpm # rpm -Uvh /mount_point/cross_tools/gcc-sh-linux-4.3.2-7.1.i386.rpm # rpm -Uvh /mount_point/cross_tools/module-init-tools-sh-linux-3.2-0.pre9.2.2.1.i386.rpm 注意：kernel のバージョンが 2.6.25.x までは、gcc-sh-linux-3.4.x でコンパイルできましたが、

それ以降の kernel は、gcc-sh-linux-4.3.x 以降の gcc が必要です。また、一部のソースファイルでは、

gcc-sh-linux-3.4.x では出なかった構文エラーが gcc-sh-linux-4.3.x では発生する場合があります。

無用なエラーを避ける意味でも本ボードと同時にリリースしたソースファイルをお使いください。

４-３IPL

付属メディアに sh-ipl のアーカイブが入っています。sh 用クロス gcc やクロス binutils などがイ

ンストールされた Linux が動作している x86PC でクロスコンパイルできるようになっています。付属メディアに linux-sh-2.6.29.4（またはそれより新しいもの）のアーカイブが入っています。sh用クロス gccやクロス binutilsなどがインストールされたLinuxが動作している x86PCでクロスコ

ンパイルできるようになっています。 sh-ipl を x86Linux マシンの適当な場所に展開します。例 $ pwd /home/foo $ mkdir sh2009 $ cd sh2009 $ tar jxf /mount_point/sh-ipl.tar.bz2 $ cd sh-ipl

140

$ make 出来上がった sh2009-ipl.bin が mtd0 にコピーできる ipl です。

４-４kernel

付属メディアに linux-sh-2.6.29.4（またはそれより新しいもの）のアーカイブが入っています。sh用クロス gccやクロス binutilsなどがインストールされたLinuxが動作している x86PCでクロスコ

ンパイルできるようになっています。 kernel ツリーを x86Linux マシンの適当な場所に展開します。例 $ pwd /home/foo $ mkdir sh2009 $ cd sh2009 $ tar jxf /mount_point/linux-sh-2.6.29.4.tar.bz2 $ cd linux-sh-2.6.29.4 $ cp arch/sh/configs/sh2009_defconfig .config $ make （$ name –j 5）コンフィグレーションが sh2009_defconfig の場合、ビルドに要する時間はシングルコアマシンの場合：20 分～30 分程度です。マルチコアマシンの場合、make に –j コアの数（make –j 5 など）とします。4 コアの CPU の

場合で 5 分程度です。（スイッチ j のオペランドは CPU のコアの数+1 が良いそうです）

４-４-１本ボードへ新しいkernelモジュールをコピーする

kernel 本体（arch/sh/boot/zImage）と共にモジュールも生成されています。モジュールは root ファイルシステムの/lib/modules/カーネルバージョン/ 以下にコピーする必要があります。一般的には以下のようにしてモジュールをインストールできます。 pwd が/home/foo/sh2009/ linux-sh-2.6.29.4 として mkdir –p ../export/lib/modules make modules_install mtd2 の zImage を入れ替えたらモジュールも更新が必要です。 /home/foo/sh2009/export/lib/modules 以下のファイルを rsync などで本ボードの/lib/modules/にコ

ピーします。（必要に応じて/home/foo/sh2009/export/lib/firmware 以下もコピーします）

カーネルトップディレクトリのMakefileの195行目あたりを変更すると別の場所へインストール

できます。 INSTALL_MOD_PATH ?= ../export

141

４-４-２IOを制御するデバイスドライバを作成される方へ

SH2009（CPU:SH7785。32 ビットアドレスモード）は、SH2007(SH7780。29 ビットアドレ

スモード)以前のものと論理アドレスが異なっています。 SH2009 では P2 領域を使用した IO アクセスができませんので、TLB で IO アドレスを P3 領域

にリマップしています。(TLB 1 エントリーは 8KB） SH2009 の IO マッピングは kernel ソースツリーの arch/sh/include/mach-sh2009/mach/hardware.h に記述しています。それを使用したリマップは、 arch/sh/boards/mach-sh2009/setup.c に ioremap を呼ぶコードがあります。 ioremap 本体は、arch/sh/kernel/io_generic.c にある generic_ioremap()です。

４-４-３ttyS0～ttyS5 RS232C/RS485 選択

シリアルインターフェースのモデム制御信号 nDTR で RS232C/RS485 を選択します。例（include や termios の設定は記載していません） void setdtr (int tty_fd, int on) { int modembits = TIOCM_DTR; ioctl(tty_fd, (on ? TIOCMBIS : TIOCMBIC), &modembits); } init_sio() { int fd; fd = open(device, O_RDWR | O_NOCTTY); setdtr(tty_fd, 0); /* RS485 を選択 */ } ttyS?を login ポートなどに設定した場合は、nDTR がアクティブになりますから、RS232C が

選択されます。 cat /etc/event.d/ttyS7 # tty1 - getty # # This service maintains a getty on tty1 from the point the system is # started until it is shut down again. start on stopped rc2 start on stopped rc3 start on stopped rc4 start on started prefdm stop on runlevel 0 stop on runlevel 1 stop on runlevel 6 respawn exec /sbin/agetty 115200 ttyS7

４-４-４ADコンバータ

142

8CH 12 ビット AD コンバータは、次のようにして利用できます。サンプル adc.c #include <stdio.h> #include <stdlib.h> #include <string.h> #include <fcntl.h> #include <sys/ioctl.h> #define ADC "/dev/adc" #define ADC_SETRANGE 0x01 #define ADC_RANGE_M5V_5V 0x00 // ±5V #define ADC_RANGE_M10V_10V 0x04 // ±10V #define ADC_RANGE_0V_5V 0x08 // 0～+5V #define ADC_RANGE_0V_10V 0x0c // 0～+10V int main(int ac, char *av[]) { int fd[8]; char buf[128]; int i; unsigned int val; unsigned long range; for ( i = 0; i < 8; i++) { sprintf(buf, "%s%1d", ADC, i); fd[i] = open(buf, O_RDONLY); } range = ADC_RANGE_0V_10V; ioctl(fd[0], ADC_SETRANGE, &range); // CH0 を 0～+10V レンジに設定 range = ADC_RANGE_M10V_10V; ioctl(fd[1], ADC_SETRANGE, &range); // CH1 を±10V レンジに設定 for (i = 0; i < 8; i++) { read(fd[i], &val, sizeof(val)); printf("CH%1d val=%d¥n", i, val); } return 0; }

udev はデバイスファイルの権限を 660 で作りますので、パーミッションを変更します。 -bash-3.2# chmod 666 /dev/sdc? [foo@sh2009n]$ gcc -O2 -o adc adc.c AD 入力に+3V を印加してテストした結果です。 [foo@sh2009n]$ ./adc CH0 val=1210 CH1 val=605 CH2 val=2417 CH3 val=2419 CH4 val=2419 CH5 val=2419 CH6 val=2419 CH7 val=2419 [foo@sh2009n]$

143

５エラータ

ユーザーランドのプログラムが exit（終了）するとき、次のようなエラーがでる場合があります。将来のリリースでは、改修する予定ですが、現行のバージョンでは以下のようなメッセージがでま

す。なお、コマンド名やレジスタ、メモリの内容は一例です。エラーの原因は命令@(r0,r1), r12 を

実行したときの R1 レジスタの内容が間違っているためです。 Unable to handle kernel paging request at virtual address de5e1442 pc = 80186418 *pde = 9e04e000 Oops: 0000 [#1] Modules linked in: ipv6 Pid : 1279, Comm: login CPU : 0 Not tainted (2.6.29.4 #57) PC is at lookup_user_key+0x18/0x460 PR is at keyctl_revoke_key+0x12/0x60 PC : 80186418 SP : 9e013f74 SR : 40008000 TEA : d2d8e36c R0 : 801864b0 R1 : 5e45af92 R2 : 00000000 R3 : 804d3494 R4 : 2f22d7c1 R5 : 00000000 R6 : 00000000 R7 : 00000004 R8 : 80185300 R9 : 2f22d7c9 R10 : 00000071 R11 : 2f22d7c1 R12 : 299c51c0 R13 : 00000054 R14 : 9e013f8c MACH: 00000001 MACL: 00000010 GBR : 29860450 PR : 80185152 Call trace: [<80185300>] sys_keyctl+0x0/0x2c0 [<801853c6>] sys_keyctl+0xc6/0x2c0 [<80185300>] sys_keyctl+0x0/0x2c0 [<80009212>] syscall_call+0xc/0x10 Code: 80186412: mov r4, r11 80186414: mov.l r13, @-r15 80186416: add r1, r1 ->80186418: mov.w @(r0,r1), r12 8018641a: mov.l r14, @-r15 8018641c: mov r7, r13 8018641e: sts.l pr, @-r15 80186420: add #-8, r15 80186422: mov r15, r14 Process: login (pid: 1279, stack limit = 9e012001) Stack: (0x9e013f74 to 0x9e014000) 3f60: 00000054 299c51c0 00417120 3f80: 00000071 0000007f 80185300 801853c6 9e013f98 80185300 80009212 7b8b778c 3fa0: 7b8b77ac 00000000 295e09bc 0000011f 00000003 2f22d7c1 00000000 295c8a2a 3fc0: 299c5220 00000000 00000000 00417120 299c51c0 00000054 7b8b778c 7b8b778c 3fe0: 296ed732 299b4a50 00000001 29860450 00000001 00000010 0000005c 00000160 ---[ end trace b6e53c9c2a47815b ]---

144

５-１ソフトウェアアップデート

アップデートされたファイルは、当社の Web サイトから入手できます。

URL http://rpm.sh-linux.org/sh2009/

http://rpm.sh-linux.org/sh2009/�

145

６著作権表示

本書内容の全て、付属の DVD-ROM（DVD-R）や Web 上で公開する SH-2009 回路図お

よび FPGA,CPLD ロジックなどの著作権は株式会社アイ・ティー・オーにあります。回路

図およびFPGA,CPLDソースファイルはSH-2009をご利用頂く上での便宜のために公開し

ています。回路図および FPGA,CPLD 内部ロジックを他のハードウェアに転用することは

できません。ただし SH-2009IO ボードに代えて独自 IO ボードを設計・製作し、SH-2009

と合わせてお使いの場合は、SH-2009 用 FPGA ソースファイルをお使い頂けます。

製品に関するお問い合わせは

URL http://www.sh-linux.org http://www.itonet.co.jp E-Mail mailto:[email protected] 販売元株式会社ダイセン電子工業〒556-0005 大阪市浪速区日本橋 4-9-24

E-Mail mailto:[email protected] Tel 06-6631-5553 Fax06-6631-6886

開発・製造元株式会社アイ･ティー･オー〒573-0046 大阪府枚方市宮之下町 8-2

E-Mail mailto:[email protected] Tel 072-853-3553 Fax 072-853-3577

http://www.sh-linux.org/�

http://www.itonet.co.jp/�

mailto:[email protected]�



Documents

SH-Linux ボード · PDF fileSH-Linuxボード. SH-2009ユーザーズガイド. Rev.1.0.1 2009/6 . 株式会社アイ･ティー･オー