• According to Clein, what has been one of the main reasons why CAD tools have failed to be successful among IC layout engineers?

• With respect to CAD tools, what are some of the advantages and • disadvantages to being a small IC design house? • What is an IC design flow? Why do IC design teams operate

within the constraints of design flows? • Why PMOS transistor networks are generally used to produce

Logic high(1) signals, while NMOS networks are used to produce Logic low(0) signals?

• On IC schematics, transistors are usually labeled with one, or sometimes two numbers. What do each of those numbers mean?

• Why is the number of gate inputs to CMOS gates (e.g. NAND or NOR gates) usually limited to four?

• What is meant by static and dynamic power with respect to the operation of a CMOS gate? Why do CMOS gates dissipate close to zero static power? Why is the static power not exactly zero?

• What is a transmission gate and what is it used for typically? Why are transmission gates made with both PMOS and NMOS transistors?

• What are the major factors that determine the speed that a logic signal propagates from the input of one gate to the input of the next driven gate in the signal's path?

• What are some of the major techniques that are usually considered when one wants to speed up the propagation speed of a signal?

• What is the difference between a mask layer and a drawn layer in an IC layout? Why do layout designers usually only specify drawn layers?

• In an IC layout, what is a polygon and what is a path? What are the advantages and disadvantages of each?

• What is the difference between a contact and a via? What is a "stacked" via process?

• Why is it that NMOS transistor can be created directly in a P-type substrate, whereas PMOS transistor must be created in an N-type well?

• Why must transistors be provided with "bulk" connections? What voltage levels are connected to a p-type substrate and an n-type well through these connections, and why?

• What are process design rules? What is their major purpose? How are design rules created?

• What are width rules, space rules, and overlap rules? • What is a "vertical connection diagram"? What is it used for? • The routing strategies for the power grid and global signals

are usually defined at the start of planning a new chip floorplan. Why?

• What are the major advantages of hierarchical IC design? • Define what is meant by the terms design rules checking, layout

versus schematic, and electrical rules check? Are all three procedures required in every chip design?

• What is meant by the term "porosity"? Why is it desirable for a cell or macro to have high porosity?

• What are the main differences in priorities between microprocessor design, ASIC design, and memory design? How those differences are reflected in the corresponding design flows?

• What is an "application-specific memory", according to Clein? What are some specific examples of this part type?

• What is the difference between a soft IP block (soft core) and a hard IP block (hard core)?

• In ASIC design, what are the main advantages of expressing the design using a hardware description language, such as VHDL or Verilog?

1

• Why are memory layouts designed primarily from the bottom up, instead of from the top down, like other ICs?

• With respect to a memory layout, what is meant by "array efficiency"?

• What is "pitch-limited layout"? What are some of the major circuits in a memory layout that must meet pitch-limited constraints?

• What are some of the typical kinds of cells that one would expect to find in a library of standard cells?

• The layout of standard cells is constrained to simplify the job of place & route tools. Give several examples of these constraints.

• Why did older cell libraries include so-called feedthrough cells? Why are such cells no longer required in cell libraries for modern processes?

• What is electromigration? How does electromigration affect the design of a standard cell based design?

• What is a gate array? Why are main advantages of using gate arrays to implement an IC? What are some of the main disadvantages, with respect to custom design or standard cell based design?

• Why might one want to use some gate array based design inside an otherwise custom IC design, according to Clein's experience?

• What are some of the major similarities and differences of standard cells and datapath cells?

• How is the problem of driving a clock node different from that of designing a regular signal node? What are the key goals when laying out a clock node?

• What is a "pad frame"? What are "staggered" pads? • Why 90 degree corners are usually avoided in the layout of pad

cells? • In the layout of output pad driver transistors, why is the gate

length often lengthened at both ends of the gate? • Why is the pad ring provided with power supply connections that

are separate from those of the core design? • What are so-called friendly cells in a DRAM core design? Why

and where these cells included in a memory design? • Why are metal straps used along with polysilicon wordlines in

memory designs? • Why are wordline driver circuits very long and narrow? • Describe some of the alignment keys that are included in IC

layouts. • Why is the power supply interconnect layout layout planned out

before other elements? Similarly, why are busses, differential signals, and shielded signals routed before other general signals?

• What are the root and resistance styles of power supply layout? • What are some of the main reasons why clock skew minimization

is such a major design challenge? • What are the major advantages and disadvantages of using a

single clock tree conductor driven by one big buffer? • In ASIC design flows, why are clock trees inserted after the

logic cells have been placed? In such clock trees, how is clock skew minimized at the leaves of the tree?

• What is a routing channel? Why are routing channels used in IC layouts?

• Why is the estimated area for routing channels increased by 10% during early stages of layout planning?

• When routing a signal interconnect, why is it desirable to minimize layer changes through vias?

• Interconnect resistance is usually minimized in IC layouts. Give at least four situations where a deliberably large, but controlled, resistance is usually required?

2

• Why should minimum-width paths be avoided in the design of deliberate resistances?

• Usually one wishes to minimize the capacitance of electrical nodes in an IC design. Give four examples of circuits where one would wish a larger, but controlled, capacitance at a node?

• The capacitance on a node is the sum of several components. What is meant by fringe capacitance? How does reducing the width of a conductor affect the fringe capacitance?

• How can the parasitic capacitance between two signal nodes possibly cause the signal transition on one of the nodes to be unexpectedly sped up?

• How can a layout designer help ensure that the propagation delay along two conductors is very similar?

• List four situations where it may be desirable to have 45 degree corners in the interconnect.

• Explain what is meant by electromigration. What are some possible consequences of unexpectedly high electromigration? How is electromigration controlled in IC layout design?

• Why are wide metal conductors, such as those in the power rings, provided with slits? What constraints must be followed when positioning these slits?

• When placing multiple vias to connect two metal conductors, why is it better to space the vias far apart from each other?

• Why would a DRAM layout be verified against two or more different sets of design rules?

• What is the antenna effect, and how can it cause problems in an IC design? What are two layout techniques that can be used to reduce vulnerability to the antenna effect?

• What is the purpose of minimum area design rules? • What is the purpose of end overlap rules? • What is the phenomenon of latch-up? Why is it a serious concern

in CMOS layout design? • Describe six different layout strategies that are commonly used

to minimize the possibility of latch-up. • Why is it wise to plan designs to make it easier to change

details later? • What is meant by metal strap programmability and via

programmability? Give one example where each techniques is commonly used.

• What is the difference between test pads and probe pads? • Dan Clein advocates the use of contact and via cells, which is

not a common design practice. What are his reasons? • In which situation should one avoid using the minimum allowed

feature sizes allowed by the design rules? • What fundamental factors limits the speed with which detected

design errors can be corrected? • When floorplanning a chip at the start of the IC layout process,

what are the main goals in deciding how to arrange the major blocks in the design?

• How is block floorplanning different from chip floorplanning? • What is a silicon compiler? How is it different from a tiler? • What is the difference between a channel router and a maze

router? Which type of router will tend to produce higher utilization factors?

• What is a chip assembly tool? What kind of routing should a chip assembly tool provide to have maximum flexibility?

• At IBM, it has been found to be advantageous to sacrifice performance when migrating a chip design in one process into a second process. Process migration is facilitated by the use of "migratable design rules". What is the major benefit that can be obtained by such rules to offset the loss in potential chip performance?

3

• At IBM a design methodology has been developed that makes the layout of standard cells very similar to that of gate array cells. What is the potential benefit of intermixing such cells in the same chip design?

• In its ASIC design flow, IBM uses a formal verification tool that performs a technique called Boolean equivalence checking. What is the primary potential benefit of using formal verification methods in design verification? What is the conventional way of verifying the equivalence of different implementations of the same function?

• IBM has standardized its logic design on the use of pulse-triggered latches, whereas the rest of the industry has tended to adopted design based on edge-triggered flip-flops. What is the strategy that IBM has adopted to be able to accommodate designers from other companies who wish to have ASICs fabricated through IBM?

• Why are terminator cells sometimes used when clock trees are inserted into a block of placed standard cells?

• When constructing a clock tree with distributed buffers, why is it very desirable to keep the buffers lightly loaded near the root of the clock distribution tree? Why can leaf nodes of the clock tree can be loaded more heavily? Why does one aim to have a balanced clock tree?

• What is the difference between two- and three-dimensional analysis of interconnect capacitance.

• Guard bands are usually built into the timing estimates employed by logic synthesis, cell placers, and other CAD tools. What is lost when the guard bands are relatively large? What could be gained if the timing estimates could be made more accurate?

• Full 3-D capacitance calculations are generally extremely timing consuming.How can the technique of tunneling be used to make such calculations efficient enough to use in large IC designs?

• The output of a 3-D field solver is a charge distribution over the signal net under consideration, and a charge distribution over the surrounding passive nets. Generally the signal net is assumed to be at a potential of 1 volt while the other nets are held at 0 volts. How can the signal net's self-capacitance and coupling capacitance then be computed?

• Moore's Law predicts a doubling in the number of transistors per chip every two to three years. The major factor supporting Moore's Law is improvements in lithographic resolution that permit finer features. What are the two other major factors that Moore believes have allowed Moore's Law to hold? Even if physical factors allow for further increases in per-chip component density, what other factors could slow or even stop Moore's Law in practice?

• What is meant by the term "dual damascene process"? How has the availability of this type of process simplified the creation of multiple interconnected metal layers?

• In processes that have multiple layers of metal interconnect, why is it common to make the upper wires thicker than the lower layers? (The use of fat wires is sometimes called "reverse scaling".) In which situations would one be willing to use reverse scaling and hence appear to throw away the possible advantages of thinner wires?

• What are some of the important reasons why DRAM technology has been a pioneer for semiconductor technology advances?

• Briefly explain what are planar DRAM cells, trench capacitor DRAM cells,and stacked capacitor DRAM cells. Which type of cell is becoming dominant in embedded DRAMs? Why is this so?

4

• There are numerous technological challenges and additional costs with embedded DRAM. Describe three of the main potential advantages that could be gained with embedded DRAM. What are characteristics of an application that could benefit from using embedded DRAM?

• What are the three most common process solutions to providing embedded DRAM? Discuss some of the important trade-offs that must be made when selecting a process strategy for embedded DRAM

• How does a MOSFET works. • What are different types of BJT configurations and when do we

use them. • What is the difference between TTL and CMOS (even others

also like ECL etc). • What is noise margin? • Which is the most important pin the microcontroller? • Explain about Ground Bounce and Vcc Sag. • What is EMI and what are different types of it. • What is LVDT? • How do we select the correct value of decoupling capacitor (or)

what is the purpose of using a decoupling capacitor. • What is parasitic capacitance & what are the effects of it. • What is the difference between microprocessor and micro

controller? • What are different types of micro processor architectures? • Difference between by pass capacitor and decoupling capacitor • How do you select an op amp (this can apply to other components

also?) • What are Single ended and differential signals. • How do you decide the layer stack up on PCB? • Filter Design: Analog and Digital Filters, different types of

filters. • What is signal integrity? • What is Meta stability? • Difference between CPLD and FPGA • Difference between DDR and DDR2 RAM. • What is termination? What are the different types of

terminations? • When do you need to use a heat sink and how do you decide on

that. • What is the difference between clock buffer and clock driver? • What is Jitter? • What is gain bandwidth product? • Define settling time of op amp. • What is slew rate of op amp, define common mode rejection ratio

and input offset voltage. • What is the difference between static response and dynamic

response? • What is an integrator and differentiator? How do we design them? • Define the parameters of an ADC or types of ADC etc. • What is sample and hold circuit. • What is a comparator? • What is Fan Out? • Different types of Voltage regulators. (Linear, Switching

etc...) • How do you create a basic delay circuit? • What is characteristic impedance? • What is ringing, undershoot and overshoot of a signal why do

they occur and how to reduce them. • What is latch up?

5

• What are the parameters to be taken into consideration while selecting a MOSFET?

• What are the different modes of operation of MOSFET and BJT (Linear & Switching and Cut Off?)

• How do you implement a current source using BJT or MOSFET? • What is hysteresis? And what are the advantages and

disadvantages of it. • What are the effects of vias on PCB? • How do you design a voltage to frequency converter? • 8051 architecture. • Ethernet communication • Different types of serial communications ex. I2C • Different types of memory devices (ROM, RAM, SRAM and EEPROM

etc) • How to select an Opto coupler. • What is the main advantage of using a bridge rectifier rather

than using a full wave rectifier? • What are the applications of zener diode? • What are the applications of schottky diode? • Why do we need a Gate Driver for MOSFET in switching operations? • What is pulse width modulation? Give any examples. • How does SMPS (Switch mode power supply) works? • What does it mean by PID control? • What are different types of Flip flops? • What is meant by quiescent current and what is the significance

of it. • How does an instrumentation amplifier differ from normal

operational amplifier? • What are snubbers and how do they protect switching circuits. • What is sampling time and how to fix it? • What is Rogowski coil and what are its advantages over normal

current transformer. • What is a relaxation oscillator? • What is hysteresis? • What are the different applications of comparators? • How does a Unijunction Transistor works. • How does programable unijunction transistor works. • What are the differences between ASIC, FPGA and CPLD? • How to select a network processor. • What is the difference between radiated emissions and conducted

emissions how to detect and reduce them? • What are the different types of negative resistance devices and

what are their applications. • What is the difference between flip flop and latch? • What are the types of errors in ADC and DAC’s? • What is Setup and Hold time of flip flop? • What is Race condition in flip flops? • What is the difference between RISC and CISC processors? • What is tri-state logic? • What is the difference between Hardware reset and Software

reset? • How do you determine the response time of any circuit. [Loop

response] • What factors will impact the characteristic impedance of the

PCB (Dielectric property of insulating material, Separation between the planes, thickness of the trace.)

• What are the advantages of using differential signal routing in PCB?

6

• How do we make sure that the impedance matching between driver and reciever are maintained?

• Different types of terminations and their advantages and disadvantages.

• What is meant by microstip and stripline? • How do you decide the placement of components on PCB? i.e.

where to route power signals, where to route clock signals, how to route digital signals and analog signals.

• Why do we need a tie? • If suppose you have designed a PCB in which you have selected

BGA components what is the care you take when routing. (Hint: - Connect all ground pins of BGA IC through thermal Pad).

• If you have decided to go for only two layer board how you route power, signal and ground layers.

• Why do we need to route gnd in planes rather than a trace? • If we have both analog and digital circuitry on PCB what care

we will take while grounding. (How doe we connect those grounds.i.e.through Ferrite bead or Jumper)

• What does it mean by positive layer and negative layer? • What is meant by Solder Mask and Solder Paste? • How to decide on what components should be present in top layer

and what components should be place in bottom layer. • What is meant by Reflow Soldering and when do we perform it. • What is meant by Wave Soldering what are the advantages and

disadvantages of it. • What are different types of connectors? (i mean through hole

and SMD and what care you need to take while placing them. usually place near to the end of PCB and never route any power signals below it.)

• what are different types of gerbers.( Hint:-Basic gerber and Extended gerber the difference is in basic gerber all apertures are linked in different files where in in extended gerber all apertures are linked in a single file.)

• On which side of the board soldering should be done first. • What are the different types of dielectric material used in PCB.

(Hint:- FR4,HFR4). • Different kinds of Vias in PCB (normal via, blind via and

burried via). • What is pulse width modulation and give some examples where we

can use that concept. • What are different types of filters (single ended and

differential filters you can also think in the way like low pass, high pass, band pass and band reject filters)?

• How does impedance mismatch in signal path effect. • Why we should not route right angled traces.(right angled

traces will act as antenna) • Why do we call BJT as current controlled device and MOSFET as

voltage controlled device. • What are active and passive devices? • What are the differences between positive and negative feed

back in amplifiers. • What are the advantages of using Darlington pair of transistors? • What does it mean by light pipes give some examples where they

can be used. • What are the different types of semiconductors (Hint:-direct

band gap and indirect band gap) • What is thyristor and what are the applications of it. • Can you explain the applications of Zener diode, Tunnel diode,

and Schottky diodes?

7

• what is the advantage of bridge rectifier when compared to full wave rectifier.(Hint:- The output polarity of bridge rectifier is always same irrespective of input polarity, hence when ever we change the supply polarity by mistake the output circuitry will not get effected)

• What is clipping and clamping design a circuit which does the same.

• Why do we need to use heat sinks on certain components? What is the criterion to select a heat sink? (Hint:- Power dissipation is the main culprit)

• Why do we operate a MOSFET or BJT in saturation when we use them for switching purpose?

• What is quiescent current? • What are the different types of oscillators? • What is thermal run away? • Can you explain briefly on different types of packages of ICs.

(Ex: TO-92 etc...) • What is IGBT and what are the advantages of it. • What are different types of MOSFETs (Hint:- Depletion type and

Enhancement type) • How do we overcome common mode noise.( explain any preventive

measures to be taken to avoid it) • What are the different types of noise? • What are buffers? What is the importance of using buffers in

any circuit? (Hint: - Buffers usually will have high input impedance and low output impedance hence it will support to connect more loads at the output and it maintains the input voltage)

• What are the different types of Analog to Digital Converters? • What are the different types of Digital to Analog Converters? • What are the applications of unijunction transistor? • Can you give some examples of Voltage to Current converters? • What is offset voltage and why do we need to care about it

while selecting an Op Amp. • What is meant by Thermocouple and what are the cares we need to

take while capturing the output of thermocouple and processing it.

• What are different types of power supplies? (Hint: - Unregulated, regulated, linear, ripple regulated and switching).

• What is Power Budgeting and how do we perform it. What are the things we will take into consideration while performing power budgeting.

• What is PLL? Did you any time worked on Voltage controlled oscillators.

• What is the most important Pin in any microcontroller? (Hint: - reset)

• What is the difference between serial and parallel communication.

• What is the difference between RS-232, RS-485 etc...? • What care you should take while interfacing any microprocessor

to memory. • What are different types of memory? (Hint:-Static, dynamic etc.) • How do you select a SDRAM? • What is EEPROM? • Can you explain in brief about the difference between Switches

and Bridges? And what are the advantages of each and when to use them.

• What is JTAG? Did you any time use JTAG to debug any circuit and how it is useful.

• Did you use any kind of Isolation Amplifiers? • How do you generate square wave from sine wave.

8

• Do you know what is mono stable multi vibrator and astable multi vibrator?

• How do you provide transient voltage suppression? • Did you any time used digital or analog multiplexer. • How do you convert serial data to parallel data and vice versa? • What do you mean by Charge Pump? • What are the considerations to be taken while selecting a micro

controller for a specific application? • How unity power factor circuit works. • What are the different grounding methods available in PCBs? • What is space vector control method? How is it different from

pulse width modulation? • How Schmitt trigger comparator circuit is better than normal

comparator circuit. • What is the difference between Hardware, Software and Firmware

for particular application? • What is thermostat and its applications? • How to select magnetic shielding for particular components and

why do you need shielding. • What is feed forward method and how is it helpful in predictive

control circuits. • What are the different types of switched mode power supplies

and what are their power ratings. • Why we should separate digital and analog grounds in a PCB. • How a MOV (metal oxide varistor) or TVS helps in protecting

circuits. • How do you design sample EMI Filters. • What are the major causes for Radiated Emission? (Hint: - clock

harmonics, improper terminations etc...) • What is wetting voltage? • What is dry contact? • What happens when a solder is dry solder. • What is a chattering contact? • What is the difference between hardware reset and software

reset? • How to you implement line monitoring in any circuit. • What are the advantages/dis-advantages of using NAND/NOR Flash. • What is the difference between SDRAM and DDRRAM? • What is memory banking? • How to set gain of an amplifier what are the parameters you

need to consider while deciding gain. • How do you determine the stability of any system? (Hint:- Pole,

zero etc..) • What is lead/lag compensation? • How to improve/decrease the slew rate of Op-Amp. • What are the different types of processor architectures (Hint:-

Von-neumann, Harvard ) • What is the difference between 8085 and 8086? What are the

major changes done to 8086? • What is miller effect? • Bode-plot, Phase-margin and Frequency Compensation in Two-stage

Op-Amp • Gain-splitting using miller-capacitor in Frequency compensation • Where is the dominal pole? estimate the magnitude of dominal

pole and other poles • If the first stage is telescope or folded-cascode, estimate its

max swing, headroom When used as unity-gain buffer, estimate its slewing rate

• If A and B are two clk pulses which are out of phase and having same frequency, how to find which input clk signal is leading?

9

• What are the differences between SIMULATION and SYNTHESIS? • What is a Microprocessor? • Give examples for 8 / 16 / 32 bit Microprocessor? • Why 8085 processor is called an 8 bit processor? • What is 1st / 2nd / 3rd / 4th generation processor? • Define HCMOS? • What does microprocessor speed depend on? • Is the address bus unidirectional? • Is the data bus is Bi-directional? • What is the disadvantage of microprocessor? • What is the difference between microprocessor and

microcontroller? • Why does microprocessor contain ROM chips? • What is the difference between primary & secondary storage

device? • Difference between static and dynamic RAM? • What is interrupt? • What is cache memory? • What is called Scratch pad of computer? • Which transistor is used in each cell of EPROM? • Differentiate between RAM and ROM? • What is a compiler? • Which processor structure is pipelined? • What is flag? • What is stack? • Can ROM be used as stack? • What is Nonvolatile RAM? • Have you studied buses? What types? • Have you studied pipelining? List the 5 stages of a 5 stage

pipeline. • Assuming 1 clock per stage, what is the latency of an

instruction in a 5 stage machine? What is the throughput of this machine?

• How many bit combinations are there in a byte? • For a single computer processor computer system, what is the

purpose of a processor cache and describe its operation? • Explain the operation considering a two processor computer

system with a cache for each processor. • What are the main issues associated with multiprocessor caches

and how might you solve them? • Explain the difference between write through and write back

cache. • Are you familiar with the term MESI? • Are you familiar with the term snooping? • Describe a finite state machine that will detect three

consecutive coin tosses (of one coin) that results in heads. • In what cases do you need to double clock a signal before

presenting it to a synchronous state machine? • You have a driver that drives a long signal & connects to an

input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

• What is the difference between = and == in C? • What types of CMOS memories have you designed? What were their

size? Speed? • What work have you done on full chip Clock and Power

distribution? • What process technology and budgets were used? • What types of I/O have you designed? What were their sizes?

Speed? Configuration? Voltage requirements?

10

• Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

• What types of high speed CMOS circuits have you designed? • What transistor level design tools are you proficient with?

What types of designs were they used on? • What products have you designed which have entered high volume

production? • What was your role in the silicon evaluation/product ramp? What

tools did you use? • If not into production, how far did you follow the design and

why did not you see it into production? • Can structures be passed to the functions by value? • Why cannot arrays be passed by values to functions? • Advantages and disadvantages of using macro and inline

functions? • What happens when recursion functions are declared inline? • Scope of static variables? • Difference between object oriented and object based languages? • Multiple inheritances - objects contain how many multiply

inherited ancestor? • What are the 4 different types of inheritance relationship? • How would you find out the no of instance of a class? • Is java a pure object oriented language? Why? • Order of constructor and destructor call in case of multiple

inheritances? • Can u have inline virtual functions in a class? • When you inherit a class using private keyword which members of

base class are visible to the derived class? • What is the output of printf("\nab\bcd\ref"); -> ef • #define cat(x,y) x##y concatenates x to y. But cat(cat(1,2),3)

does not expand but gives preprocessor warning. Why? • Can you have constant volatile variable? Yes, you can have a

volatile pointer? • ++*ip increments what? it increments what ip points to • Operations involving unsigned and signed — unsigned will be

converted to signed • a+++b -> (a++)+b • malloc(sizeof(0)) will return — valid pointer • main() {fork();fork();fork();printf("hello world"); } — will

print 8 times. • Array of pts to functions — void (*fptr[10])() • Which way of writing infinite loops is more efficient than

others? there are 3ways. • # error — what it does? • How is function itoa() written? • Who to know wether systemuses big endian or little endian

format and how to convert among them? • What is interrupt latency? • What is a forward reference w.r.t. pointer in c? • How is generic list manipulation function written which accepts

elements of any kind? • What is the difference between hard real-time and soft real-

time OS? • What is interrupt latency? How can you reduce it? • What is the differnce between embedded systems and the system

in which rtos is running? • How can you define a structure with bit field members? • What are the features different in pSOS and vxWorks?

11

• How do you write a function which takes 2 arguments - a byte and a field in the byte and returns the value of the field in that byte?

• What are the different storage classes in C? • What are the different qualifiers in C? • What are the different BSD and SVR4 communication mechanisms • What is pipelining? • What are the five stages in a DLX pipeline? • For a pipeline with ‘n’ stages, what’s the ideal throughput?

What prevents us from achieving this ideal throughput? • What are the different hazards? How do you avoid them? • Instead of just 5-8 pipe stages why not have, say, a pipeline

with 50 pipe stages? • What are Branch Prediction and Branch Target Buffers? • How do you handle precise exceptions or interrupts? • What is a cache? • What’s the difference between Write-Through and Write-Back

Caches? Explain advantages and disadvantages of each. • Cache Size is 64KB, Block size is 32B and the cache is Two-Way

Set Associative. For a 32-bit physical address, give the division between Block Offset, Index and Tag.

• What is Virtual Memory? • What is Cache Coherency? • What is a Snooping cache? • What are the components in a Microprocessor? • What is ACBF(Hex) divided by 16? • Convert 65(Hex) to Binary • Convert a number to its two’s compliment and back • The CPU is busy but you want to stop and do some other task.

How do you do it? • Give two ways of converting a two input NAND gate to an

inverter • Given a circuit, draw its exact timing response. (I was given a

Pseudo Random Signal Generator; you can expect any sequential ckt)

• What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?

• Give a circuit to divide frequency of clock cycle by two • Design a divide-by-3 sequential circuit with 50% duty circle.

(Hint: Double the Clock) • Suppose you have a combinational circuit between two registers

driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)

• The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?

• What are the different Adder circuits you studied? • Give the truth table for a Half Adder. Give a gate level

implementation of the same. • Draw a Transmission Gate-based D-Latch. • Design a Transmission Gate based XOR. Now, how do you convert

it to XNOR? (Without inverting the output) • How do you detect if two 8-bit signals are same? • How do you detect a sequence of "1101" arriving serially from a

signal line? • Design any FSM in VHDL or Verilog. • Explain RC circuits charging and discharging. • Explain the working of a binary counter. • Describe how you would reverse a singly linked list.

12

• What is the use of BLOCKS? • What is the use of PROCEDURES? • What is the usage of using more then one architecture in an

entity? • Explain why & how a MOSFET works • Draw Vds-Ids curve for a MOSFET. Now, show how this curve

changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel Length Modulation

• Explain the various MOSFET Capacitances & their significance • Draw a CMOS Inverter. Explain its transfer characteristics • Explain sizing of the inverter • How do you size NMOS and PMOS transistors to increase the

threshold voltage? • What is Noise Margin? Explain the procedure to determine Noise

Margin • Give the expression for CMOS switching power dissipation • What is Body Effect? • Describe the various effects of scaling • Give the expression for calculating Delay in CMOS circuit • What happens to delay if you increase load capacitance? • What happens to delay if we include a resistance at the output

of a CMOS circuit? • What are the limitations in increasing the power supply to

reduce delay? • How does Resistance of the metal lines vary with increasing

thickness and increasing length? • You have three adjacent parallel metal lines. Two out of phase

signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other

• What happens if we increase the number of contacts or via from one metal layer to the next?

• Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

• Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

• Draw the stick diagram of a NOR gate. Optimize it • For CMOS logic, give the various techniques you know to

minimize power consumption • What is Charge Sharing? Explain the Charge Sharing problem

while sampling data from a Bus • Why do we gradually increase the size of inverters in buffer

design? • Why not give the output of a circuit to one large inverter? • In the design of a large inverter, why do we prefer to connect

small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

• Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

• Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

• Why don't we use just one NMOS or PMOS transistor as a transmission gate?

• For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

• Draw a 6-T SRAM Cell and explain the Read and Write operations

13

• Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

• What happens if we use an Inverter instead of the Differential Sense Amplifier?

• Draw the SRAM Write Circuitry • Approximately, what were the sizes of your transistors in the

SRAM cell? How did you arrive at those sizes? • How does the size of PMOS Pull Up transistors (for bit & bit-

lines) affect SRAM's performance? • What's the critical path in a SRAM? • Draw the timing diagram for a SRAM Read. What happens if we

delay the enabling of Clock signal? • Give a big picture of the entire SRAM Layout showing your

placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

• In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

• How can you model a SRAM at RTL Level? • What is the difference between Testing & Verification? • For an AND-OR implementation of a two input Mux, how do you

test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

• What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

• Can u tell me the differences between latches & flip-flops? • Equivalence between VHDL and C? • What is the difference between using direct instantiations and

component ones except that you need to declare the component? • What is a D-latch? Write the VHDL Code for it? • Implement D flip-flop with a couple of latches? Write a VHDL

Code for a D flip-flop? • Differences between Signals and Variables in VHDL? If the same

code is written using Signals and Variables what does it synthesize to?

• Differences between functions and Procedures in VHDL? • Explain the concept of a Clock Divider Circuit? Write a VHDL

code for the same? • Difference between RTL and Behavioral code. • What happens in the following two cases with CMOS invetrer

o if positions of source and drain of both n and p mos devices are interchanged

o nmos is replced by pmos and vice versa

• How transition time is going to effect your delay? • If load is more, would delay increase or decrease? why? • How skew is goint to effect your setup and hold? Will it help

the setup? • If skew is more, how it is going to effect your design? • If phase delay is more, how it is going to effect your design? • Why we need to fix the max transition before setup and hold? • What is meant by false path? When can we call selection line of

multiplexer as a false path? And when not? • How we will decide the path as a false path? Can you tell by

taking mux as an example? • Why we need to fix hold after CTS only? • Explain multi cycle path with example and waveform • How is power consumption effected with shrinking technology? • What are the different types of placements? • How will u know whether to do a Timing Driven placement or

Congestion Driven placement?

14

• What does timing library consist of? • Tell about Look up tables? • How to calculate die size? • How to calculate the no of VDD and VSS pads? • Convert 2 i/p mux to inverter? • What is "set input delay" in sdc file? • During IPO upsizing and downsizing,what are upsized or

downsized,FF's or Combi logic? Why? • Explain setup and hold with example and waveforms • What is and effects of Hot carrier effect? • How buffer minimizes skew as gate delays is more than

propagation or transition Delays? • How to form cap in MOS? If Drain and source is shorted how will

it behave Like a capacitor? Which type of cap is it? • How Mos device works? • How CMOS Inverter works. How the N MOS/PMOS works in different

region ie. Cut-off, saturation, linear. • Equation of IDS in different region. • Electro migration Calculation • Antenna effect, from where the charge comes? • Where will we put the diode, nearer to gate or far from gate, &

why? • How layer hopping reduces the process Antenna effect? • Why distance between diffusion contacts? • Cross section of MOS? • Cut it in half; how the view looks like? • Guard Ring, secondary guard ring? Why is it always as ring? • If u cut guard ring how will it look like? • In diffusion region why multiple contact, what will happen if

we put a big contact? • How will u calculate the power stripe width? • How will u improve IR drop effect? • RC ckt. (Low pass Filter), o/p curve • If u increase Vdd, what will be the effect on the sub threshold

current? • What kind of Capacitor is there in MOS? MOS device cap curve?

Value of C Substrate? • DFM rule? • How even no. of fingering is better than odd no. of fingering?

How does it effect the • Quality of layout? • A circular wheel is half painted black and the other half

painted white. There are 2 censors mounted 45 degree apart at the surface of this wheel( not touching the wheel) which give a "1" for black and "0" for white passing under them. Design a circuit to detect which way the wheel is moving. Can not assume any fixed position for start.

• What accuracy do you expect from a typical untrimmed bandgap? • What is nonlinearity" and "which technique to reduce

nonlinearity in Analog or Mixed-signal or RF IC design"? • Typically, what breaks first on a MOSFET as voltage bias is

increased, the gate or the drain diffusion? • What are types of routing? • There are two flip-flops....one flip flop (FF) was havng a clk

of 10MHz and the other 18MHz...the o/p of 10MHZ FF was fed directly to I/P of 18MHz FF.now wht are the problems in this circuit(if any) and what are the remedies for them,,,,,take the FF as T-FF

• Asynchronously writing means......... • When bust of data is coming........

15

• design an inverter for a fan-out of four • What are the setup and hold time constraints? What do they

signify? Which one is critical for estimating maximum clock frequency of a circuit?

• How to implement 4:1 mux and 2:1 mux as Nor gate? • Suppose there are 10 setup and 10 hold violations in a design.

Manager will come and tell you that design needs to be taped out tomorrow. As much as possible violations need to be fixed. How you go about fixing these violations? Which violation you try to fix either setup or hold and why?

• Electro migration, & How will u overcome this & at what level u see it (In Processing or after a chip is manufactured?)

• How will u calculate Electro migration & what r the data u need to calculate E.M.? How fingering effect the E.M.?

• What is Antenna effect & how metal hopping improves antenna effects? (Positive Charge gets collected on the metal, from where this charge comes?)

• Explain Latch up? How the Vdd value will come down to 0.9 if it is 5V earlier?

• How more substrate contact reduces +ve resistance and also well contact?

• How P-tap / N-tap improves latch up? • When the ESD does occur? In processing or in operation? • When the Electro migration does occur? In processing or in

Operation? • Timing Slack, Setup, Hold, How to calculate the slack? • If I am writing into FIFO Arrow asynchronously with 25 writes

per second and reading form FIFO with 25 reads per second synchronously. Then what is the depth of this FIFO?

• What should be the expected output?

16

• The opamp shown in the circuit has the open loop response given as shown, so it has enough phase margin. When the opamp is connected in the feedback as shown, it becomes unstable for a particular Vin as Vin is increased. Why does that happen?

• What is the output of AND gate in the circuit below, when A and B are as in waveform? Where, Tp is gate delay of respective gate

17

• Identify the below circuit, and its limitation?

• What is the current though the resistor R1 (Ic)?

• Referring to the diagram below, briefly explain what will happen if the propagation delay of the clock signal in path B is much too high compare to path A. How do we solve this problem if the propagation delay of path B can not be reduced?

• What is the function of a D flip-flop, whose inverted output is connected to its input?

• Design a circuit to divide input frequency by 2? • Design a divide-by-3 sequential circuit with 50% duty cycle. • What are the different types of adder implementation? • Draw a Transmission Gate-based D-Latch? • Give the truth table for a Half Adder. Give a gate level

implementation of the same • What is the purpose of the buffer in below circuit, is

it necessary/redundant to have buffer?

18

• What is output of the below circuit, assuming that value of 'X' is not known?

• Consider a circular disk as shown in figure below with two sensors mounted X, Y and blue shade painted on the disk for a angle of 45 degree. Design a circuit with minimum number of gates to detect the direction of rotation.

• Design a OR gate from 2:1 MUX.

• What is the difference between a LATCH and a FLIP-FLOP ? • Design a D Flip-Flop from two latches.

• Design a 2 bit counter using D Flip-Flop.

19

• What are the two types of delays in any digital system ? Wire Delay and Gate Delay

• Design a Transparent Latch using a 2:1 Mux.

o logic

of other

ng D-Latch.

ive Clock Skew, Positive Clock Skew?

nchronous counter ?

he difference between a NAND-based Flash and NOR-based

Design a 33.3 MHz clock with

s superior Asynchronous Reset or Synchronous Reset,

te machine for Traffic Control at a Four point

irectional?

egisters?

n 8085? VI?

de?

uring DMA transfer?

e functions of ALE in 8085.

• Design a 4:1 Mux using 2:1 Mux's and some comb• What is metastable state? How does it occur? • Design a FSM to detect sequence "101" in input sequence

Design a D and T flip flop using 2:1 mu• x, use components not allowed, just the mux.

• Design a divide by two counter usi• Design D Latch from SR flip-flop • Define Clock Skew , Negat• What is Race Condition? • Design a 4 bit Gray Counter ? • Design 4-bit Synchronous counter, Asy• Design a 16 byte Asynchronous FIFO? • What is the difference between a EEPROM and FLASH ?

What is t• Flash ? You are given a 100 MHz clock • , and without 50 % duty cycle?

• Design a Read on Reset System ? Which one i• Explain ? Design a Sta• Junction ?

• Which type of architecture 8085 has? • How many memory locations can be addressed by a microprocessor

with 14 address lines? • 8085 is how many bit microprocessor? • Why is data bus bi-d• What is the function of accumulator? • What is flag, bus? • What are tri-state devices and why they are essential in a bus

oriented system? • Why are program counter and stack pointer 16-bit r• What does it mean by embedded system? • What are the different addressing modes i• What is the difference between MOV and M• What are the functions of RIM, SIM, IN?• What is the immediate addressing mo• What are the different flags in 8085? • What happens d• What do you mean by wait state? What is its need? • What is PSW? • What is ALE? Explain th• What is a program counter? What is its use? • What is an interrupt?

20

• Which line will be activated when an output device require attention from CPU?

• What is meant by D-FF? • What is the basic difference between Latches and Flip flops?

• n you convert an JK Flip-flop to a D Flip-flop? fy it?

• akdown and avalanche breakdown? s of filters? ng ideal response of filters and

•

unterparts.

d full-duplex communication?

on? • e need for modulation?

• for

• ition to fundamental frequency?

r to supply

• s more efficient than BFSK in presence of noise. Why? -emphasis?

not

• you mean by ASCII, EBCDIC? OR gate for fabrication?

ise

• u size NMOS and PMOS transistors to increase the

• delay if we include a resistance at the output

• sing the power supply to

• tal lines vary with increasing

• techniques you know to

• ing data from a Bus?

ircuit to one large

ain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

• What is a multiplexer? • How can you convert an SR Flip-flop to a JK Flip-flop?

How ca• What is Race-around problem? How can you recti• Which semiconductor device is used as a voltage regulator and

why? • What do you mean by an ideal voltage source?

What do you mean by zener bre• What are the different type• What is the need of filteri

actual response of filters? What is sampling theorem?

• What is impulse response? • Explain the advantages and disadvantages of FIR filters

compared to IIR co• What is CMRR? Explain briefly. • What do you mean by half-duplex an

Explain briefly. • Which range of signals are used for terrestrial transmissi

What is th• Which type of modulation is used in TV transmission?

Why we use vestigial side band (VSB-C F) transmission 3

picture? When transmitting digital signals is it necessary to transmitsome harmonics in add

• For asynchronous transmission, is it necessary to supply some synchronizing pulses additionally or to supply ostart and stop bit? BPFSK i

• What is meant by pre-emphasis and de• What do you mean by 3 dB cutoff frequency? Why is it 3 dB,

1 dB? What do

• Why is NAND gate preferred over N• What is Noise Margin? Explain the procedure to determine No

Margin • Explain sizing of the inverter?

How do yothreshold voltage?

• What is Noise Margin? Explain the procedure to determine Noise Margin?

• What happens to delay if you increase load capacitance? What happens toof a CMOS circuit? What are the limitations in increareduce delay? How does Resistance of the methickness and increasing length? For CMOS logic, give the various minimize power consumption? What is Charge Sharing? Explain the Charge Sharing problem while sampl

• Why do we gradually increase the size of inverters in buffer design? Why not give the output of a cinverter?

• What is Latch Up? Expl

21

• Give the expression for CMOS switching power dissipation? What i• s Body Effect?

o

•

•

•

ith one another in an inverter?

Digital Circuits? ys to

l B.

tate-machines

d • ie-high and tie-low cells and where it is used

hes and flip-flops based

Low-Vt cells?

• skew, global-skew, useful-skew mean? ke care in

• eant by virtual clock definition and why do I need it?

esign? ted by the

th an MOSFET? • Vds-Ids curve for an MOSFET, with increasing Vgs. • What is Channel length Modulation?

• Why is the substrate in NMOS connected to Ground and in PMOS tVDD?

• What is the fundamental difference between a MOSFET and BJT? Which transistor has higher gain? BJT or MOS and why?

• Why do we gradually increase the size of inverters in buffer design when trying to drive a high Capacitive load? In CMOS technology, in digital design, why do we design the size of pmos to be higher than the nmos.What determines the size of pmos wrt nmos. Though this is a simple question try tolist all the reasons possible? Why PMOS and NMOS are sized equally in a Transmission Gates?

• All of us know how an inverter works. What happens when the PMOS and NMOS are interchanged w

• Give 5 important Design techniques you would follow when doing a Layout for

• What is metastability? When/why it will occur?Different waavoid this?

• Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signa

• To optimize delay of the two series NMOS inputs A and B which one would you place near to the output?

• what is the difference between mealy and moore s• How to solve setup & Hold violations in the design • What is antenna Violation & ways to prevent it • how to estimate the width of the power-strap of the power-gri

what is t• what is the difference between latc

designs • What is High-Vt and• What is LEF mean? • What is DEF mean? • Steps involved in designing an optimal padring • What is metastability and steps to prevent it?

What is local-• What are the various timing-paths which I should ta

my STA runs? • What are the various components of Leakage-power? • What are the various yield-losses in the design?

What is m• What are the various Variations which impacts timing of the

design? • What are the various Design constraints used while performing

Synthesis for a d• Specify few verilog constructs which are not suppor

synthesis tool. • What are the various capacitances wi

22

•

If the following inverter biased in the middle of Vdd, what is the small signal gain? (Answer gmXro)

• Crossection diagram of the inverter (be able to draw the

T leads to latch-up. clampping

• erter or NOR/NAND gate. •

How about it stability?

contact of power supply and ground)

• From the crossection of the diagram, be able to draw the parasitic BJ

• How to prevent latch-up (do not forget guard ring,circuits!) Draw the layout of an invFor the following source follower, what is its -3dB bandwidth?

In the following f • igu s are equal, what

source follower.

re, if the two resisteris its -3dB bandwidth? Compare its stability with that of a

• For the following circuit, if the input is a rail-to-rail

square wave, plot the wave after the inverter and vo.

23

•

If

e NMOS

Now gain remains constant with increasing biasing current!)

For the following circuits, What is the gain? Using what technology to improve the matching of the input transistors?the bias current increase, what happens to the gain? (Hit: Decrease!!!) What happens to the bandwidth? Replace thwith npn BJT and PMOS with pnp BJT, answer the above questions.(

• tages and disadvantages of these two amplifiers?

For the following circuits, answer the questions again. What are the advan

• value of the resistance is R).

Answer: both of them are 1/gm.

What are the effective resistance from source to drain of the following two transistors? (The

24

• es the dominant pole

locate? How about the pole at node 1?

What is the low frequency gain of the following circuits? Theinput is the input current Iin. WhereDo

•

he transistors VS Vin. (This question was supplied by Wang Ge)

For the following circuit, the threshold voltage of the transistor is 0.7V. Vb1=1v, Vb2=2v, When Vin changes from 5V to 0V, draw the current flow through t

• ll me what are Vo1 and

Vo2 when Vin is 5V, 3V, 2.5V and 0V.

For the following circuits, Vdd=5v, te

• ? Where

is the Feedback and what is the function of feedback?

For the following circuit, what is the gain of Vout/Vin

25

For the following circuits, the small signal input is iin, thesmall signal output

• is vout, what is the small signaloutput?

What is the gain?

Figure out the Vout wave form of the following circuits:

•

26

• wave form at B. Note: this is a

For the following circuit, at time 0, the switch switches from A to B, figure out the voltage"classic" question. It was asked 10 years ago and I was asked this question just recently.

• Fo the following circuit, what is the voltage value at A and B? (The Vt of the transistor is 1V).

The capacitor of the following figure is connected with two ideal MOS switches. Switches T1 and T2 are alternately turned on with a frequency

•

nt flowing

node 1 to node 2?

ffc. What is the average currefrom node 1 to node 2? What is the equivalent impedance from

You are porbing a square wave pulse in the lab that • has a

he oscilloscope to view the signal? w to

nction as buffer and

• between onehot and binary encoding? two clock

risetime of 5 ns and fall time of 2 ns. What is the minimum bandwidth of t

• What is glitch? What causes it (explain with waveform)? Hoovercome it?

• Given only two xor gates one must fuanother as inverter?

• Difference between heap and stack? Difference

• What are different ways to synchronize between domains?

• How to calculate maximum operating frequency?

27

• How to find out longest path? • How to achieve 180 degree exact phase shift?

• e follo ng FIFO and rules, how deep does the FIFO need

to be to preven u• RULES:

ency(clk_B) / 4

25% set?

• • max

T_hold = 2nS T_propagation = 10nS

•

R to second XNOR w

• few of its industry applications?

ors, one with a clock skew of 100ps f 50ps. Which one is likely to

•

ond is "ripple"

• The circle can rotate clockwise and back. Use minimum hardware

of rotating.?

• What is significance of ras and cas in SDRAM? Tell some of applications of buffer?

• Given th wit nderflow or overflow?

• frequency(clk_A) = frequ• period(en_B) = period(clk_A) * 100 • duty_cycle(en_B) =

• Difference between Synchronous and Asynchronous re• Why are most interrupts active low?

How do you detect if two 8-bit signals are same? Convert D-FF into divide by 2. (not latch) What is theclock frequency the circuit can handle, given the following information?

T_setup= 6nS• Design all the basic gates (NOT,AND,OR,NAND,NOR,XOR,XNOR) using

2:1 Multiplexer? N number of XNOR gates are connected in series such that the N inputs (A0,A1,A2......) are given in the following way: A0 & A1 to first XNOR gate and A2 & O/P of First XNOgate and so on..... Nth XNOR gates output is final output. Hodoes this circuit work? Explain in detail? Design a circuit that calculate• s the square of a number? It should not use any multiplier circuits. It should use Multiplexers and other logic?

• How will you implement a Full subtractor from a Full adder?• In a 3-bit Johnson's counter what are the unused states?

What is an LFSR .List a• What is false path? How it determine in ckt? What is the effect

of false path in ckt? Consider two similar pr• ocessand other with a clock skew ohave more power? Why? What are multi-cycle paths? You have two counters counting up to 16, built from neg-edge • DFF , First circuit is synchronous and sec(cascading), Which circuit has a less propagation delay? Why? What is difference between RAM and FIFO?

• to build a circuit to indicate the direction

• Draw timing diagrams for following circuit?

28

• Implement the fD

in no of 2 inpur XNOR

Assuming 3 inputs A,B,C?

• sible to reduce clock skew to zero? Explain your

•

ollowing circuits: 3 input NAND gate using min no of 2 input NANGates 3 input NOR gate using min no of 2 inpur NOR Gates 3 input XNOR gate using mGates

Is it posanswer? Give the circuit to extend the falling edge of the input by 2 clock pulses? The waveforms are shown in the following figure.

• yes,

For the Circuit Shown below, what is the Maximum Frequency of Operation? Are there any hold time violations for FF2? If how do you modify the circuit to avoid them

• nput xor's are needed to implement 16 input parity

• number

? • en Synchronous, Asynchronous & Isynchronous

•

• Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch? • How to implement a Master Slave flip flop using a 2 to 1 mux?

How many 2 igenerator? Design a circuit for finding the 9's compliment of a BCD using 4-bit binary adder and some external logic gates?

• What is Difference between write back and write through cacheDifference betwecommunication?

• What are different ways to Multiply & Divide? Design a black box whose input clock and output relationship asshown in attachment.

• umentation Amplifier(IA) and what are all the

gn?

• m and maximum frequency of dcm in spartan-3 series fpga?

• Explain zener breakdown and avalanche breakdown? What is Instradvantages?

• What is the basic difference between Analog and Digital Desi• What is ring oscillator? And derive the freq of operation?

What is minimu

29

• Tell me some of constraints you used and their purpose during your design?

• Suppose for a piece of code equivalent gate count is 600 and for another code equivalent gate count is

• 50,000 will the size of bitmap change? In other words will size of bitmap change it gate count change?

• What are different types of FPGA programming modes? what are you currently using ?how to change from one to another?

• Tell me some of features of FPGA you are currently using? • What is gate count of your project? • Can you list out some of synthesizable and non synthesizable

constructs? • Can you explain what struck at zero means? • Can you draw general structure of fpga? • Difference between FPGA and CPLD? • What are Digital clock manager (DCM)'s?why they are used? • FPGA design flow? • What is slice, clb, lut? • Can a clb configured as ram? • What is purpose of a constraint file what is its extension? • What is FPGA you are currently using and some of main reasons

for choosing it? • Draw a rough diagram of how clock is routed through out FPGA? • How many global buffers are there in your current fpga,what is

their significance? • What is frequency of operation and equivalent gate count of u r

project? • Tell me some of timing constraints you have used? • Why is map-timing option used? • What are different types of timing verifications? • Compare PLL & DLL? • Given two ASICs. One has setup violation and the other has hold

violation. how can they be made to work together without modifying the design?

• Suggest some ways to increase clock frequency? • What is the purpose of DRC? • What is LVS and why do we do that. What is the difference

between LVS and DRC? • What is DFT? • There are two major FPGA companies: Xilinx and Altera. Xilinx

tends to promote its hard processor cores and Altera tends to promote its soft processor cores. What is the difference between a hard processor core and a soft processor core?

• What is the significance of contamination delay in sequential circuit timing?

• When are DFT and Formal verification used? • What is Synthesis? • We need to sample an input or output something at different

rates, but I need to vary the rate? What's a • clean way to do this?

30