Solid-State Electronics 111 (2015) 67–75

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Solid-State Electronics

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Short channel amorphous In–Ga–Zn–O thin-film transistor arrays forultra-high definition active matrix liquid crystal displays: Electricalproperties and stability

http://dx.doi.org/10.1016/j.sse.2015.05.0020038-1101/� 2015 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +1 734 936 0964; fax: +1 734 615 2843.E-mail address: kanicki@umich.edu (J. Kanicki).

Soo Chang Kim a,b, Young Sun Kim a, Eric Kai-Hsiang Yu b, Jerzy Kanicki b,⇑a YE Team, Samsung Display, Asan, Chungnam 336-741, South Koreab Solid-State Laboratory, Electrical Engineering & Computer Science, University of Michigan, Ann Arbor, MI 48109, USA

a r t i c l e i n f o a b s t r a c t

Article history:Received 17 November 2014Received in revised form 18 April 2015Accepted 6 May 2015Available online 5 June 2015

Keywords:In–Ga–Zn–OThin-film transistorActive matrix liquid crystal display(AM-LCD)Short channel effectTikhonov’s regularizationAC bias-temperature stress stability(AC BTS)

The electrical properties and stability of ultra-high definition (UHD) amorphous In–Ga–Zn–O (a-IGZO)thin-film transistor (TFT) arrays with short channel (width/length = 12/3 lm) were examined. A-IGZOTFT arrays have a mobility of �6 cm2/V s, subthreshold swing (S.S.) of 0.34 V/decade, threshold voltageof 3.32 V, and drain current (Id) on/off ratio of <109 with Ioff below 10�13 A. Overall these devices showedslightly different electrical characteristics as compared to the long channel devices; non-saturation ofoutput curve at high drain-to-source voltage (Vds), negative shift of threshold voltage with increasingVds, and the mobility reduction at high gate voltage (Vgs) were observed. The second derivative methodadopting Tikhonov’s regularization theory is suggested for the robust threshold voltage extraction. Thetemperature dependency of c-value was established after taking into consideration the impact of sour-ce/drain contact resistances. The AC bias-temperature stress was used to simulate the actual operationof active matrix liquid crystal displays (AM-LCDs). The threshold voltage shift had a dependency onthe magnitude of drain bias stress, frequency, and duty cycle due to the impact ionization acceleratedat high temperature. This study demonstrates that the short channel effects, source/drain contact resis-tances and impact ionization have to be taken into account during optimization of UHD AM-LCDs.

� 2015 Elsevier Ltd. All rights reserved.

1. Introduction

Oxide semiconductors such as an amorphous indium galliumzinc oxide (a-IGZO) have been intensively studied for past tenyears especially for the application to next generation flat paneldisplays [1–3]. Superior characteristics of the a-IGZO thin filmtransistors (TFTs) as compared to the hydrogenated amorphousSi (a-Si:H) TFTs such as a high field effect mobility and trans-parency have increased their potential to become switching ordriving transistors in next generation active matrix liquid crystaldisplay (AM-LCD) or active matrix organic light emitting diode(AM-OLED), respectively. Today it has been already establishedthat a-IGZO TFTs can be processed uniformly over large-size areaat low temperature, and can use existing active-matrix arrays pro-duction infrastructure [4–6]. Recently, the high-end displays withthe ultra-high definition (UHD > �4000 � 2000 pixels), large-area(>70 in.), and high frame rate (>240 Hz) are being introduced torealize displays with more realistic visual images [7]. To fabricate

such displays, the dimension of TFTs, such as channel length andwidth, needs to be reduced to keep a high transmittance of pixelelectrodes without any decrease of pixel aperture ratio and carriermobility. Prior studies have focused on the electrical performanceor electrical stability of TFTs with the relatively large channelwidth W (>100 lm) and length L (>10 lm) to avoid the short chan-nel and source/drain contact effects. Moreover, all reports pub-lished so far on a-IGZO TFTs have focused on a single TFTstructures [8–12]. To our best knowledge, there is no report inopen literature on electrical characteristics of the a-IGZO TFTarrays with a short channel length used in the UHD AM-LCDs. Itis important to notice that the exact understanding of the funda-mental electrical properties of the a-IGZO TFT arrays with a UHDresolution is required to objectively compare the electrical behav-iors of the devices manufactured under different conditions. Recentstudies of a-IGZO electrical bias-temperature stability (BTS) haveemployed a pulsed AC gate and/or drain bias simultaneously toreflect the typical driving scheme in AM-LCDs [13–18]. However,the unipolar pulsed gate stress (e.g. 0 V to positive or negative to0 V pulse) has been often used with the source/drain grounded.Also the duty cycle, which is defined as the ratio of turn-on time

68 S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75

(ton) to frame time (tframe), was too large (25–75%) as comparedwith the typical duty cycle used in AM-LCDs ranging from 0.05%to 1% depending on the display resolution and refresh rate.

In this work, we examined in details the electrical characteris-tics of the a-IGZO TFT arrays used in the ultra-high definition dis-plays panel with relatively short channel dimension (W = 12 lm,L = 3 lm) and we studied the bias-temperature stability using theAC pulsed gate and drain bias-temperature stress to simulate theactual operation of the AM-LCDs.

Fig. 2. Schematic diagram of the pulsed gate bias and DC drain bias stressconditions used in this investigation.

0 2 4 6 8 100

10

20

30

40

-15 -10 -5 0 5 10 15 20

10-14

10-12

10-10

10-8

10-6

10-4

0.0 0.2 0.4 0.6 0.8 1.00

1

2

3

4

5

Id ( μ

A)

Vds (V)

5V

10V

15VI d( μ

A)

Vds(V)

Vgs=20V

(a)

I d(A

)

Vds=0.1V positive sweep Vds=0.1V negative sweep Vds=20V positive sweep Vds=20V negative sweep

ΔVhysteresis at Id=100pA ~ 0.05V

|ΔV(at Vds=20V)-ΔV(at Vds=0.1V)|= 1.39V

2. Experimental

A-IGZO TFT arrays were fabricated in a well-controlled manu-facturing line on the glass substrate following the similar processdescribed in [5,7]. The TFT has a back channel etched (BCE)inverted staggered bottom-gate structure. The active layers weredeposited by conventional sputtering technique with optimizedconditions so that it has In:Ga:Zn = 1:1:1 non-stoichiometric com-position. The array is composed of 100 same-structured TFTswhich are connected in parallel as shown in Fig. 1. The measuredtotal drain current (Id) was divided by 100 to obtain the averageId representing one single TFT. We verified independently thatthe average TFT characteristic is very similar to single TFT mea-sured separately. In manufacturing environment, it is very impor-tant to investigate the TFT arrays rather than single TFT propertiesfor monitoring the uniformity and quality during the manufactur-ing process. The channel width and length of individual TFT isabout 12 lm and 3 lm, respectively.

The electrical characteristics of a-IGZO TFT arrays were mea-sured at 0.2 V steps using an Agilent B1500A semiconductorparameter analyzer in ambient air and dark conditions. The sampletemperature was regulated by a heated chuck of the probe station.The measurements were repeated several times to acquire repro-ducible data. The B1500A and a HP 8114A pulse generator are con-nected to an HP E5250A switching matrix to measure the ACbias-temperature stress (AC BTS) stability [18]. An AgilentEasyExpert software routine automatically switches the E5250Abetween the HP 8114A for AC stressing and the B1500A for devicemeasurement. Fig. 2 shows the AC gate pulse ranging fromVGL = �5 V to VGH = +15 V and DC Vds (0/5/10 V) voltage used in thisstudy. Since the drain voltage continuously fluctuates (e.g. from 0 Vto 10 V with the center being common voltage) to supply theappropriate voltage corresponding the gray scale level, it is reason-able to set the drain-to-source voltage (Vds) at a constant DC volt-age during AC BTS. The accumulated stress time is defined as thetotal time a gate bias (negative or positive) is applied to the gateelectrode. The device stressing is interrupted at predeterminedtime intervals to measure the TFT transfer characteristics at stresstemperature (Tst) 70 �C.

Fig. 1. Schematic diagram of the 100-TFT-array used in this study.

(b)Vgs (V)

Fig. 3. (a) The average Id–Vds output and (b) average Id–Vgs transfer TFT character-istics are shown. The (a) inset shows no current crowding is observed close to theorigin of the output plot. The hysteresis between positive and negative sweep issmall (about 0.05 V) in the subthreshold region.

3. Results and discussion

3.1. TFT electrical characteristics

Fig. 3(a) shows typical averaged output curve at different gatebias voltage (Vgs). The inset shows no significant current crowdingat low drain-to-source voltage (Vds) close to the origin of the output

Fig. 4. (a) The average Id–Vgs transfer TFT characteristics in the linear and saturationregion of operation are shown. Solid lines are the linear fits using 10–90% linearmethod. (b) The lcal and its derivatives, extracted from the average transfercharacteristics, as a function of gate bias are shown. (c) The lcal variation with thegate-to-source bias with different temperatures ranging from 20 �C to 80 �C isshown.

Table 1Extracted a-IGZO TFT electrical properties for different Vds using 10–90% linearmethod.

Vds (V) l (cm2/V s) Vth (V) S.S. (V/dec) Ion/Ioff ratio

0.1 5.96 3.32 0.34 <109

20 6.25 1.93 0.38 <109

S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75 69

curve indicating that a good contact was formed between theCu-based source/drain electrodes and a-IGZO. However, the draincurrent (Id) at high Vds does not saturate and the non-saturationbecomes more significant at higher gate biases. This effect is com-monly observed in a-Si:H TFT [19] and polysilicon TFT [20] as wellas in a single a-IGZO TFT [8–11] (normally for L < 4 lm) when thechannel length is reduced. This non-saturation is associated withthe channel length modulation which accounts for the Id increaseresulted from the shrinking channel length with the applicationof Vds in excess of the saturation drain-to-source voltage (Vdsat).The degree of the channel length modulation is expressed by thechannel length modulation parameter k in the saturation regionas follows [21]:

Id ¼ Idsat½1þ kðVds � VdsatÞ�; ð1Þ

where Vdsat and Idsat are the Vds and Id when the slope of output

curve @Id@Vds

���Vgs¼const:

� �is first matched with the experimental data.

The parameter k values range from 0.037 V�1 at Vgs = 5 V to0.058 V�1 at Vgs = 20 V. It is speculated that the channel length mod-ulation effect increases with increasing Vgs for TFTs with short chan-nels. Fig. 3(b) shows a representative averaged transfer curve at Vds

of 0.1 V and 20 V. The hysteresis between positive and negativesweep is small (about 0.05 V) in the subthreshold region.Negligible hysteresis indicates that very small number of electronswere trapped at or near the gate dielectric (a-SiNx/a-SiOx

bilayer)/a-IGZO interface or within the a-IGZO active channel bulk.The on/off current ratio (Ion/Ioff) is over 109 with Ioff below 10�13 A.This low leakage current will prevent the voltage of the pixel capac-itor from decreasing during the TFT off-state and during changing ofthe display’s grayscale levels resulting in reduced power dissipation[3]. In general, the carrier field-effect mobility (l) and TFT thresholdvoltage (Vth) are extracted from the standard MOSFET Id–Vgs equa-tion in the linear region (Vds = 0.1 V) or/and saturation region(Vds = 20 V) [22]:

IdðlinÞ ¼ lCoxWLðVgs � VthÞVds; ð2aÞ

IdðsatÞ ¼ lCoxW2LðVgs � VthÞ2; ð2bÞ

where Cox is the gate insulator capacitance per unit area, W and Lare TFT channel width and length, respectively. As Fig. 4(a) showsthe 10–90% linear method used for extraction of the field-effectmobility and threshold voltage, considerable deviation betweenexperimental and fitted curves can be observed. Since the carrierfield-effect mobility (l) extracted by the 10–90% linear methodcan be considered as average value, the incremental field-effectmobility (lcal) corresponding to specific Vgs should also beevaluated:

lcal ¼@Id

@Vgs

� �L

WCoxVds: ð3Þ

As shown in Fig. 4(b) and (c), lcal of a-IGZO TFT arrays dependson Vgs and temperature. As the temperature increases, a largernumber of electrons that are thermally activated from the localizedtrap sites into the conduction band will contribute to a free carriersresulting in a higher mobility and smaller threshold voltage, Fig. 7[23].

Another important TFT parameter is the subthreshold swing(S.S.) that was extracted as the average of three values nearestthe maximum value in the subthreshold region using the followingequation:

S:S: ¼ d logðIdÞdVgs

� ��1

: ð4Þ

The extracted parameters from the transfer curve in the linear andsaturation regions are listed in Table 1.

From experimental data, compared to the long channel a-IGZOTFT, we observe that the negative shift of threshold voltagebetween linear (Vds = 0.1 V) and saturation regime (Vds = 20 V) isrelatively large (1.39 V), Fig. 3(b). This shift can be understood bya charge sharing model and a drain induced potential barrier low-ering (DIBL), in general, observed in a short channel MOSFETs [24].The channel charges near the source/drain contacts are controlledby the electric field originating not only from the gate, but alsofrom the source/drain electrodes. As a consequence, the portionof charges directly controlled by gate is reduced resulting in theVth lowering at high Vds. The DIBL is 69.9 mV/V, and can be calcu-lated by [25]

DIBL ¼VthjVdsðsatÞ

� VthjVdsðlinÞ

VdsðsatÞ � VdsðlinÞ

����������: ð5Þ

0.00 0.05 0.10 0.15 0.20 0.25 0.30

-96.4

-96.0

-95.6

-95.2

-10 -5 0 5 10 15

-4

-2

0

2

4

6(b)

α = α∗

dis

(×10

-12 )

α

(a)

Vth(353.15K) = 0.40α = α * (293.15K)

α = α * (353.15K)α = 0

∂2 I d/∂V

gs2 (×

10-9)

Vgs(V)

Vth(293.15K) = 2.80

Fig. 5. Threshold voltage extraction using Tikhonov’s regularization is shown. (a)Determination of the regularization parameter a, and (b) @2Id/@Vgs

2 profilesextracted with optimum regularization parameter a = a⁄ and a = 0. Extracted Vth

for two temperatures are shown.

70 S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75

Obtained DIBL value is comparable to value of the a-IGZO TFTs withL < 4 lm as shown by Baek et al. [25].

Expected Ioff (Ioff/W � 10�15 A/lm) change with Vds cannot beobserved in our experiments since measured Ioff is limited byexperimental setup.

In Fig. 4(a), the linear region Id–Vgs curve shows the non-linearbehavior with Vgs. Fitting of the experimental data to Eq. (2a) israther difficult and it will result in overestimation of Vth. Hence,the determination of Vth and mobility using the 10–90% linearmethod is not reliable for short channel TFT having non-linearId–Vgs characteristics. Other methods for threshold voltage extrac-tion must be considered. One of possible methods is the transcon-duction change method. It is well known that only thetransconductance change method can exclude the effects of theinterface state, the mobility degradation, and the parasitic resis-tance, and can approach the physically meaningful threshold volt-age [26–28]. In former studies [26–28], the transconductancechange method defined the threshold voltage as the Vgs at whichthe second derivative of Id to Vgs (@2Id=@V2

gs) is a maximum.Fig. 4(b) shows the determination of threshold voltage by the sec-ond derivative method (Vth � 2.8 V). Since the second-order differ-entiation tends to be very noisy and obtained results can vary withthe measurement conditions, we suggest extracting more stablethreshold voltage using the Tikhonov’s regularization theory [29].Tikhonov’s regularization is useful to obtain meaningful solutionestimates even for ill-conditioned measurements.

gðVÞ ¼ fAThAh þ aðBT Bþ CT CÞg

�1AT

hf k; ð6Þ

where g(V), V, f k, a, Ah, Bh, and Ch are the second derivative extractedby the regularization, Vgs, measured Id, regularization parameter,the matrix representing the second order differentiation, the iden-tity matrix, and the matrix representing the first order differentia-tion, respectively. The optimum regularization parameter a� isdefined as

disja¼a� ¼ minZjAhg � f kj

2dV � k2� �

; ð7Þ

where k is discrepancy value of which variation had no effect on theresults (not shown). Fig. 5(b) shows the second derivative profileextracted with the regularization parameter obtained in Fig. 5(a).In case of a = 0, it gives us very noisy variation, preventing thresholdvoltage extraction. Once a is optimized (a = a*), the noises are sup-pressed, resulting from the subthreshold region, and smooth curveis obtained enabling robust threshold voltage determination. Itshould be recognized that any variation in Vth extraction will impactthe calculation of other TFT parameters such as gamma (c) and K[30] values included in following equations:

lcal ¼@Id

@Vgs

� �L

WCoxVds¼ KcðVgs � VthÞc�1

: ð8Þ

Id ¼ KCoxWLðVgs � VthÞcVds: ð9Þ

The c and K can be extracted from the linear fit of the log–logplot of lcal as a function of the effective gate voltage (Vgs � Vth) inEq. (8). In other words, c is obtained from the slope, (c � 1), andK is calculated from the intercept when using the followingequation:

logðlcalÞ ¼ logðKcÞ þ ðc� 1Þ logðVgs � VthÞ: ð10Þ

Fung et al. suggested the current ratio method to extract the Vth

and c at the same time using the Eq. (9) [30]. The Vth and c aredetermined by selecting the best linear fit to the logarithm of fol-lowing drain current ratio with minimum root mean square(RMS) error:

logId

I0

� �¼ c log

Vgs � Vth

V0 � Vth

� �; ð11Þ

where I0 is the reference drain current at Vgs = V0 and chosen to bemuch larger than the subthreshold current. Fig. 6 shows the extrac-tion of Vth and c at 20 �C using the current ratio method. It should bestated that this procedure is rather complicated since the leastsquare fitting over a number of estimated Vth values have to berepeated to reach minimum RMS error. Also, when the thresholdvoltage shift with the temperature is close to or within the mea-surement resolution (0.2 V in this study), it can be difficult toextract the exact Vth.

Fig. 7 shows the evolution of threshold voltages with tempera-ture extracted with four different methods, which are: (1) 10–90%linear method; (2) second derivative method adopting Tikhonov’sregularization; (3) current ratio method; and (4) constant Id

(10�10 A) method. The second derivative method before and afteradopting Tikhonov’s regularization provided similar Vth results(not shown). The threshold voltage extracted by the second deriva-tive method has expected non-linear dependence on temperature[31].

Fig. 8(a) compares the Id fitting results with c and K valuesextracted using four different threshold voltage extraction meth-ods. Overall both current ratio and constant Id methods do not pro-vide satisfactory results. They fit relatively well the experimentaldata at low (�5 V) and high Vgs (18 V�) but showed the largestdeviation at the intermediate Vgs (8–15 V). The 10–90% linearmethod results in Id shift to the right as compared to the secondderivative method adopting Tikhonov’s regularization. The rootmean square (RMS) error of the second derivative method forabove threshold and intermediate Vgs range is the smallest of four

-1.5 -1.0 -0.5 0.0 0.5 1.0-3

-2

-1

0

1

2

-1.0 -0.5 0.0 0.5 1.01.2

1.6

2.0

2.4

2.8

3.2

(b)

Vth ≈ 0.2V

Threshold Voltage(V)

γ

γ = 1.79

(a)

0.00

0.05

0.10

0.15

0.20

0.25

0.30

Standard E

rror

log

(I d/I 0)

log ((Vgs-Vth)/(V0-Vth)

slope = γ

V0 = 5V

γ = 1.79

Fig. 6. Current ratio method for threshold voltage extraction at 20 �C is shown. (a)variation of c and standard error of the linear fit as a function of Vth, and (b) linearfitting at Vth with minimum error are shown.

290 300 310 320 330 340 350 360

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Second derivative method Current ratio method 10-90% linear method Constant Id method

Vth(V

)

Temperature (K)

Vds = 0.1V

Fig. 7. Evolution of the threshold voltages with the temperature extracted withfour different methods is shown.

0.0

0.1

0.2

0.3

0.4

(b)

Experimental 10-90% linear method Second derivative method Current ratio method Constant Id method

I d(μ

Α)

(a)

5 10 15 200.0

0.1

0.2

0.3

0.4

0.5

T=293.15K Experimental T=353.15K Experimental T=293.15K Id fitting T=353.15K Id fitting

Vgs (V)

I d(μ

A)

T=293.15 K

RS/D ≅ 6.48Ω cm2

RS/D ≅ 36.24Ω cm2

T=353.15 K

ΔVgs = RS/D× Id

Fig. 8. (a) Comparison of the Id fitting results above threshold region for c and Kvalues extracted using different threshold voltage extraction methods and (b)contact resistance estimated from the difference between the experimental Id dataand the fitted values with the threshold voltage extracted using the secondderivative based on Tikhonov’s regularization theory.

S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75 71

methods considered in this study, as shown in Table 2. From ourresults, we concluded that the second derivative method is mostsuitable for extracting the threshold voltage of the a-IGZO TFTarrays. Still, the observed parallel shift (DVgs) to the right needs

Table 2Root mean square errors between experimental data and the results fittedmethods.

Method

10–90% linear method (Fig. 4(a))Second derivative method using Tikhonov’s regularization (Fig. 5)Current ratio method (Fig. 6)Constant Id method (10�10 A) (Fig. 3(b))

to be explained. This difference between calculated and experi-mental data becomes smaller at higher temperatures as shown inFig. 8(b). We propose to explain this shift by the reduction of effec-tive gate voltage (Vgs � DVgs) due to source/drain contact resis-tances (RS/D), decreasing with the increasing temperature.Assuming that the difference between the fitting curves and exper-imental data is associated with the source/drain contact resis-tances (DVgs ¼ RS=D � Id), the RS/D decreases from 36.24 X cm2 to6.48 X cm2 when the temperature increases from 20 �C to 80 �C.It can be speculated that for the a-IGZO TFT arrays, the contactresistance decreases with the increasing temperature as it wasthe case for a-Si:H TFT [32]. It is noted that as the Vgs increases,DVgs increases slightly (D(DVgs) �0.18 V at 20 �C) since Id is Vgs

dependent (DVgs / Id / Vgs). At high temperature (80 �C), DVgs

change with the Vgs decreases below 0.10 V. To simplify the Id

and mobility fitting, constant RS/D and effective gate voltage reduc-tion DVgs at Id = 0.2 lA were used. Fig. 9(a) and (b), respectively,show the Id and mobility fitted with c and K extracted by takingthe constant effective gate voltage reduction (about 1.4 V at20 �C) into account. The Id fitting results are not perfect and thedeviation of mobility at high Vgs is relatively large. This deviation

using the c and K values obtained with four different Vth extraction

RMS (10�7) (above threshold) RMS (10�7) (8 V < Vgs < 15 V)

1.483 1.0111.070 0.7491.100 0.9971.074 0.972

5 10 15 202

3

4

5

6

7

8

9

0.0

0.1

0.2

0.3

0.4

(b)

Experimental Fitting

I d( μΑ

)

Vds = 0.1V(a)

γ = 1.50K = 1.36 cm2/Vγ+1secVth = 1.4 V

Experimental Fitting 1 Fitting 2

μ cal(c

m2 /V

sec)

Vgs

(V)

μ = 5.96 (10−90% linear method)

Fig. 9. The fitting of (a) Id and (b) lcal with the extracted c, K values for abovethreshold voltage region. Fitting 1 is calculated using only one c and K value andfitting 2 takes into consideration the impact of the source/drain contact resistancesfor each Vgs.

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

290 300 310 320 330 340 350 3601.3

1.4

1.5

1.6

Vth

(V)

Vds = 0.1V

γ

Temperature (K)

Fig. 10. Evolution of (a) threshold voltages extracted by the second derivativemethod adopting Tikhonov’s regularization theory and (b) c-value with thetemperature after considering the impact of the source/drain contact resistances.

72 S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75

comes from the mobility reduction caused by the source/drain con-tact resistances at high Vgs [9]:

lFE � l01

1þ l0WL CoxRS=DðVgs � VthÞ

; ð12Þ

where l0 is the intrinsic mobility of the a-IGZO material. We wouldlike to indicate that it is not possible to fit perfectly the mobilitywith single c and K obtained using the least square method of Eq.(8) without taking into consideration the impact of the source/draincontact resistances. The impact of this contact resistance willchange with the gate bias. Fitting 2 in Fig. 9(b) shows plot for whichthe source/drain contact impact with the gate bias was taken intoconsideration; this fitting corresponds well to experimental data.

Fig. 10 shows the evolution of threshold voltages extracted bythe second derivative method adopting Tikhonov’s regularizationtheory and c value with increasing temperature after consideringthe impact of the source/drain contact resistances. The c tends todecrease as the temperature increases as it would be expectedfrom previous studies. But, the c variation within investigated tem-perature range is relatively small range (0.1). The c can bedescribed by 2(TG/T) � 1 (a-Si:H TFT [33]) or by Tc/T + c0 (a-IGZOTFT [34]); where TG and Tc are the characteristic temperature andc0 is a fitting parameter. Characteristic temperature is associatedwith the density of states (DOS) of conduction band tail. The Tcand c0 can be extracted from the linear fit of c as a function ofthe reciprocal temperature (Tc = 150 K, c0 = 1.01). Extracted Tcvalue indicates a low density of conduction band tail states andis in agreement with Abe et al.’s results [34]. From our results,we can conclude that the dependency of the effective gate voltagereduction in short channel device needs to be taken into accountwhile extracting Vth and c.

3.2. AC bias-temperature stress stability

Fig. 11(a) and (b) shows the representative evolution of theaverage TFT transfer curves with the stress time at stress temper-ature (Tst) of 20 �C and 70 �C, respectively, under the condition ofpulsed Vgs = �5 V to +15 V, f = 240 Hz, Vds = 10 V, and dutycycle = 0.046%. The transfer curve at 70 �C shifts to the negativedirection more significantly than that at 20 �C, especially in thesubthreshold region. In this section, for simplicity and to be consis-tent with other BTS studies, we define the threshold voltage (Vth) asthe Vgs that induces a drain current (Id) of 10�10 A, e.g. constant Id

method is used for Vth extraction. The carrier mobility change withAC BTS is negligible (within 3%) within investigated stress temper-ature. The subthreshold swing changed from 0.58 V/dec to0.64 V/dec at 20 �C and from 0.56 V/dec to 0.75 V/dec at 70 �C dur-ing AC BTS indicating very negligible thermally accelerated defectgeneration in the bulk and/or interface between a-IGZO and gatea-SiNx/a-SiOx dielectric. It was found in Fig. 11(c) that the transfercharacteristics can be recovered to its initial state when array iskept unstressed for an extended period of time at room tempera-ture. This recovery can be accelerated by heating. In general, thisbehavior can be associated with the charge trapping at the inter-face between channel and gate dielectric; thermally generateddefects in the bulk are annihilated in a relatively short time with-out the electrical stress at high temperature.

To further investigate the Vth shift phenomenon by the ACpulsed gate and drain bias stress, the effects of Vds voltage, fre-quency (f), and duty cycle (ton/tframe) are examined with the stresstime. Fig. 12(a) shows that the Vth shifts more negatively with thestress time as the Vds voltage increases when Vgs = �5 V to +15 V,f = 120 Hz, duty cycle = 0.046%, and T = 70 �C are used. The Vth

10-16

10-14

10-12

10-10

10-8

10-6

10-13

10-11

10-9

10-7

-15 -10 -5 0 5 10 15 2010-14

10-12

10-10

10-8

10-6

(c)

(b)

Vgs = -5V~+15V pulseVds = 10Vf = 240HzDuty cycle = 0.046%T = 20oC

0 s 100 s 400 s 700 s 1000 s 4000 s 7000 s 10000 s

I d (A)

(a)

T = 70oC 0 s 100 s 400 s 700 s 1000 s 4000 s 7000 s 10000 s

I d (A)

Room temperature storage

Before stress After stress (10000 sec) Recovery (5 days)

I d (A)

Vgs (V)

Fig. 11. An example of typical average TFT transfer curve shift with the stress time(a) at 20 �C and (b) 70 �C, and (c) recovery behavior of TFT characteristics after anextended storage at room temperature.

-1.2

-0.8

-0.4

0.0

-1.6

-1.2

-0.8

-0.4

0.0

100 1000 10000

-1.6

-1.2

-0.8

-0.4

0.0

0.4 (c)

(b)

Vds = 0V Vds = 5V Vds = 10V

Δ Vth(V

)

(a)

f = 60Hz f = 120Hz f = 240Hz

ΔVth(V

)

Duty cycle = 0.046% Duty cycle = 10% Duty cycle = 25% Duty cycle = 50% Duty cycle = 50%, Vds = 0V

ΔVth(V

)

Accumulated stress time (s)

Fig. 12. The Vth evolution with the accumulated stress time for different (a) Vds

stress voltage, (b) frequency (f), and (c) duty cycle (ton/tframe). The AC BTStemperature was maintained at 70 �C. Stretched exponential fitting parametersare summarized in Table 3.

Table 3The stretched exponential parameters for various stress conditions used for calcu-lation of the curve fits shown in Fig. 12.

s (s) b

Vds (V) 0 2 � 107 0.345 8 � 105 0.4310 3 � 105 0.48

Frequency (Hz) 60 5 � 105 0.43120 3 � 105 0.48240 2 � 105 0.49

Duty cycle (%) 0.046 3 � 105 0.4810 6 � 105 0.3050 at Vds = 0 V 9 � 106 0.56

S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75 73

changes (DVth) with the stress time are well fitted by the stretchedexponential equation [35],

DVth ¼ DV0 1� exp � tst

s

� �b" #( )

; ð13Þ

where DV0 is the difference between stress voltage Vst (e.g.�5 V) andinitial threshold voltage Vth0 (DV0 = Vst � Vth0), s represents the char-acteristic trapping time of carriers, and b is the stretched-exponentialexponent. The extracted stretched exponential parameters (s and b),for the stress conditions used in this study, are listed in Table 3. Thestretched-exponential time dependence of DVth can be associatedwith the trapping of charges into the existing traps and/or the contin-uous redistribution of charges located in the gate dielectric or at thechannel/dielectric interface [30,35]. The Vds voltage dependence ofDVth can be explained by the electron–hole or positively charged spe-cies pairs generation at the drain side by impact ionization that isaccelerated by high drain-to-source lateral electrical field and hightemperature. The electron and positively charged species pairs aregenerated in the very short period of Vgs = +15 V under positive Vds.The existence of increasing self-heating in the channel with the stresstime and drain bias stress caused by the drain current have alreadybeen established by the thermal analysis [36–38]. The oxygen vacan-cies (Vo

2+) are possible candidates of positively charged species[39,40]. The generated electrons are swept into the drain electrodeby the positive drain voltage, but positively charged species areattracted and then trapped near the channel/gate dielectric interfacein the period of Vgs = �5 V which takes most of the time (toff = 8.33ms � tframe) during each frame except for a very short positive pulse(e.g. at UHD 120 Hz, ton = 3.9 ls). Therefore the stretched-exponential modeling with Vst = �5 V is appropriate. The averagetransfer curve at Vds = 0 V (e.g. no impact ionization) also shifts to

the direction of negative bias, but this is only due to pulsed AC gatebias without supplying additional trapping charges at the channel/-gate dielectric interface. We speculate that the Vth shift is mainlyattributed to the charge trapping and can be well described bystretched-exponential model. The nearly full recovery of TFT charac-teristics to their initial state with negligible degradation of sub-threshold swing at high temperature which may be caused by thepositively charged species generated in the bulk by the impact ioniza-tion supports this speculation.

To examine the influence of the number of turn-on per one gateline [Non = frequency (f) � accumulated stress time in s (tst)] andlength of turn-on time during a given stress time (tst) on the impactionization, the effects of frequency and duty cycle on DVth wereinvestigated. Since high frame-rate devices (e.g. 240 Hz) have veryshort turn-on time (e.g. �1.9 ls), it needs to be checked whether

74 S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75

such a short time is sufficient to induce the impact ionization dur-ing the drain bias. On the other hand, if the turn-on time isextended at the same refresh rate, the influence of positive gatebias during the pulsed gate stress cannot be ignored in attractingthe electrons generated by the impact ionization. As the frequencyincreases from 60 Hz to 240 Hz, the turn-on time (ton) per a framedecreases from 7.7 ls to 1.9 ls but the number of turn-onincreases from 6 � 105 to 24 � 105 during the stress time of10,000 s. Fig. 12(b) shows that as the frequency increases, the mag-nitude of DVth increases when Vgs = �5 V to +15 V, Vds = 10 V, dutycycle = 0.046%, and T = 70 �C are used for AC BTS. It was found thateven a short turn-on time of 1.9 ls at 240 Hz is sufficient to gener-ate the electron–hole (or positively charged species) pairs by theimpact ionization. These results are consistent with Chen et al.’sreport [41]; in their study turn-on time varied from 1 ls to100 ls and the DVth s were independent of turn-on time in theinvestigated range. Therefore, the negative shift of threshold volt-age during AC bias-temperature stress should be carefully consid-ered to realize a high frame-rate driving in UHD AM-LCDs.

Fig. 12(c) shows the effect of duty cycle on the DVth forVgs = �5 V to +15 V, Vds = 10 V, f = 120 Hz, and T = 70 �C AC BTS con-ditions. The increment of duty cycle at the same refresh rate canshow the effect of extended positive gate bias on the electronand/or positively charged species trapping. The DVth shifts morenegatively for duty cycle of 10% in comparison to 0.046%. Thiscan be attributed to the generation of larger number of electron–hole (positively charged species) pairs over the extended periodof time, e.g. from 3.9 ls to 0.83 ms at UHD 120 Hz, and/or the holetrapping at the channel/gate dielectric interface induced by alonger negative gate bias. However, when the duty cycle increasesup to 25% and 50%, the DVth first shifts negatively but eventuallyturns to the positive direction after 4000 s. This behavior can beassociated with the competitive processes between the electrontrapping by a positive gate bias during an extended turn-on timeand trapping of more positively charged species generated by theimpact ionization during a corresponding turn-on time. Whenthe same stress condition of 50% duty cycle is applied atVds = 0 V, the DVth shifts positively as shown in Fig. 12(c) due to lar-ger positive gate bias stress during AC gate pulse (VGH +15 V > VGL

�5 V). These results clearly indicate the important role of drainbias stress in generating the electron–hole pairs needed for thehole trapping at the channel/gate dielectric interface.

Long channel a-IGZO TFTs have also been exhibiting the asym-metrical degradation behavior between source and drain elec-trodes due to the different stress voltage and temperaturedistribution [37,38,40,42–44]. This asymmetrical degradationbetween source and drain electrodes can be simply checked byconfirming the difference between the forward mode and reversemode of transfer curve before and after stress [44–46]. The forwardmode of transfer curve is defined when the source-drain electrodesremain in the same position as that of the stressed condition andthe reverse mode is defined when the source-drain electrodes areinterchanged with respect to stressed condition. The forward andreverse mode of transfer curve of TFT arrays used in this study doesnot show any differences before and after stress (not shown). Thissymmetrical degradation behavior between source and drain elec-trodes is mainly associated with the charge trapping of holes whichare relatively uniformly distributed in the short channel devices.Also, the temperature is more evenly distributed in short channelin comparison to long channel TFTs [38].

4. Conclusions

In this work, the electrical characteristics and stability of theultra-high definition a-IGZO TFT arrays were examined.

Compared to the long channel length TFTs, the a-IGZO TFT arrayselectrical characteristics showed short channel effects. Thenon-saturation of output curve at high Vds was explained by thechannel length modulation caused by effective channel lengthreduction as the channel length decreases. The negative shift ofthreshold voltage in the average transfer curve with the increasingVds was observed and is described by the drain-induced-barrierlowering (DIBL). To obtain robust and physically meaningfulthreshold voltage, the second derivative method adoptingTikhonov’s regularization theory was introduced and comparedwith the other Vth extraction methods. The difference betweenthe Id experimental and fitted data as a function of Vgs was consid-ered as the reduction of effective gate voltage by the source/draincontact resistances. The mobility reduction at high Vgs is alsobelieved to be associated with the source/drain contact resistancesinfluence as the channel length decreases. The extracted c valuesshowed only slight temperature dependency by taking into consid-eration the impact of source/drain contact resistances. To simulatethe actual operation of AM-LCDs, the AC bias-temperature stressstability of TFT arrays was investigated. The Vth has a dependencyon the magnitude of drain bias stress, frequency, and duty cycle athigh temperature. The main mechanism responsible for thresholdvoltage shift appears to be associated with the hole trapping atthe channel/gate dielectric interface over long negativegate-biased time; the electron–hole (positively charged species)pairs generated by the thermally accelerated impact ionizationare at the origin of holes creation. This study showed that the elec-trical characteristics and stability of the UHD a-IGZO TFT arrays tobe used for high frame-rate high-end displays should be thor-oughly investigated. The short channel effects, source/drain con-tact resistances and impact ionization should be taken intoconsideration when optimization of pixel design for future UHDdisplays is performed.

Acknowledgment

This research was supported at the University of Michigan bySamsung Display Co., Ltd. under the Visiting Scholar Program 2014.

References

[1] Nomura K, Ohta H, Takagi A, Kamiya T, Hirano M, Hosono H. Room-temperature fabrication of transparent flexible thin-film transistors usingamorphous oxide semiconductors. Nature 2004;432:488–92.

[2] Park JS, Maeng WJ, Kim HS, Park JS. Review of recent developments inamorphous oxide semiconductor thin-film transistor devices. Thin Solid Films2012;520:1679–93.

[3] Park JS, Kim H, Kim ID. Overview of electroceramic materials for oxidesemiconductor thin film transistors. J Electroceram 2014;32:117–40.

[4] Lu HH, Ting HC, Shih TH, Chen CY, Chuang CS, Lin Y. 32-inch LCD panel usingamorphous indium–gallium–zinc–oxide TFTs. In: SID symp int tech papers;2010. p. 1136–1139.

[5] Song J, Lim JH, Ahn BD, Lee J. High mobility oxide TFTs for future LCDapplications. In: SID Symp Int Tech Papers; 2013. p. 93�96.

[6] Park JS. Oxide TFTs for AMOLED TVs. Inf Disp 2013;29:16–9.[7] http://www.samsunghub.com/2010/11/08/samsung-develops-70-inch-lcd-

panel-using-oxide-semiconductor-tech/.[8] Heo YW, Cho KM, Sun SY, Kim SY, Lee JH, Kim JJ, et al. Effects of channel

dimensions on performance of a-InGaZnO4 thin-film transistors. J Vac SciTechnol, B 2011;29:021203.1–3.7.

[9] Cho EN, Kang JH, Yun I. Contact resistance dependent scaling-down behavior ofamorphous InGaZnO thin-film transistors. Curr Appl Phys 2011;11:1015–9.

[10] Park JS. Characteristics of short-channel amorphous In–Ga–Zn–O thin filmtransistors and their circuit performance as a load inverter. J Electroceram2012;28:74–9.

[11] Kang DH, Han JU, Mativenga M, Ha SH, Jang J. Threshold voltage dependenceon channel length in amorphous–indium–gallium–zincoxide thin-filmtransistors. Appl Phys Lett 2013;102:083508.1–8.4.

[12] Ha SH, Kang DH, Kang I, Han JU, Mativenga M, Jang J. Channel lengthdependent bias-stability of self-aligned coplanar a-IGZO TFTs. J Disp Technol2013;9:985–8.

S.C. Kim et al. / Solid-State Electronics 111 (2015) 67–75 75

[13] Cho IT, Lee JM, Lee JH, Kwon HI. Charge trapping and detrappingcharacteristics in amorphous InGaZnO TFTs under static and dynamicstresses. Semicond Sci Technol 2009;24:015013.1–3.6.

[14] Kim SJ, Lee YW, Lee SY, Woo JS, Kwon JY, Han MK, et al. The effect of AC biasfrequency on threshold voltage shift of the amorphous oxide TFTs. In: SIDSymp Int Tech Papers; 2011. p. 1195�1197.

[15] Chen TC, Chang TC, Hsieh TY, Lu WS, Jian FY, Tsai CT, et al. Investigating thedegradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor. Appl Phys Lett 2011;99:022104.1–4.3.

[16] Yang CY, Huang SC, Chiu HL, Hsieh T, Yeh BL, Lin CS, et al. AC gate-drain-biasstress study of amorphous indium gallium zinc oxide thin film transistors forGOA applications. In: SID Symp Int Tech Papers; 2012. p. 1126�1128.

[17] Kim SJ, Lee SY, Lee YW, Kuk SH, Kwon JY, Han MK. Effect of charge trapping/detrapping on threshold voltage shift of IGZO TFTs under AC bias stress.Electrochem Solid State Lett 2012;15(4):H108–10.

[18] Yu EKH, Abe K, Kumomi H, Kanicki J. AC bias-temperature stability of a-InGaZnO thin-film transistors with metal source/drain recessed electrodes.IEEE Trans Electron Devices 2014;61(3):806–12.

[19] Wie CR. Nonsaturating drain current characteristic in short-channelamorphous–silicon thin-film transistors. IEEE Trans Electron Devices2010;57(4):846–54.

[20] Fortunato G, Valletta A, Gaucci P, Mariucci L, Brotherton SD. Short channeleffects in polysilicon thin film transistors. Thin Solid Films 2005;487:221–6.

[21] Smith KC, Sedra AS. Microelectronic circuits. New York: Oxford UniversityPress; 2004.

[22] Kanicki J, Martin S. Hydrogenated amorphous silicon thin-film transistors. In:Kagan CR, Andry P, editors. Thin-film transistors. New York: Dekker; 2003. p.71–137.

[23] Chen C, Abe K, Kumomi H, Kanicki J. Density of states of a-InGaZnO fromtemperature-dependent field-effect studies. IEEE Trans Electron Devices2009;56(6):1177–82.

[24] Taur Y, Ning TH. Fundamentals of modern VLSI devices. Cambridge: CambridgeUniversity Press; 1998.

[25] Baek G, Abe K, Kumomi H, Kanicki J. Scaling of a-InGaZnO TFTs and pixelelectrode for AM-LCDs. In: AM-FPD 19th int workshop; 2012. p. 13�16.

[26] Wong HS, White MH, Krutsick TJ, Booth RV. Modeling of transconductancedegradation and extraction of threshold voltage in thin oxide MOSFETs. SolidState Electron 1987;30(9):953–68.

[27] Booth RV, White MH, Wong HS, Krutsick TJ. The effect of channel implants onMOS transistor characterization. IEEE Trans Electron Devices 1987;ED-34:2501–9.

[28] He J, Xi X, Chan M, Cao K, Hu C, Li Y, et al. Normalized mutual integraldifference method to extract threshold voltage of MOSFETs. IEEE ElectronDevice Lett 2002;23:428–30.

[29] Choi WY, Kim H, Lee B, Lee JD, Park BG. Stable threshold voltage extractionusing Tikhonov’s regularization theory. IEEE Trans Electron Device2004;51(11):1833–8.

[30] Fung TC, Abe K, Kumomi H, Kanicki J. Electrical instability of RF sputteramorphous In–Ga–Zn–O thin-film transistors. J Disp Technol 2009;5(12):452–61.

[31] Kim SC, Kim YS, Kanicki J. Density of states of short channel amorphousInGaZnO TFT arrays fabricated using manufacturable processes. Jpn J ApplPhys 2015;54(5):051101.1–1.7.

[32] Kuo A. High performance hydrogenated amorphous thin-film transistorstructure. University of Michigan Ph.D. dissertation; 1997, p. 121.

[33] Kishida S, Naruke Y, Uchida Y, Matsumura M. Theoretical analysis ofamorphous-silicon field-effect-transistors. Jpn J Appl Phys 1983;22(3):511–7.

[34] Abe K, Sato A, Takahashi K, Kumomi H, Kamiya Hosono TH. Mobility- andtemperature-dependent device model for amorphous In–Ga–Zn–O thin-filmtransistors. Thin Solid Films 2014;559:40–3.

[35] Libsch FR, Kanicki J. Bias-stress-induced stretched-exponential timedependence of charge injection and trapping in amorphous thin-filmtransistors. Appl Phys Lett 1993;62:1286–8.

[36] Fujii M, Uraoka Y, Fuyuki T, Jung JS, Kwon JY. Experimental and theoreticalanalysis of degradation in Ga2O3–In2O3–ZnO thin-film transistors. Jpn J ApplPhys 2009;48. 04C091.1–1.6.

[37] Urakawa S, Tomai S, Ueoka Yamazaki YH, Kasami M, Yano K, Wang D, et al.Thermal analysis of amorphous oxide thin-film transistor degraded bycombination of joule heating and hot carrier effect. Appl Phys Lett2013;102:053506.1–6.4.

[38] Kim JI, Chang KS, Kim DU, Cho IT, Jeong CY, Lee D, et al. Thermoreflectancemicroscopy analysis on self-heating effect of short-channel amorphous In–Ga–Zn–O thin film transistors. Appl Phys Lett 2014;105:043501.1–1.4.

[39] Oh H, Hwang CS, Pi JE, Ryu MK, Park SHK, Chu HY. Unusual instability mode oftransparent all oxide thin film transistor under dynamic bias condition. ApplPhys Lett 2013;103:123501.1–1.5.

[40] Lee D, Jeong CY, Song SH, Xiao-Shi J, Kim JI, Lee JH, et al. Asymmetricaldegradation behaviors in amorphous InGaZnO thin-film transistors undervarious gate and drain bias stresses. J Vac Sci Technol, B2015;33(1):011202.1–2.8.

[41] Chen TC, Chang TC, Hsieh TY, Tsai MY, Chen YT, Chung YC, et al. Self-heatingenhanced charge trapping effect for InGaZnO thin film transistor. Appl PhysLett 2012;101:042101.1–1.4.

[42] Hsieh TY, Chang TC, Chen TC, Tsai MY, Chen YT, Chung YC, et al. Origin of self-heating effect induced asymmetrical degradation behavior in InGaZnO thin-film transistors. Appl Phys Lett 2012;100:232101.1–1.4.

[43] Hsieh TY, Chang TC, Chen TC, Tsai MY, Chen YT, Jian FY, et al. Investigating thedrain-bias-induced degradation behavior under light illumination for InGaZnOthin-film transistors. IEEE Electron Dev Lett 2012;33(7):1000–2.

[44] Seo SB, Park HS, Jeon JH, Choe HH, Seo JH, Yang S, et al. Drain bias effect on theinstability of amorphous indium gallium zinc oxide thin film transistor. ThinSolid Films 2013;547:263–6.

[45] Dey A, Allee DR, Clark LT. Impact of drain bias stress on forward/reverse modeoperation of amorphous ZIO TFTs. Solid State Electron 2011;62:19–24.

[46] Jeong CY, Lee D, Song SH, Kim JI, Lee JH, Kwon HI. A study on the degradationmechanism of InGaZnO thin-film transistors under simultaneous gate anddrain bias stresses based on the electronic trap characterization. Semicond SciTechnol 2014;29:045023.1–3.6.