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Abstract— Within this special session paper we present a

selection of our designed and prototyped silicon integrated circuits realized in SiGe BiCMOS technology at 10 GHz and 35 GHz. The circuits have been prototyped within European Space Agency contracts that SIRC implements as well as in an NCBiR project. The ICs, prototyped in IHP SG25V and SG13S technologies, have been mounted as chip on board and measured for their parameters. In this paper, we show a selection of circuit designs, prototyped ICs, mounting and achieved measurement results.

Index Terms— Integrated circuits, SiGe BiCMOS, space applications, X band, Ka band, integrated receiver, integrated transceiver

I. INTRODUCTION

A D A R systems find their application both in the civil and military domains [1]. Traditionally, front-end

components for radar systems have been designed and fabricated in III-V semiconductor technologies, e.g. GaAs, which ensure high achievable output powers and low receiver noise figures. However, their main disadvantages are high cost, low energy efficiency and relatively large size of realized components [2], which renders their application ineffective outside of military or special use segments. Currently, with expansion of mass market and commercial domain applications, more and more attention is paid to the reduction of cost and size of the elements as well as to the reduction of power consumption in radar systems. Especially, such requirements are important for systems with many antenna elements, whereby achievement of low cost, low size and low power targets may be attained by changing the design and production technology for active elements from III-V to silicon [3]. Potential application areas include space sector, miniaturized radars mounted on drones, autonomous industrial vehicles or in toys, used for navigation and obstacles avoidance, which would benefit from more compact size, lower energy consumption and ultimately much lower cost at high production volumes.

This paper was submitted on 5th April 2016. Presented work was supported

by the European Space Agency within Polish Industry Incentive Scheme (ESA Contract No. 4000112604/14/NL/CBi) and by NCBiR (National Center for Research and Development) in Poland under Grant INNOTECH-K3/HI3/14/227478/NCBR/14.

R. Piesiewicz is with SIRC Sp. z o.o., Gdynia, Poland (e-mail: r.piesiewicz@si-research.eu).

In this context, a very attractive alternative to GaAs components offer integrated circuits based on silicon technology, e.g. SiGe BiCMOS, which are characterized by high integration levels, low power consumption, simple integration of digital control and low price at high production volume [4]. Development of silicon technologies for radar components has been very dynamic recently, whereby silicon technology has reached the technological and commercial maturity level that allows realization of analog front-end components with comparable functional parameters to the ones in GaAs, though at lower cost, much more compact size and much better energy efficiency. It can be expected that silicon circuits will push out and replace GaAs components in many applications at microwave and mm-wave frequencies [5], especially for low-power radar applications, in receiver paths of phased-array and multi-channel radar systems in space and earth-bound applications, as well as in commercial, low power compact radar solutions.

The aim of this paper is to show design and measurement results of prototyped MMICs (Monolithic Microwave Integrated Circuits), implemented in SiGe BiCMOS technology and dedicated to operate in the 10 GHz and 35 GHz bands. The reported work has been conducted within a publicly co-funded R&D project within the framework of INNOTECH III program of the National Center for Research and Development in Poland as well as in ESA financed projects within Polish Industry Incentive Scheme.

II. X-BAND TRANSCEIVER

A. Schematic Diagram

A schematic block diagram of the targeted complete MMIC FMCW radar transceiver is depicted in Fig. 1.

Fig. 1. Block diagram of the X-band FMCW radar transceiver

Silicon Integrated Circuits for Space Applications

R. Piesiewicz

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978-1-5090-2214-4/16/$31.00 ©2016 IEEE

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The Tx (transmitter) path of the MMIC is composed of a) VCO (Voltage Controlled Oscillator), designed to cover 8-12 GHz band with 4 sub-bands to achieve desired noise parameters, b) PA (Power Amplifier) with regulated gain and maximum 15 dBm output power, c) Frequency Divider 1/8 to deliver the signal to an external PLL (Phase Locked Loop) circuit for the control of the VCO signal. The Rx (receiver) path of the MMIC is composed of a) LNA (Low Noise Amplifier) with regulated gain, b) Double balanced quadrature mixers, c) Phase Shifter 0/90 to deliver the VCO signal to the mixers, d) Output Buffers, which are low gain amplifiers that provide for impedance matching between the mixers and external circuitry.

B. Operational Parameters

The specification of the operational parameters of the targeted FMCW radar transceiver is compliant with CEPT [6] and ITU-R [7] regulations for short-range devices. The MMIC parameters are presented in Table I.

TABLE I. TRANSCEIVER PARAMETERS

MMIC transceiver parameters

Parameter Value

Frequency range 8-12 GHz

Output Tx power 0-15 dBm

Rx path gain 0-20 dB

Rx noise figure < 5 dB

RF Input Rx impedance 50 Ohm

RF Output Tx impedance 50 Ohm

IF Output Rx impedance 500 Ohm

Supply voltage 3.3 V

Power consumption < 500 mW

C. MMIC Technology

The designed transceiver structures have been prototyped using IHP SiGe BiCMOS SG25V technology in the MPW service [8]. Produced bare dies have be packaged in QFN (quad-flat no-leads) [9], the packaging technology, which is industry standard, compatible with SMT (Surface Mount Technology) process [10]. The IHP silicon technology has been selected for its superior stability, competitive silicon semiconductor technology parameters and its availability both for short prototyping runs at an reasonable price and full-scale industrial engineering runs for subsequent market deployment.

First structures, including the VCO and the LNA were designed and sent for production in November 2014. They were delivered by IHP in March 2015. The photograph of the delivered chips is shown in Fig. 2. They were packaged in QFN, shown in Fig. 3 and then mounted on dedicated demonstration boards, shown in Fig. 4. Subsequently, they were measured for their electrical parameters. On-board measurements were conducted at the Warsaw University of Technology in the Radiocommunications Division and covered S parameters, noise figure, gain and linearity.

Fig. 2. ICs delivered from IHP

Fig. 3. QFN mounted IC

Fig. 4. Multi-layer demonstration board with QFN mounted circuitry

The demonstration board is a laminated multi-layer

exploiting Rogers RO3003 for mounting high-frequency structures and conventional FR4 for mechanical stabilization and DC/IF connections and circuitry.

III. KA-BAND RECEIVER

A schematic block diagram of the designed receiver (RX) monolithic microwave integrated circuit (MMIC), combining a low noise amplifier (LNA), quadrature mixers, a poly-phase filter, a local oscillator (LO) buffer for 35.5-36 GHz band is depicted in Fig. 5.

Fig. 5. Block diagram of the Ka-band radar receiver

Layout of the receiver is shown in Fig. 6. The receiver has been designed to cover the 35.5 – 36 GHz band, have gain of 20 dB, noise figure smaller than 3 dB and consume less than 60 mW of power.

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Fig. 6. Layout of the Ka-band radar receiver

The receiver has been prototyped using IHP SG13S process and the ICs have been mounted as chip-on-board using wire-bonding. The prototyped and wire-bonded ICs are shown in Fig. 7.

Fig. 7. Prototyped and mounted Ka-band receiver

IV. DESIGN AND MEASUREMENT RESULTS

In the following sub-sections, design and measurement results of the critical building blocks of the X-band FMCW MMIC transceiver are discussed. They include VCO and LNA. ADS design environment produced by Keysight Technologies was used for circuits design, simulations and optimization, while for their layouting TexEDA produced by TexEDA Design GmbH was employed.

A. VCO

The designed VCO is a differential one operating as a buffered Colpitts oscillator as depicted in Fig. 8. The circuit uses a pair of bipolar transistors and integrated inductors, which together with MIM (metal-insulator-metal) capacitors make a resonant circuit. In order to enable VCO tuning, varactor diode is used, available in silicon technology. Designed VCO has been simulated both in the time domain (transient) and the frequency domain (HB – harmonic balance). The VCO is powered by a 3.3V supply and in a static case consumes 10.2 mA of current.

A. Fig. 8. Schematic diagram of the VCO

The simulated tuning characteristic of the VCO as a

function of the varactor diode capacitance is shown in Fig. 9.

Fig. 9. VCO tuning vs. varactor diode capacitance

The simulated output power of the VCO as a function of the operation frequency is depicted in Fig. 10. The simulated phase noise of the VCO is shown in Fig. 11. for the 11.5 GHz operation.

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The VCO measured current consumption amounts to 11mA @ 3.3V. The achieved tuning range is between 9.7GHz and 10.98GHz. The measured peak output power is 6.3dBm @ 10.6GHz. The measured phase noise amounts to -113dBc @ 1MHz. The measured VCO tuning range and output power are shown in Fig. 12 and Fig. 13, respectively. The achieved S-shaped VCO tuning range characteristic is typical of voltage controlled oscillators, due to the real varactor diode behaviour, unaccounted for in simulations where an ideal element was assumed. The specific shape of the VCO output power is due to the influence of the output buffer that follows a typical gain characteristic of an amplifier. The VCO exhibits tuning range of 1.28GHz which is in good agreement with simulation based on rudimentary varactor model. The oscillation frequency was shifted down roughly by 1GHz but it was also expected. The design goal was to achieve centre frequency of 10.6GHz. The output power of the VCO followed by buffers reaches 6.2dBm at 10.6GHz which fits the project requirements.

Fig. 10. VCO output power vs. operation frequency

Fig. 11. VCO phase noise at 11.5 GHz operation

Fig. 12. VCO tuning range - measured

Fig. 13. VCO output power – measured

B. LNA

The designed LNA is a transformer loaded amplifier in a cascode configuration with emitter degeneration as depicted in Fig. 14. The selected configuration improves input-output isolation as there is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a much higher bandwidth. The input matching circuit accounts for both a bond-wire, modelled as an inductor as well as the input pad capacitance. The input matching includes ESD protection diodes which ensure the robustness of the circuit thus not influencing its high frequency performance. LNA design includes polarizing circuits for both cascode transistors which are not shown in the schematic. The transformer load ensures galvanic separation from the following stages giving us freedom in the choice of their biasing. The simulated LNA consumes 4.9 mA of current from the 3.3 V supply source.

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Fig. 14. Schematic diagram of LNA

The simulated reflection properties of the LNA are shown in Fig.15. The S11 is below -10 dB in the whole X (8-12 GHz) band. The S22 is not as wideband, but it is sufficient, since the LNA output will be matched to the mixers input at a later design stage.

Fig. 15. Reflection at the input and output of the LNA

The simulated LNA gain is depicted in Fig.16. The

maximum gain of 14 dB is reached at 10 GHz. The 3 dB band covers the whole X band, which fulfills design targets. The simulated noise figure of the LNA is presented in Fig.17. The minimum NF, amounting to 1.9 dB is achieved for 9 GHz. The noise figure is below 2.4 dB in the whole X band. The stability factor of the amplifier is above 1 in the whole X band, which guarantees unconditional stability of the LNA. Linearity and 1 dB compression point are shown in Fig. 18.

Fig. 16. LNA gain

Fig. 17. LNA noise figure

Fig. 18. Linearity and 1 dB compression point of the LNA

The LNA test-structure which was fabricated consisted of

the previously reported LNA and a buffer stage. The buffer stage was designed to ease the measurements as it included bond-wire compensation network. It introduced also additional 4dB of gain in simulation. The measured LNA current consumption is 5.4mA @ 3.3V. The measured LNA peak gain amounts to 17.4dB @ 9.35GHz. The achieved 3dB bandwidth

7 8 9 10 11 12 136 14

-30

-25

-20

-15

-10

-5

-35

0

freq, GHz

dB

(S(1

,1))

dB

(S(2

,2))

7 8 9 10 11 12 136 14

4

6

8

10

12

14

2

16

freq, GHz

dB(S

(2,1

))

m1

m3m4

m1freq=dB(S(2,1))=14.006

10.00GHzm3freq=dB(S(2,1))=10.918

8.000GHzm4freq=dB(S(2,1))=11.392

12.00GHz

7 8 9 10 11 12 136 14

2.0

2.2

2.4

2.6

2.8

3.0

1.8

3.2

freq, GHz

NF

min

nf(2

)m2

m2freq=nf(2)=1.990

10.00GHz

10.00 GHz

Fundamental Frequency

-25 -20 -15 -10 -5 0 5-30 10

8

9

10

11

12

13

14

7

15

Fund. Output Power, dBm

m1

m2

Transducer Power Gain, dB

1.095 1.613

Gain Compressionbetween markers, dB

Output Powerat Marker m2, dBm

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is 7.67GHz – 11.16GHz. The measured NF is 2.95dB @ 9.6GHz. The measured 1dB ICP is -7dBm, while 1dB OCP is 9.3dBm.

The measured S21, S11 and S22 parameters are shown in Fig. 19-21, respectively.

Fig. 19. LNA S21 – measured

Fig. 20. LNA S11 – measured

Fig. 21. LNA S22 – measured

The measured S21 for different supply voltage is illustrated

in Fig. 22.

Fig. 22. LNA S21 – measured for different supply voltages: 3.3V, 3.0V,

3.6V

The measured NF for different supply voltages is depicted

in Fig. 23.

Fig. 23. LNA NF – measured for different supply voltages: 3.3V, 3.0V,

3.6V

The measured linearity of the LNA is shown in Fig. 24.

Fig. 24. LNA linearity – measured

The LNA frequency response was shifted down by 650MHz. Along with the gain the input matching was also shifted down. This phenomenon was investigated and it was found that the length of input bond-wires was underestimated as well as some additional parasitic of on-chip feeding lines caused the shift. The results of this investigation were taken into account in the redesign phase and necessary changes were introduced. The noise figure is about 1dB higher than simulated, however, the measured results are valid for the chip-on-board. This means the NF is affected by the losses of feeding lines and SMA connectors which could not be

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deembeded. This let us assume that the real NF can be lower by about at least 0.5dB which would be a very good result.

V. CONCLUSION

Design and measurement results of critical building blocks, i.e. VCO and LNA of the MMIC FMCW transceiver in SiGe BiCMOS technology are reported. The structures have been prototyped using IHP SG25V silicon technology. The achieved measurement results from the first prototyping run are in good agreement with the simulated parameters and characteristics. Conclusions from the measurement campaign will be considered in the subsequent prototyping runs to arrive at the targeted FMCW transceiver structure.

ACKNOWLEDGMENT

The presented R&D work has been conducted within the framework of the publicly co-financed project (INNOTECH-K3/HI3/14/227478/NCBR/14), entitled “Silicon microwave integrated circuits for the 10 GHz band” (Polish: “Krzemowe mikrofalowe układy scalone na pasmo 10 GHz”) from the INNOTECH HiTECH III program of the National Center for Research and Development in Poland as well as within European Space Agency project (ESA Contract No. 4000112604/14/NL/CBi), entitled “Integrated low-power Ka-band receiver in SiGe BiCMOS technology for remote sensing applications” from the Polish Industry Incentive Scheme.

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[2] Gaetan Prigent, et al, (2010). Trend on Silicon Technologies for Millimetre-Wave Applications up to 220 GHz, Microwave and Millimeter Wave Technologies from Photonic Bandgap Devices to Antenna and Applications, Igor Minin (Ed.), ISBN: 978-953-7619-66-4, InTech, DOI: 10.5772/9066

[3] E. Brookner, Phased arrays and radars – past, present and future, Microwave Journal, January 2006

[4] John D. Cressler, SiGe Technology: New Research Directions and Emerging Application Opportunities, IEEE Electron Devices Society Distinguished Lecture, IEEE Southeastern Michigan Chapter IV, Ann Arbor, Mi, May 2009

[5] Gabriel M. Rebeiz, Recent Developments in SiGe and CMOS Phased-Arrays for Millimeter Wave Applications, Phoenix Talk, April 2012, UCSD

[6] CEPT ERC Recommendation 70-03 E, RELATING TO THE USE OF SHORT RANGE DEVICES (SRD), Październik 2004

[7] ITU-R SM.2153-2, Technical and operating parameters and spectrum use for short range radiocommunication devices, June 2011

[8] http://www.ihp-microelectronics.com/en/services/mpw-prototyping/sigec-bicmos-technologies.html

[9] Andy Longford, (2005) "Chip packaging challenges … a roadmap based overview", Microelectronics International, Vol. 22 Iss: 2, pp.17 – 20

Trybula, W. J. and Trybula, M. 2005. Surface Mount Technology. Encyclopedia of RF and Microwave Engineerin