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Hewlett PackardLabs
Silicon Photonics PDK Development
M. Ashkan SeyediLarge-Scale Integrated Photonics
Hewlett Packard Labs, Palo Alto, CA
Outline
–Motivation of Silicon Photonics
–Approach to PDK development
–Theory
–Design
–Optical Components
–Experimental Results
–PDK Results
–Future Work
HPE “The Machine”
Electrons
Photons
Ions
Compute
Communicate
Store
Penetration of optics into communication systems
Active optical cable
Mid-board optics
Co-packaged
Integrated
Level of integration
• Multiple SOC + memory nodes
• High radix packet switch, exploiting photonic IO
• Optical switching for reconfiguration
• Intra-rack fiber in all-to-all topology
• All fiber from motherboard edge
• Inter-rack fiber, all-to-all between racks, many parallel paths
VCSEL-based
OE engineHybrid laser
HPE Photonic Roadmap
Photonic fabric for future datacenters
All-optical
logicSilicon PIC
4
The Photonic Opportunity for Data Movement Energy efficient, low-latency, high-bandwidth data interconnectivity is the core
challenge to continued scalability across computing platforms
Energy consumption completely dominated by costs of data movement
Bandwidth taper from chip to system forces extreme locality
Reduce Energy Consumption Eliminate Bandwidth Taper
K. Bergman, ECOC, 2015
0.001 0.01 0.1 1
1
10
Verbosity (byte/flop)
En
erg
y b
ud
ge
t p
er
bit (
pJ)
10 Gigaflop/J, 10% of the envelope
10 Gigaflop/J, 15% of the envelope
50 Gigaflop/J, 10% of the envelope
50 Gigaflop/J, 15% of the envelope
Exascale network energy requirementsEnd-to-end data movement energy budget:
0.25 pJ/bit
100s of pJ to 10s pJ
10s of pJ to
single pJs
pJs to fJs!
K. Bergman, ECOC, 2015
Objective: Build analytical model in Verilog-A that predictably determines electro-optical behavior of ring modulator
Inputs:Waveguide dimensions
Through/Drop GapsDC heater voltageAC modulator drive
Verilog-A modelMap physical dimensions to
analytical equation parameters
Experimentally determine device behavior dependence on input parameters by a Design
of Experiments
Proposed Approach Workflow – Dream Scenario
7
This approach allows an ‘automated PCell’ approach that would automatically modify the GDS depending on choice of foundry, design parameters, etc.
The Dream Explained
UHU Project 8
STMicroelectronics
F. Boeuf, OFC, 2015
Cadence/Lumericalhttps://www.lumerical.com/solutions/partners/cadence/
Mentor Graphics/Lumericalhttp://www.mentor.com/company/news/mentor-lumerical-optical-design
IPKISS/Lucedawww.ipkiss.org
Existing Capabilities
Remaining steps are open areas for innovation and development, as proposed in this approach
Buried Oxide
Carrier-Injection Ring Modulator
– Fabricated at Leti (Grenoble, FR) on 200mm platform
– 5 and 10 micron diameter
– ~2dB/bend loss
– Q in the range of 7-12k routinely
– Resistive heater in silicon rib
– 30 uW/GHz efficiency
– Carrier injection P-i-N diode
– ER > 10dB
– IL < 1dB
P+ Si
Intrinsic Si
N+ Si
Buried Oxide/Cladding
450nm
250nm 300nm
Ring Resonator PDK Component
–Vary gaps for a fixed coupler width to achieve critical coupling as determined by quality factor Q and extinction ratio (ER)
Gth
Gdr
Wcp
Wcp
Lumerical MODE varFDTD Simulation Setup
Lumerical Modeling – Simulation results
Simulation Results cont’d.
Cadence Virtuoso SKILL Code and Layout
Full Reticle
Ring Resonator DOE Layout
Over Coupling
Under Coupling
Gt =
15
0:2
5:3
00
Gd = 175:25:325
Extract Q and ER from Microring Spectra
Experimental Statistical Data
Extract Coupling Coefficients from Q and ER: Equations
2 2
1 2
1 2
,t a d
c a
L
Define:
2
FSR
rc
Q
1 0(1 )2
c R
2 0(1 )2a
c R
Under coupling:
Over coupling: 1 0(1 )2
c R
2 0(1 )2a
c R
From FSR
From the transmission at resonance wavelength R0
Extract Coupling Coefficients from Q and ER: Experiments
– Kappa thru decreases with Gthru
– Kappa drop decreases with Gdrop
– There are some unexpected fluctuations, especially in kappa drop
Model of Coupling Coefficient vs. Coupling Gap
Define:
2
1
2
2
t
a dL
1 1 1 1
2 2 2 2
exp( )
exp( )
t
a d
a b G c
a b G c
1 2
2
1 2
1 2
2
1 2
2
( )
Thru port
2Drop port efficiency
r
a
a
a
t d
a
QFSR
ER
Q and ER depend on delta_1 and 2a:
Therefore, we just need to store a1, b1, c1, a2, b2, c2, we could calculate delta_1 and 2a and then the Q and ER
a1 = 4.599
b1 = 0.02606
c1 = 0
a2 = 3.145
b2 = 0.02403
c2 = 0.03413
Use average of the kappa thru (or drop)
Virtuoso Simulated Ring Spectra
Gthru = 200 nmx-axis: wavelength in umy-axis: optical power in mWInput optical power = 1mW
Gdrop = 175 nmUnder-coupling
Gdrop = 225 nmCritical-coupling
Gdrop = 275 nmOver-coupling
Virtuoso Schematic SimulationsR. Wu, et al., IPR (Vancouver) 2016
Virtuoso Simulation ResultsR. Wu, et al., IPR (Vancouver) 2016
Objective: 0.25Tb/s/fiber+ with <5pJ/bit (all inclusive)
Cavity Q
High (>10k)Narrow channel spacing More channels
Long photon lifetime Lower data rate
Low (<10k)Wider channel spacing Less channels Short photon lifetime Higher data rate
Data Rate
High (>10 Gb/s)“More challenging” driver design
Higher PD sensitivity and TIA power
Low (<10 Gb/s)Easier/Cheaper driver design
Lower PD sensitivity and TIA power
What is the crosstalk between two channelsgiven a certain Q, spacing, and data rate?
Leakage due to Lorentzian lineshape
Sidebands from modulation
Spectral Blue shift of Lorentzian
Back to Back On-Chip Transceiver
5 channel Transmitter
5 channel ReceiverElectrical I/O & power
Optical
Power supply
* C. Li et. al. ISSCC’13, IEEE Design & Test’14
* K. Yu et. al. OFC’15, ISSCC’15
* C. –H. Chen et. al. OIC’13, ‘14, ‘15
23 lines at 50GHz spacing
Back-to-Back Simulation in Virtuoso: SchematicMod OutputOptical Eye
PD PhotocurrentElectrical Eye
20 Gb/s
Gthru = 200 nm Gdrop = 225 nmCritical-coupling
Eye Diagrams
10 Gb/sRing Mod: 15 Gb/s 20 Gb/s 25 Gb/s
On-Chip PD:
Laser power increased ~2dB here to improve eye quality
Device Optical Transmission
Experimental Setup
Tunable Laser 1
Photonics Chip
High-Speed Photodetector
(Discovery Semi.)
8dB/Grating IL
Anritsu BER
Anritsu PPG
D /D
+ df
DCA Scope
3dB Combiner
Tunable Laser 2
Tunable Optical Filter
Anritsu BER
Anritsu PPG
D /D
+ df
Related Experimental ResultsSeyedi, et al., Photonics in Switching 2016
Future Steps
–Work to improve uniformity and number of comb laser lines
–DWDM with packaged CMOS driver
Thank [email protected]
