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Introduction toIntroduction to
Analog-Digital-ConverterAnalog-Digital-Converter
Dr.-Ing. Frank SillDepartment of Electrical Engineering, Federal University of Minas Gerais,
Av. Antnio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil
http://www.cpdee.ufmg.br/~frank/
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Analog Digital Converter 2Copyright Sill, 2008
AgendaAgenda
Introduction Characteristic Values of ADCs
Nyquist-Rate ADCs
Oversampling ADC Practical Issues
Low Power ADC Design
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Analog Digital Converter 3Copyright Sill, 2008
IntroductionIntroduction
ADC = Analog-Digital-Converter Conversion ofaudio signals (mobile micro,
digital music records, ...)
Conversion ofvideo signals (cameras,frame grabber, ...)
Measured valueacquisition (temperature,
pressure, luminance, ...)
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Analog Digital Converter 4Copyright Sill, 2008
ADC - SchemeADC - Scheme
Sample
& Hold
Quantizationfsample
AnalogDigital
Analog input can be voltage or current (in the following
only voltage)
Analog input can be positive or negative (in the following
only positive)
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Analog Digital Converter 5Copyright Sill, 2008
2. Characteristic Values of ADCs2. Characteristic Values of ADCs
Which values characterize an ADC?
What kind oferrors exist?
What is aliasing?
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Analog Digital Converter 6Copyright Sill, 2008
ADC ValuesADC Values
Resolution N: number of discrete values to represent theanalog values (in Bit) 8 Bit = 28 = 256 quantization level, 10 Bit = 210 = 1024 quantization level
Reference voltageVref: Analog input signal Vin is related
to digital output signal Dout through Vref with:
Vin = Vref(D02-1 + D12
-2 + + DN-12-N)
Example: N= 3 Bit, Vref= 1V, Dout= 011
=> Vin = 1V ( 2-2 + 2-3) = 1V (0.25 + 0.125) = 0.375V
ADCVin Dout = D0D1DN-1
Vref
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Analog Digital Converter 7Copyright Sill, 2008
ADC Values contdADC Values contd
VLSB : Minimum measurable voltage difference inideal case (LSB least significant Bit)
VLSB = Vref /2N
Vin = VLSB(D02N-1 + D12
N-2 + + DN-120)
Example: N= 3 Bit, Vref = 1V, Dout= 011
=> VLSB= 1V / 23 = 0.125V
=> Vin = 0.125V ( 21+ 20) = 0.125V 3 = 0.375V
V: Voltage difference between two logic level Ideal: all V= VLSB
VFSR: Difference between highest and lowest
measurable voltages (FSR full scale range)
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Analog Digital Converter 8Copyright Sill, 2008
ADC Values contdADC Values contd
SNR: Signal to Noise Ratio Ratio of signal power to noise power
ENOB: Effective Number of Bits Effective resolution of ADC under observance of all noise and
distortions
SINAD (SIgnal to Noise And Distortion) ratio of fundamentalsignal to the sum of all distortion and noise (DC term removed)
Comparison of SINAD of ideal and real ADC with same wordlength
02.6
76.1= SINADENOB
, 10log signal signal
dbnoise noise
P PSNR SNR
P P
= =
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Analog Digital Converter 9Copyright Sill, 2008
Ideal ADCIdeal ADC
000
001
010
011
100
101
110
111
8
refV
DigitalO
utputDout
Analog InputVin
7
8refV
4
8refV
V, VLSB
VFSR
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Analog Digital Converter 10Copyright Sill, 2008
Further ADC ValuesFurther ADC Values
Bandwidth: Maximum measurable frequency of the inputsignal
Power dissipation Conversion Time: Time for conversion of an analog
value into a digital value (interesting in pipeline and
parallel structures) Sampling rate (fsamp): Rate at which new digital values
are sampled from the analog signal (also: sample Errors: Quantization, offset, gain, INL, DNL, missing
codes, non-monotonicity
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Analog Digital Converter 11Copyright Sill, 2008
Quantization ErrorQuantization Error
000
001
010
011
100
101
110
111
inV
2LSBV
2
LSBV
7
8refV
Dout
2 2
LSB LSBV V 1 VLSB or maximum INL > 0.5 VLSB
000
001
010
011
100
101
110
111
8
refV 4
8refV
7
8refV
Dout
in
V
Missing Code
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Analog Digital Converter 18Copyright Sill, 2008
Non-MonotonicityNon-Monotonicity
Lower conversion result for a higher input voltage Includes that same conversion may result from two
separate voltage ranges
000
001
010
011
100
101
110
111
8
refV 4
8 refV
7
8 refV
Dout
inV
Non-Monotonicity
Ideal
curve
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Analog Digital Converter 19Copyright Sill, 2008
AliasingAliasing
Too small sampling rate fsamp (under-sampling) can lead to
aliasing ( = frequency of reconstructed signal is to low)
Nyquist criterion: fsamp more than two times higherthan highest frequency
component fin of input signal: fsamp > 2fin
Input signal(with fin)
Reconstructedoutput signal
Measured data points
(sample rate: fsamp)
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Analog Digital Converter 20Copyright Sill, 2008
3. Nyquist-Rate ADCs3. Nyquist-Rate ADCs
How can Nyquist-rate ADCs be grouped? What is a dual slope ADC?
What is a successive approximation ADC?
What is an algorithmic ADC? What is a flashADC?
What is a pipelined ADC?
What are the pros and cons of the
Nyquist-rate ADCs?
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Analog Digital Converter 21Copyright Sill, 2008
Nyquist-Rate ADCsNyquist-Rate ADCs
Sampling frequency fsamp
is in the same range as
frequency fin of input signal
Low-to-medium speed and high accuracyADCs
Integrating
Medium speed and medium accuracyADCs Successive Approximation
Algorithmic
High speed and low-to-medium accuracy ADCs
Flash
Two-Level Flash
Pipelined
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Analog Digital Converter 22Copyright Sill, 2008
Integrating (Dual Slope) ADCsIntegrating (Dual Slope) ADCs
Phase 1: Integration (capacitor C1) ofVin in known time Tload
Qload = Vin / R1 Tload
Phase 2: Integration of reference voltage -Vrefuntil Vout= 0 and
estimation of time T
Qref = -Vref / R1 T= -Qload => Vin = Vref T / Tload
Independent of R1 und C1!
Vin
-VrefS1
S2
C1
Control
logicCounter
Comparator
D0
D1D2
D3
DN-1Integrator
VoutR1
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Analog Digital Converter 23Copyright Sill, 2008
Integrating (Dual Slope) ADCs contdIntegrating (Dual Slope) ADCs contd
Voltage
Time
Vin3
Vin2
Vin1
Phase 1 Phase 2
T1
T2T3
Tload
constantslope
slope depends
on Vin
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Analog Digital Converter 24Copyright Sill, 2008
Integrating ADCs: pros and consIntegrating ADCs: pros and cons
Simple structure (comparator andintegrator are the only analog
components)
Low Area / Low Power
Slow
Time intervals are not constant
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Analog Digital Converter 25Copyright Sill, 2008
Successive Approximation ADCSuccessive Approximation ADC
Generate internal analog signal VD/A
Compare VD/A with input signal Vin
Modify VD/A by D0D1D2DN-1 until closest possible value
to Vin is reached
S&HLogic
DAC
D0 D1 DN-1
Vin
Vref
VD/A
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Analog Digital Converter 26Copyright Sill, 2008
Successive Approximation ADC contdSuccessive Approximation ADC contd
S&HLogic
DAC
D0 D1 DN-1
Vin
Vref
VD/A
Comparsion ofVD/A with
2
Vref
2in
Vref
V>2
in
Vref
V4
in
Vref
V4
in
Vref
V 0
Di = 0
V= 2(V - Vref/4) V= 2(V + Vref/4)
i= i+1
i > N
Stop
yes
no
yes
Vin
S&H
X2
S1
Vref/4-Vref/4
S2
D0 D1 DN-1
Shift register
no
S&H
D.A.. Johns, K. Martin,Analog Integrated Circuit design, John Wiley & Sons, 1997
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Analog Digital Converter 31Copyright Sill, 2008
Algorithmic ADC: pros and consAlgorithmic ADC: pros and cons
Less analog circuitry than Succ. Approx.ADC
Low Power / Low Area
High effort for multiply-by-two gain amp
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Analog Digital Converter 32Copyright Sill, 2008
Flash ADCFlash ADC
Vin
Vref
Over range
D0
D1
DN-1
(2N-1) to N
encoder
R/2
R
R/2
R
R
R
R
R
R
Vin connected with 2N
comparators in parallel
Comparators connected
to resistor string
Thermometer code R/2-resistors on bottom
and top for 0.5 LSB
offset
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Analog Digital Converter 33Copyright Sill, 2008
Some Flash ADC design issuesSome Flash ADC design issues
Input capacitive loading on Vin Switching noise if comparators switch at the
same time
Resistors-string bowing by input currents of
bipolar comparators (if used)
Bubble errors in the thermometer code based on
comparators metastability
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Analog Digital Converter 34Copyright Sill, 2008
Flash ADC: pros and consFlash ADC: pros and cons
Very fast
High effort for the 2Ncomparators
High Area / High Power
Recommended for 6-8 Bit and less
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Analog Digital Converter 35Copyright Sill, 2008
Two-Level Flash ADCTwo-Level Flash ADC
Conversion in two steps:
1. Determination of MSB-Bits and reconverting of
digital signal by DAC
2. Subtraction from Vin and determination of LSB-Bits
F.e. 8-Bit-ADC: Flash: 28
=256 comparators, Two-level:224 = 32 comparators
N/2-BitFlash ADC x2
N
MSB (D0 DN/2-1) LSB (DN/2 DN-1)
N/2-BitFlash ADC
gain amp
Vin N/2-BitDAC
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Analog Digital Converter 36Copyright Sill, 2008
Two-Level Flash ADC: pros and consTwo-Level Flash ADC: pros and cons
Same throughput as Flash ADC
Less area, less power, less capacity loadingthan Flash ADC
Easy error-correction after first stage
Larger latency delay than Flash ADC
Design ofN/2-Bit-DAC
Currently most popular approach for high-speed/medium accuracy ADCs
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Analog Digital Converter 37Copyright Sill, 2008
Pipelined ADCsPipelined ADCs
Extension of two-level architecture to multiple stages (up-
to 1 Bit per stage) Each stage is connected with CLK-signal
Pipelined conversion of subsequent input signals
First result afterm CLK cycles (m - amount of
stages) Stages can be different
Stage 1 Stage 2 Stage mVin,0 Vin,1 Vin,m-1
CLK
D0 Dk-1 Dk D2k-1 Dmk DN-1
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Analog Digital Converter 38Copyright Sill, 2008
Pipelined ADCs: SchemePipelined ADCs: Scheme
k-Bit
ADCk-Bit
DAC
x2k
k Bits
Vin,i
Stage 1
S&H
Stage 2 Stage mVin,0
Vin,i+1
Vin,1 Vin,m-1
Time Alignment & Digital Error Correction
D0 D1 DN-1
CLK
CLK
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Analog Digital Converter 39Copyright Sill, 2008
Pipelined ADC: pros and consPipelined ADC: pros and cons
High throughput
Easy upgrade to higher resolutions
High demands on speed and accuracy on gain
amplifier
High CLK-frequency needed
High Power
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Analog Digital Converter 40Copyright Sill, 2008
4. Oversampling ADCs4. Oversampling ADCs
What are the problems of the quantizationnoise?
How does oversampling work?
What is noise shaping? What is a sigma-delta ADC?
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Analog Digital Converter 41Copyright Sill, 2008
Quantization ErrorQuantization Error(recap)(recap)
000
001
010
011
100
101110
111
inV
2LSBV
2
LSBV
7
8refV
Dout
2 2
LSB LSBV V >
+ +
N i Sh i td
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Analog Digital Converter 51Copyright Sill, 2008
Noise Shaping contdNoise Shaping contd
Oversampling and noise shaping:
Doubling offs increases SNR by 9 dB
Equivalently to a increase of resolution by 1.5 Bits
F.e. Vinis sinusoidal wave
SNR = (6.02 N+ 1.76 5.17 + 30log [OSR]) dB
up to fin = 100 kHz (and more)
1-Bit Quantizer (Comperator)1-Bit DAC
OS d NS i F D iOS d NS i F D i
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Analog Digital Converter 52Copyright Sill, 2008
OS and NS in Frequency DomainOS and NS in Frequency Domain
Power
fs/2 = OSRf0/2f0/2 f
Digital filter response
Oversampling
Power
fs/2f0/2 f
Oversampling and noise shaping
Power
f0/2 f
Signal
amplitude
Average
quantization noise
Si D lt ADC E lSi D lt ADC E l
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Analog Digital Converter 53Copyright Sill, 2008
DAC
Comparator
Vref= 2.5 V
Vin = 1.2 V
( ) ( )inv t t dt = ( ) ( )inv t t=
Sigma Delta ADC ExampleSigma Delta ADC Example
1.2
-1.3
3.7
-1.3
1.2
-0.1
3.6
2.3
1
0
1
1
2.5
-2.5
2.5
2.5
Si D lt ADC E l (C )Si D lt ADC E l (C )
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Analog Digital Converter 54Copyright Sill, 2008
Sigma Delta ADC Example (Curves)Sigma Delta ADC Example (Curves)
http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma_D.html
H(z)
In
tegrator
1Bit
-QuantizerCLK
DAC
Si D lt ADC dSi D lt ADC d
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Analog Digital Converter 55Copyright Sill, 2008
Sigma Delta ADC: pros and consSigma Delta ADC: pros and cons
High resolution
Less effort for analog circuitry
Low speed High CLK-frequency
Currently popular for audio applications
5 P ti l i5 P ti l i
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Analog Digital Converter 56Copyright Sill, 2008
5. Practical issues5. Practical issues
What are the performance limitations ofADCs?
What are the differences between PCB-
andIC-designs?
Are therehints to improve the ADC
design?
What are S&H circuits?
P f Li it tiP f Li it ti
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Analog Digital Converter 57Copyright Sill, 2008
Performance LimitationsPerformance Limitations
Analog circuit performance limited by:
High-frequency behaviorof applied components
NoiseCrosstalk (analog analog, analog digital)
Power supply coupling Thermal noise (white noise)
Parasitic components(capacitances, inductivities)
Wire delays
P iti C t E lP iti C t E l
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Analog Digital Converter 58Copyright Sill, 2008
Parasitic Component ExampleParasitic Component Example
Effect of 1pF capacitance on inverting input of an
opamp:
Mancini, Opamps for everyone, Texas Instr., 2002
N i D d E lN i D d E l
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Analog Digital Converter 59Copyright Sill, 2008
Noise Demands ExamplesNoise Demands Examples
Example 1: Vref
= 5V, 10 Bit resolution
VLSB = 5V / 210 = 5V / 1024 = 4.9 mV
Every noise must be lower than 4.9 mV
Example 2: Vref= 5V, 16 Bit resolution
VLSB = 5V / 216 = 5V / 65536 = 76 V
Every noise must be lower than 76 V
PCB IC D iPCB versus IC Design
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Analog Digital Converter 60Copyright Sill, 2008
PCB- versus IC-DesignPCB- versus IC-Design
PCB: Printed Circuit Board, IC: Integrated Circuit Noise in PCB-circuits much higher than in ICs Influences ofparasitics in PCB-circuits much
higher than in ICs
High-frequency behaviorof PCB-circuits muchworse than of ICs Wire delays in PCB much higher than in ICs
High accuracy, high speed, highbandwidth ADCs only possible in ICs!
S Hi t f Mi d Si l D iSome Hints for Mixed Signal Designs
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Analog Digital Converter 61Copyright Sill, 2008
For PCB and IC:
Keep ground lines separate! Dont overlap digital and analog signal wires!
Dont overlap digital and analog supply wires!
Locate analog circuitry as close as possible to the I/Oconnections! Choose right passive components for high-frequency
designs! (only PCB)
Some Hints for Mixed Signal DesignsSome Hints for Mixed Signal Designs
Mancini, Opamps for everyone, Texas Instr., 2002
Sample and Hold Circ itsSample and Hold Circuits
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Analog Digital Converter 62Copyright Sill, 2008
Sample and Hold CircuitsSample and Hold Circuits
S&H circuits hold signal constant for conversion
A sample and a hold device (mostly switch and capacitor) Demands:
Small RC-settling-time (voltage over hold capacitor has to befast stable at < 1 LSB)
Exact switching point (else aperture-error) Stable voltage over hold capacitor (else droop error) No charge injection by the switch
6 Low Power ADC Design6 Low Power ADC Design
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Analog Digital Converter 63Copyright Sill, 2008
6. Low Power ADC Design6. Low Power ADC Design
What are the main components of powerdissipation?
How can each component be reduced?
What are the differences between powerand energy?
Power DissipationPower Dissipation
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Analog Digital Converter 64Copyright Sill, 2008
Power DissipationPower Dissipation
Two main components:
Dynamic power dissipation (Pdyn) Based on circuits activity
Square dependency on supply voltageVDD2
Dependent on clock frequencyfclk
Dependent on capacitive load Cload Dependent on switching probability
Pdyn = VDD2 Cload fclk
Static power dissipation (Pstatic)
Constant power dissipation even if circuit is inactive Steady low-resistance connections between VDD und GND
(only in some circuit technologies like pseudo NMOS) Leakage (critical in technologies 0.18 m)
Low Power ADC DesignLow Power ADC Design
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Analog Digital Converter 65Copyright Sill, 2008
Low Power ADC DesignLow Power ADC Design
Reduction ofVDD:
Highest influence on power (P~ VDD2)
Sadly, delay increases (td ~ 1/VDD )
Sadly, loss of maximal amplitude SNR goes down
Possible solutions: Different supply voltages within the design
Dynamic change ofVDD depending on required
performance
Reduction offclk:
Dynamic change offclk
Low Power ADC Design contdLow Power ADC Design contd
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Analog Digital Converter 66Copyright Sill, 2008
Low Power ADC Design cont dLow Power ADC Design cont d
Reduction ofCload:
Cload depends on transistor count andtransistor size,
wire count and wire length
Possible Solutions:
Reduction of amount evaluating components Sizingof the design = all transistor get minimum
size to reach desired performance
Intelligent placing and routing
Low Power ADC Design contdLow Power ADC Design contd
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Analog Digital Converter 67Copyright Sill, 2008
Low Power ADC Design cont dLow Power ADC Design cont d
Reduction of:Activity = possibility that a signal changes within one
clock cycle
Possible Solutions:
Clock gating no clock signal to inactive blocks High active signals connected to the end of blocks
Asynchronous designs
Which ADC for Low Power?Which ADC for Low Power?
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Analog Digital Converter 68Copyright Sill, 2008
Which ADC for Low Power?Which ADC for Low Power?
Iflow speed: Dual Slope ADCArea is independent of resolution
Less components
Problem: Counter
Ifmedium / high speed: mixed solutions Popular: pipelined ADC with SAR
Pipelined solutions allows reduction of VDD
Long latency but high throughput
Power vs EnergyPower vs Energy
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Analog Digital Converter 69Copyright Sill, 2008
Power vs. EnergyPower vs. Energy
Powerconsumption in Watts Power = voltage current at a specific time point Peak power:
Determines power ground wiring designs andPackaging limits
Impacts of signal noise margin and reliabilityanalysis
Energy consumption in Joules Energy = power delay (joules = watts * seconds)
Rate at which power is consumed over time Lower energy number means less power to perform a
computation at the same frequency
Power vs Energy contdPower vs Energy contd
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Analog Digital Converter 70Copyright Sill, 2008
Power vs. Energy cont dPower vs. Energy cont d
Watts
time
Poweris height of curve
Watts
time
Energy is area under curve
Approach 1
Approach 2
Approach 2
Approach 1
Power vs Energy: Simple ExamplePower vs Energy: Simple Example
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Analog Digital Converter 71Copyright Sill, 2008
Power vs. Energy: Simple ExamplePower vs. Energy: Simple Example
VDD I (each gray block) Delay Power Energy
Flash 1 V 1 A 1 ns 4 W 4 fJ
2L-Flash 1 V 1 A 2.5 ns 2 W 5 fJ
VDDVin
I
Vin
VDD
I
Flash 2L-Flash
Shaded blocks are ignored
Dissipation for one input signal:
Low Power ADCs ConclusionLow Power ADCs Conclusion
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Low Power ADCs ConclusionLow Power ADCs Conclusion
There is no patent solution for low power ADCs!
Every solution depends on the specific task.
Before optimization analyze the problem:Which resolution?
Which speed?
What are the constraints (area, energy, VDD, Vin,)?
Which technology can be used?
Think also about unconventional solutions(dynamic logic, asynchronous designs, ).
Open QuestionsOpen Questions
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Analog Digital Converter 73Copyright Sill, 2008
Open QuestionsOpen Questions
Is there another way to design low power ADCs?
Is it recommended to reduce the analog part and
put more effort in the digital part?
How do I achieve a high SNR with low power
ADCs? Is it better to have only one block with high
frequency ormany blocks with low frequency?
How can asynchronous designs help me? How do I realize a low power ADC in sub-micron
technologies?
Basic ADC LiteratureBasic ADC Literature
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Basic ADC LiteratureBasic ADC Literature
[All02] P. E. Allen, D. R. Holberg, CMOS Analog Circuit Design,Oxford University Press, 2002
[Azi96] P.M. Aziz, H. V. Sorensen, J. Van der Spiegel, "AnOverview of Sigma-Delta Converters" IEEE SignalProcessing Magazine, 1996
[Eu07] E. D. Gioia, Sigma-Delta-A/D-Wandler, 2007
[Fi05] P. Fischer, VLSI-Design 0405 - ADC und DAC, UniMannheim, 2005
[Man02] Mancini, Opamps for everyone, Texas Instr., 2002
[Joh97] D. A. Johns, K. Martin, Analog Integrated Circuit design,John Wiley & Sons, 1997
[Tan00] S. Tanner, Low-power architectures for single-chip digitalimage sensors, dissertation, University of Neuchatel,Switzerland, 2000.
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More Questions?More Questions?
Signal ReconstructionSignal Reconstruction
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Analog Digital Converter 76Copyright Sill, 2008
Signal ReconstructionSignal Reconstruction
Continuous time (input signal):
Discrete (reconstructed by ADC):
/ 2 2
_
/ 2
( )T
RMS ct
T
v tV dt
T=
v(t)
time
2
0_
[ ]
n
i RMS discrete
x nV
n==
x[n]
n
RMS: root mean square
Voltage supply reductionVoltage supply reduction [Tan00][Tan00]
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Voltage supply reductionVoltage supply reduction [Tan00][Tan00]
For analog design, it is
shown that a voltagesupply reduction does notalways lead to a powerconsumption reduction forseveral reasons:
Threshold of MOStransistors.
Loss of maximal amplitudes(SNR degradation).
Limits of conduction in
analog switches. Low speed of MOS
transistors. Limited stack of transistors.
0
0.5
1
1.5
2
2.5
3
0 1 2 3 4 5 6Supply Voltage [V]
PowerDissipation[mW/M
S/s]
Power consumption of 10-bit S-C
1.5 bit/stage pipelined ADCs in
function of the voltage supply.
[Tan00] S. Tanner, Low-power architectures for
single-chip digital image sensors, dissertation,
University of Neuchatel, Switzerland, 2000.