SiNANO Workshop

Carrier mobility enhancement in strained silicon germanium

channelsDavid Leadley

University of Warwick

Collaborators

WarwickTim Grasby, Andy Dobbie, Chris Beer, Jon Parsons, Evan Parker, Terry Whall

IMECGareth Nicholas, Marc Meuris, M Heyns, P Zimmerman, Matty Caymax, ++

SINANO partnersKTH, Udine, Chalmers, AMO

Why is mobility still critical ?

*m

e

ITRS – long term years

By 2020, Lg=5nm, Vdd=0.7V

Mobility enhancement factor of 1.04 each node

Ballistic enhancement factor x2

Double gate structures – light doping

High mobility - light mass and minimal scattering

Why add Ge?

ADVANTAGES– Smaller bandgap– Lighter hole mass– Strain – splits bands and reduces scattering

BUT…– Native oxide no good– Band-to-band tunnelling

Pseudomorphic Si0.64Ge0.36 on Si

Mobility doubled

Vint (V)

-8.0-6.0-4.0-2.00.0

M-1

(n

o u

nits

)

10-5

10-4

10-3

10-2

10-1

100

101

Si Control

SiGe

Vgs = -1.5 V

Impact Ionisation

Reduced impact ionisation for SiGe, despite higher mobility

source

body

I

I

Nicholas et al, Electronics Letters 41, 20052074

High-k gated SiGe

Deposited HfO2

Si cap – oxidises to thin SiO2 interlayerMetal

HfO2

SiO2

SiGe

Si

< 1nmLowest EOT 12Å

Metal gate/HfO2 gate stack development for Si(cap)/Si0.8Ge0.2 channel

as-deposited425C, 30min, N2/H2

800C, 30sec, Ar950C, 30sec, Ar

Si Control SiGe 1nm Cap SiGe 2nm Cap SiGe 3nm Cap

Ave

rage

Dit

(cm

-2eV

-1)

1010

1011

1012

1013

as-deposited425C, 30min, N2/H2

950C, 30sec, Ar

Vg (V)

-4 -3 -2 -1 0 1 2 3 4

Jg (

A/c

m2)

1e-12

1e-11

1e-10

1e-9

1e-8

1e-7

1e-6

1e-5

1e-4

1e-3

1e-2

1e-1

1e+0

Thick TiNThin TiNW

950C, 30sec, Ar

Gate leakageInterface state density (W gate)

Warwick, AMO, Chalmers

High-k/metal gated Si0.8Ge0.2 surface p-channel devices

Gate Overdrive (V)

-3 -2 -1 0

Dra

in C

urr

en

t (

A/

m)

0.00

0.02

0.04

0.06

0.08

0.10SiliconSiGe 1nm capSiGe 3nm capSiGe 4nm cap

L = 50m, W = 50mVds = -50mV

Effective Field (MV/cm)

0.1 0.2 0.3 0.4 0.5

Eff

ectiv

e M

obili

ty (

cm2/V

s)0

20

40

60

80

100

120

140SiliconSiGe 1nm capSiGe 3nm capSiGe 4nm cap

L = 50m, W = 50m

KTH, Warwick, Chalmers, AMO

........enhancements beating Intel (IEDM 2004)

Effective Field (MV/cm)

0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1

Eff

ect

ive

Mo

bilit

y (c

m2/V

s)

0

20

40

60

80

100

120

140

160Si ControlSiGe 1nm CapSiGe 2nm CapSiGe 3nm CapSiGe 4nm CapSiGe 5nm Cap

Si Universal

Effective MobilityBest SiGe (25%) devices show mobility enhancement over silicon control

Mobility degradation compared to universal – interface roughness and Coulomb scattering important

KTH, Warwick, Chalmers, AMO

HOT SiGeHybrid Orientation Technology

– n on (100), p on (110) in Si, Yang et al. IEDM 2003

– in Si, no variation with orientation for long channels, but <110> best for short channels, Saito et al VLSI 2006

– 50% enhanced Idsat for SiGe (110) over Si (100),3.3x for mobility, Liu et al VLSI 2006

(100) substrate

[011]

[011]

(110) substrate

[001]

[110]

Novel p-channel/substrate orientations

0

0,1

0,2

0,3

0,4

0,5

0 30 60 90 120 150 180

Si (100) tox

=2.6 nm

Si0.8

Ge0.2

(110) tox

=4.5 nm

g m [

µS

/µm

]

Rotation [deg]

PMOSFETs, VDS

=-0.1 V, L=25 µm, W=4.6 µm

<112> <112><112><111> <110> <100><110> <100> <100><110> <110>

= 3.2 nm

… enhancement beating Liu et al (VLSI Symp 2006)

KTH, Warwick, Chalmers, AMO

Unstrained Ge pMOS

High performance Ge pMOS devices using a Si-compatible process flow

Zimmerman et al. IEDM 2006

IMEC

4nm HfO2

2μm Ge on Si substrate

12Å EOT, TDD 107-108 cm-2

PMOS fabricated with Lg ~125 nm

Unstrained Ge

Si

Ge

+ anneal

IMEC

Nit spread 0.2-8x1012cm-2

- affects Ids, gm and Vt

Uniformity restored after annealIMEC

Thinner EOT?

Mobility increase with thinner HfO2

- less charge trappingRagnarsson et al. IEEE TED 53, 1657 ( 2006)

Si

Starts to leak when too thin !

IMEC

Mobility in unstrained Ge

μ > 300 cm2/Vs

Correction required for Rsd in short channel devices Lg<0.25μm

IMEC

Investigating trapped charge

PhononSRCoulombPeak 1111

Warwick, IMEC

Dit varies across wafer 1011 - 2x1012cm-2

itt DV

itCoulomb

n charges, ofnumber 1

tPeak

V

1

Interface charge density

Warwick, IMEC

Extract Dit in 3 ways at 300K:i. from Vt – average all energiesii. subthreshold slope – specific energyiii. charge pumping

Mobility modelling at 4K

At low T, with confinement only have one HH subband.

ghnessSurfaceRouCoulombPeak 111

iCoulomb

n

1 4221F

SR

K

Warwick, IMEC

Fit using ni and as parameters ...

Modelled 4K mobility

Warwick, IMEC

Annealed As grown

ni agrees with values from Dit

Δ decreases after anneal from 0.6nm to 0.5nm,

hence μSR increases by 35%

μ300K must also depend on surface roughness

Strain tuning buffers

Strained-Si by local strain now in production

Si1-yGey virtual substrates for global strain

o y~0.2 for s-Si

o y~0.5 for s-Si1-xGex

o y~0.8 for s-Ge

Need low TDD and zero pile-up

Terrace Graded VS – better than industrial quality

XTEM TDD ≤ 105cm-2, PUD=0

10x10um2 AFM image indicating RMS roughness 1.5nm

Warwick, LETI, Jeulich

20% Ge

State-of-the-art sSi electron mobilityfrom TG-VSs

y = 15 -27%strain 0.6 – 1.1%

State of the art

Warwick, Udine, KTHF. Driussi et al., ULIS 2007

sGe global platform- 80% terrace grade

TDD=3x105/cm-2, PUD = 0, RMS ≈ 8nm

Warwick, FZ-Jeulich, LETI

Novel thin VS for sGe

20x20 um2 AFM image. 1.3nm RMS, fully relaxed 80% platformTDD ≈ 106/cm2 range

Seed layer

300nm Si0.2Ge0.8 Grade

Strained Ge

Si Sub

Strained Si

Warwick

Strained Ge pMOS

ASM, Warwick, IMEC

150nm TiN 4nm ALD HfO2

Positive Vt due to gate workfunction

Record Ge mobility via CMOS process

0

100

200

300

400

500

600

700

0 0.2 0.4 0.6 0.8 1

Effective Field (MV/cm)

Eff

ecti

ve H

ole

Mo

bil

ity

(cm

2/V

s)

Si/SiO2 universal

Unstrained Ge1 nm Si

2 nm Si

25 nm strained Ge

15 nm strained Ge

Warwick, IMECG. Nicholas et al., IEEE EDL 28, 825 (2007)

Peak μ = 650 cm2/Vs

Further comments on s-Ge

Full band Monte Carlo calculations, incl. BTBT, SCE etc. show best prospect for pMOS …

… strained-Ge directly on Si ! Krishnamohan et al (Stanford) VLSI (2006)

For s-SiGe OI, Idsat enhancement in short channels

exceeds μ increase in long channel.Tsutomu Tezuka et al. VLSI (2006)

nMOS still a problem for Ge …

… but tensile strain Si0.1Ge0.9 on relaxed Ge promising.

Summary

Addition of Ge improves mobility

High-k makes Ge viable

Mobility enhancements relevant for nanometre scale devices

Terrace grading – new generation of virtual substrates

TDD ≈ 4 x 104 cm-2

PUD = 0

30%

Warwick

≈105 cm-2 TDD Pile-up ≈1 cm-1

LG 30%

High stability sSi layers

Linear Grading

Terrace Grading

Strained Si thickness (nm)

Rel

axat

ion

(%)

Warwick, FZ-JeulichJ. Parsons et al., ULIS 2007

Extended Stacking Faults

Defect etch image of 20nm strained silicon layer

PVTEM image of 180nm strained silicon layer

Warwick, FZ-JeulichJ. Parsons et al., ULIS 2007

Extended Stacking Faults

S-Si

SiGe

“Perfect” dislocation

Trailing (30°) “partial” dislocation

Leading (90°) “Partial” dislocation

Stacking fault

Stacking faults – effective misfit dislocation blockers?

Defect etch images of 30nm strained silicon layer

J. Parsons et al., ULIS 2007 Warwick, FZ-Jeulich

50% terrace graded (for sSi)

TDD = 2x105 cm-2

PUD = 0

Warwick

≈ 20% TG - slower growth(+sSi)

TDD = 4 x 104/cm2

PUD = 0

Schottky Barrier MOSFET- world best?

-3.0 -2.5 -2.0 -1.5 -1.0 -0.51.0E-10

1.0E-9

1.0E-8

1.0E-7

1.0E-6

1.0E-5

1.0E-4

1.0E-3

1.0E-2

1.0E-1

1.0E+0

1.0E+1

1.0E+2

1.0E+3

Vds = -1.4 V

SBMOS4 #17

sbt off

mh.sbt=0.16

mh.sbt=0.20

Vg (V)Id

(m

A/m

m)

Thermionic

emmision

Tunnelling f(m*)

UCL, Warwick, Glasgow

Measurement Modelling

D.J. Pearman et al., IEEE Trans ED (accepted 2006)