15
SiPM BIAS and AMPLIFIER CIRCUIT G. FELICI LNF-INFN

SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

  • Upload
    others

  • View
    24

  • Download
    2

Embed Size (px)

Citation preview

Page 1: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM BIAS and AMPLIFIER CIRCUIT

G. FELICILNF-INFN

Page 2: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

EDIT2015–FRASCATIOCTOBER20-29 2D.BADONI-G.FELICI

SIPM POWER SUPPLY !

Page 3: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM BIAS (I)

EDIT2015–FRASCATIOCTOBER20-29 3D.BADONI-G.FELICI

The Problem u  8 SiPMsu  Each SiPM has a different working point TWO POSSIBLE APPROACHES

16 lutego 2011 Wojciech Kucewicz 8

FLCFLC--SiPMSiPMFLCFLC--SiPMSiPMThe The SiPMSiPM gain strongly depended of the bias voltage, so it has to be gain strongly depended of the bias voltage, so it has to be

adjusted for each diode.adjusted for each diode.An 8An 8--bit DACbit DAC was added in parallel to each input of preamplifier.

The DAC provide up to 5 V bias voltage moderation.

HV=VBREAKDOWN+VREF DAC

VSIPM = HV - VDAC

1st : use a DAC to move SiPM reference•  Very cheap using multi-channels DAC•  Easy to integrate in ASIC design•  Very low ripple required in main HV generator•  SiPMworkingpointsetupisabittricky(singleSiPMworkingpointsarenotindependent)

Page 4: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM BIAS (II)

EDIT2015–FRASCATIOCTOBER20-29 4D.BADONI-G.FELICI

2nd : use Main Voltage Generator and different regulators to adjust the single SiPM working point u  The regulators behave also like a filter to reduce the Main Voltage Generator rippleu  Independent SiPM working points adjustmentu  More components and PCB space required (size of the board increased)

3.2. Layout of the front-end electronics 37

October 2013. In this section, the circuit layout is introduced. The full layout isprinted in the appendix, see fig. A.3. In figure 3.10, a schematic version is shown inorder to explain why this layout is better than the default circuits proposed by theSiPM manufacturers. Details are mentioned in the following subsections.

The default layout proposed by several manufacturers [23] [22] [26] is quite easy tounderstand, see figure 3.9: A low-pass at the cathode of the SiPM is used to limitthe current and to filter high frequencies from the constant bias voltage. The SiPMsignal output has already been introduced in the last chapter and is based on a shuntresistor and an (inverting) op-amp.

3.2.1 Beissel voltage controlling circuit

The Beissel voltage controlling (BVC) circuit has originally been introduced by FranzBeissel († 2012) at III. Physikalisches Institut, RWTH Aachen University. Figure3.11 shows a very simplified version of the BVC circuit. The simplified version canbe used to explain the DC performance of the voltage controller.

The di↵erential voltage at the op-amp is zero, which means that the op-amp is tryingto pull the voltage in the inverting node to V

r

. A current flows through the resistorR

7

which is equal to

I

7

= V

r

/R

7

.

The op-amp draws no current in the input, that is I� = 0. The same current I

7

flows through the resistor R6

. Therefore,

+

V

r

I�

R

7

I

7

R

6

I

6

L

b

I

b

V

b

C

b

R

E

V

i

C

E

I

6

+ I

b

Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuitmodified in this thesis, see fig. A.3 for detailed circuit elements. The voltage atnode V

b

is set by the op-amp according to eq. (3.2). This simplified circuit is validfor DC performance only and especially when no current is drawn at the V

b

node,i.e. I

b

= 0.

Simplified version of Beissel voltage controlling circuit

HOW DOES IT WORK ?u  Assuming an ideal operational amplifier the voltage at the inverting node we’ll be Vr, then I7=Vr/R7

u  The same current will flow through R6 (ZIN=∞)à Vr/R7= (Vb –Vr)/R6

u  Then if Vi > Vb (the transistor must be polarized) à Vb=(1+R6/R7)*Vr

u  Adjusting the R6/R7 ratio or Vr value we can adjust the SiPM working voltage

IDEAL AMP OPu  gain=∞u  ZIN=∞u  ZOUT=∞u  BW=∞

Page 5: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

EDIT2015–FRASCATIOCTOBER20-29 5D.BADONI-G.FELICI

PREAMPLIFIERS !

Page 6: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

VOLTAGE PREAMPLIFIER

EDIT2015–FRASCATIOCTOBER20-29 6D.BADONI-G.FELICI

PREAMPLIFIER=INPUT AMPLIFIERu  Generally located on the detector (ON-DETECTOR ELECTRONICS)u  Amplify the signal optimizing the signal-to-noise ratiou  Three basic configurations:

u  Voltage preamplifier u  Current preamplifieru  Charge preamplifier

VOLTAGE PREAMPLIFIER (for sensors generating voltage signals or as second stage for sensors generating current signals)

en

AV

detC( )↓ti _det preinconntottot

inout CCCC

CQV ++==

Ctot can change as a function of detector working parameters or PT à Vout changes

Page 7: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

CURRENT PREAMPLIFIER

EDIT2015–FRASCATIOCTOBER20-29 7D.BADONI-G.FELICI

infout iRV −≈

Rf

⎟⎟⎟⎟

⎜⎜⎜⎜

+⋅−=

−=−

−=

A

iRV

iRVVAVV

infout

infinout

inout

11

1

AV

detCVout

Vin

+-

( )↓ti

INPUT IMPEDANCE

→+

=→−=⎟⎟⎟⎟

⎜⎜⎜⎜

+⋅−

⎟⎟⎟⎟

⎜⎜⎜⎜

+⋅−=

−=

AiR

VAV

A

iR

A

iRV

AVV

infinininf

infout

inout

111

1

11

1

AR

Z fin +=1

Cin CONTRIBUTION

RCjRZin ω+

=1

u  InputsignalisconvolvedwithanexponenXal.

u  IncreasingRfincreasesboththepreamplifiersensiXvityandτ.

C R( )↓ti

Page 8: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

CHARGE PREAMPLIFIER

EDIT2015–FRASCATIOCTOBER20-29 8D.BADONI-G.FELICI

( )

( )

⎟⎟⎟⎟

⎜⎜⎜⎜

+⋅−=

−=−

−=

ACj

iV

CjiVV

AVV

f

inout

f

ininout

inout

11

1ωω

ωω

fC

Vout+

-

( )↓ti

( )f

inout Cj

iVωω

−≈

t

Vout

t

-Q/Cf( ) ( )tQti inin δ⋅=

INPUT IMPEDANCE

Vout = −AVin Vout = −iin ω( )jωCf

⋅1

1+ 1A

⎜⎜⎜

⎟⎟⎟

−iin ω( )jωCf

⋅1

1+ 1A

⎜⎜⎜

⎟⎟⎟= −AVin →Vin =

iin ω( )jωCf ⋅ 1+ A( )

( ) fin CAC ⋅+= 1

HOW MUCH SIGNAL ARE WE GOING TO LOOSE ?

( ) ( )

( ) f

tamp

tff

amp

CACQQ

CCAQ

CAQ

⋅++

=

+⋅+=

⋅+

11

11

Es. A=103; Cf=1pF

Ct=10 pF àQampl/Q=0.99

Ct=100 pF àQampl/Q=0.90

tC ( ) fCA ⋅+1( )↓ti

Page 9: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

EDIT2015–FRASCATIOCTOBER20-29 9D.BADONI-G.FELICI

WHICH AMPLIFIER ?!

Page 10: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

VOLTAGE, CURRENT OR CHARGE AMPLIFIER ?

EDIT2015–FRASCATIOCTOBER20-29 10D.BADONI-G.FELICI

u  SiPMs output charge of the order of hundreds of fCu  SiPM devices have excellent timing properties. u  SiPM devices exhibit single photon resolution, but have a quite poor lineari response

Voltage or Current amplifiers configurations can be used as head-stage amplifiers

+V

+

_

R1

R2

RS

(a) Pre-amplifier

+V

+

_

RF

CF

RG

(b) Transimpedance

Figure 2: Two amplifier setups, not shown are the capacitively decoupledpower lines which all high speed circuits should have.

called a voltage amplifier. The impedance of the photodiode is largely ir-relevant as it is normally much larger than RS. Increasing RS increasesthe voltage generated by the photodiode, however this also increases thevoltage noise generated by the input current noise of the op-amp and alsodecreases the bandwidth of the photodiode. The gain in non-inverting setupis set by one plus the ratio of the feedback resistor to the resistor to groundG = 1 + R2/R1. The bandwidth (cuto↵ frequency, f�3dB) of the circuit isnormally set by the gain bandwidth product of the op-amp as the photodiodenormally has a much larger bandwidth.

2 Transimpedance amplifier

In the transimpedance amplifier setup the amplifier itself is acting as thecurrent-to-voltage convertor (this is often called a current amplifier), withthe output voltage gain set by the feedback resistor. A feedback capacitor isalso often needed control the frequency response of the circuit as at higherfrequencies the signal increases with a gain of

3

In voltage amplifiers increasing RS increases input amplifier voltage, but amplifier input voltage noise increase and bandwidth decreases.Current (or transimpedance) amplifier allows to overcome voltage amplifier limitations in terms of gain and bandwidth still maintaining a good signal-to-noise ratio (but stability problems could arise because diode parasitic capacitance).

Page 11: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

EDIT2015–FRASCATIOCTOBER20-29 11D.BADONI-G.FELICI

AMPLIFIER STABILITY !

Page 12: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM AMPLIFIER (I)

EDIT2015–FRASCATIOCTOBER20-29 12D.BADONI-G.FELICI

SiPM PS

16

© 2004 National Semiconductor Corporation

The Photodiode Amplifier:

• Oh yeah, addsome feedback:

-10 Volts

Light +

-

+-

This pin stays at ground so output goes more positive with more light.

This current makes positive voltage here

-

+

16

© 2004 N

ational Sem

iconductor Corporation

Th

e P

ho

tod

iod

e A

mp

lifier:

•Oh yeah, add

some feedback:

-10 Volts

Light+ -

+-

This pin stays at ground so output goes m

ore positive w

ith more light.

This current makes

positive voltage here

- +

The SiPM current makes positive voltage at the output of operational amplifier

This pin at GND force this pin to GND (virtual GND)REMIND à GAIN=∞

BUT most likely if you use high bandwidth amplifier looking at the output with a scope

17

© 2004 National Semiconductor Corporation

The Photodiode Amplifier:

• So it oscillatesand/or clips,what is wrong?

-10 Volts

Light +

-

THE AMPLIFIER OSCILLATES !! WHY ???

Page 13: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM AMPLIFIER (II)

EDIT2015–FRASCATIOCTOBER20-29 13D.BADONI-G.FELICI

-

+

THE PROBLEM: oscillation are caused by SiPM parasitic capacitance on input

17

© 2004 National Semiconductor Corporation

The Photodiode Amplifier:

• So it oscillatesand/or clips,what is wrong?

-10 Volts

Light +

-

-

+

16

© 2004 National Semiconductor Corporation

The Photodiode Amplifier:

• Oh yeah, addsome feedback:

-10 Volts

Light +

-

+-

This pin stays at ground so output goes more positive with more light.

This current makes positive voltage hereSiPM current source

forces output to change

SiPM parasitic capacitance lag the feedback signal

FEEDBACK LAG IS BAD

Page 14: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

SiPM AMPLIFIER (III)

EDIT2015–FRASCATIOCTOBER20-29 14D.BADONI-G.FELICI

-

+

THE SOLUTION: insert a capacitance to compensate for the phase lag

NEXT PROBLEM: noise (current noise & voltage noise)

CURRENT noise important on this pin

VOLTAGE noise important on this pin

AMPLIFIER NOISEu  Hard to match low current noise and low voltage noise requirement on the same deviceu  JFET amplifiers have low current noiseu  Bipolar amplifiers have low voltage noise

u  More on this in Noise Introduction slides ….

Page 15: SiPM BIAS and AMPLIFIER CIRCUIT - Agenda (Indico) · Figure 3.11: Highly simplified circuit of the Beissel voltage controlling circuit modified in this thesis, see fig. A.3 for

BIBLIOGRAPHY

EDIT2015–FRASCATIOCTOBER20-29 15D.BADONI-G.FELICI

[1]Front-endElectronicsforSiliconPhotomulXpliers,JohannesSchumacher[2]Photodiodeamplifier–G.Lochead