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Slide 1EE40 Fall 2009 Prof. Cheung
EE40
Final Exam Review
Prof. Nathan Cheung
12/01/2009
Practice with past examshttp://hkn.eecs.berkeley.edu/exam/list/?exam_course=EE%2040
Slide 2EE40 Fall 2009 Prof. Cheung2
Overview of Course
Circuit components: R, C, L , sources I-V characteristics energy storage/dissipation
Circuit analysis: Laws: Ohm’s, KVL, KCL Equivalent circuits (series/ parallel, Thevenin, Norton) Superposition for linear circuits Nodal analysis Mesh analysis Phasor I and V
First-order transient excitation/analysis:Second Order RLC circuitsBode Plots
Slide 3EE40 Fall 2009 Prof. Cheung3
Semiconductors Devices pn-diodes (many types) FETs (n-channel, p-channel, CMOS)
Useful Diode and FET circuits: Amplifiers: op-amp (negative feedback), rectifiers; wave shaping circuits
Logic gates; Combinatorial logic (sum-of-products, Karnaugh maps), sequential logic etc.
Overview of Course
Slide 4EE40 Fall 2009 Prof. Cheung
Diode Circuit Analysis by Assumed Diode States
•1) Specify Ideal Diode Model or Piecewise-Linear Diode Model
•2) Each diode can be ON or OFF•3) Circuit containing n diodes will have 2n states•4) The combination of states that works for ALL diodes (consistent with KVL and KCL) will be the solution
reverse bias
forward bias
ID (A)
VD (V)reverse bias
forward bias
ID (A)
VDon
Slide 5EE40 Fall 2009 Prof. Cheung
Example Problem: Perfect Rectifier Model
Sketch Vout versus Vin
Suggested problem: What if there is a 0.6V drop when diodes are on ?
Slide 6EE40 Fall 2009 Prof. Cheung
Diode with Capacitor Circuit (e.g.Level Shifter)
- VC +
VOUT
+
-
VIN
+
-
C
VIN
t
1) Diode =open, VC(t)=0, VOUT (t)= VIN(t)2) Diode =short, VC(t)= -VIN(t) , VOUT(t)=03) Diode =open, VC(t)= -VIN(min), VOUT(t)= VIN(t)-VIN(min)
VOUT (t)= VC(t)+ VIN(t)
,
VC
VOUT
t
1 3
2Finds out what happens to VC when VIN changes
VIN(min)
Slide 7EE40 Fall 2009 Prof. Cheung
Example: Diode with RL Circuit
Answer
Sketch i(t)
= L/R = 0.05 msec
Note: i(t) is continuous
Slide 8EE40 Fall 2009 Prof. Cheung
Load-Line Analysis
We have a circuit containing a two-terminal non-linear element “NLE”, and some linear components.
1V+-
250K
S
Non-linear element
9A1M
D
+- 2V
200K
S
NLE
D
Then define I and V at the NLE terminals (typically associated signs)
First replace the entire linear part of the circuit by its Thevenin equivalent.
ID
VDS+ -
Slide 9EE40 Fall 2009 Prof. Cheung
Example of Load-Line Analysis (con’t)
And have this connected to a linear (Thévenin) circuit
+- 2V
200K The solution !
Given the graphical properties of two terminal non-linear circuit (i.e. the graph of a two terminal device)
VDS
ID A)
10
(V)1 2
IDDNLE S
Whose I-V can also be graphed on the same axes (“load line”)
Application of KCL, KVL gives circuit solution
+- 2V
200K
S
NLE
D ID
VDS+ -
Slide 10EE40 Fall 2009 Prof. Cheung
Example : Voltage controlled Attenuator
VC and RC Determines rd atQ point of diode
Slide 11EE40 Fall 2009 Prof. Cheung
The large capacitors and DC bias source are effective shortsfor the ac signal in small-signal circuits
Example : Voltage Controlled Attenuator
Slide 12EE40 Fall 2009 Prof. Cheung12
VDS
ID A)
10
(V)1 2
Three-Terminal Parametric Graphs
Concept of 3-Terminal Parametric Graphs:
We set a voltage (or current) at one set of terminals (here we will apply a fixed VGS, IG=0)
and conceptually draw a box around the device with only two terminals emerging so we can again plot the two-terminal characteristic (here ID versus VDS).
3-Terminal Device
ID
DG
S
VGS
+-
VGS = 3
VGS = 2
VGS = 1
But we can do this for a variety of values of VGS with the result that we get a family of curves.
Slide 13EE40 Fall 2009 Prof. Cheung13
Graphical Solutions for 3-Terminal Devices
Now draw ID vs VDS for the 2V - 200K Thevenin source.
First select VGS (e.g. 2V) and draw ID vs VDS for the 3-Terminal device.
VDS
ID A)
10
(V)1 2
VGS = 3
VGS = 2
VGS = 1
ID
G+-
+-
V2V
D200K
S
VDS
ID A)
10
(V)1 2
The only point on the I vs V plane which obeys KCL and KVL is ID = 5A at VDS = 1V.
The solution !
We can only find a solution for one input (VGS) at a time:
Slide 14EE40 Fall 2009 Prof. Cheung
1) Guess the mode of operation for the transistor. (We will learn how to make educated guesses).
2) Write the ID vs. VDS equation for this guess mode of operation.
3) Use KVL, KCL, etc. to come up with an equation relating ID and VDS based on the surrounding linear circuit.
4) Solve these equations for ID and VDS.
5) Check to see if the values for ID and VDS are possible for the mode you guessed for the transistor. If the values are possible for the mode guessed, stop, problem solved. If the values are impossible, go back to Step 1.
SOLVING MOSFET CIRCUITS: STEPS
Slide 15EE40 Fall 2009 Prof. Cheung
CHECKING THE ANSWERS
NMOS 1) VGS > VT(N) in triode or saturation VGS ≤ VT(N) in cutoff
•2) VDS < VGS – VT(N) in triode VDS ≥ VGS – VT(N) in saturation
DS tov V0GSv
TriodeSaturationCut-off
toV
PMOS1) VGS < VT(P) in triode or saturation VGS ≥ VT(P) in cutoff2) VDS > VGS – VT(P) in triode VDS ≤ VGS – VT(P) in saturation
DS tov V 0GSv
Triode Saturation Cut-off
toV
Slide 16EE40 Fall 2009 Prof. Cheung
Example Problem : MOSFET Circuit
Slide 17EE40 Fall 2009 Prof. Cheung
Find VGS such that VDS=2V
Example Problem : MOSFET Circuit
Answer
Check: VDS(=2V) > VGS-VT (=1.5-0.5=1V)MOSFET indeed is in saturation mode
Guess Saturation Mode
Slide 18EE40 Fall 2009 Prof. Cheung
Find small-signal model parameters
Example Problem : MOSFET Circuit
=10-5 Siemens
Slide 19EE40 Fall 2009 Prof. Cheung
How do you guess the right mode ?
Often, the key is the value of VGS.
(We can often find VGS directly without solving the whole circuit.)
VGS ≤ VT(N)
definitely cutoff
VDS
ID
VGS = VT(N) +
probably saturation
VDS
ID
VGS - VT(N) =
Slide 20EE40 Fall 2009 Prof. Cheung
triode mode saturation mode
VDS
VGS - VTH(N)
When VGS >> VTH(N), it’s harder to guess the mode.
ID
If ID is small, probably triode mode
How do you guess the right mode ?
Slide 21EE40 Fall 2009 Prof. Cheung
EXAMPLE
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_4 V
3 V
1.5 k
GIVEN: VTH(N) = 1 V, K= 250 A/V2, = 0 V-1.
1) Since VGS > VTH(N), not in cutoff mode. Guess saturation mode.
2) Write transistor ID vs. VDS:
mA1
V 1V 310250II 26tDsaD
3) Write ID vs. VDS equation using KVL:
0V4 DDS I k 1.5-V-
Slide 22EE40 Fall 2009 Prof. Cheung
EXAMPLE
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_4 V
3 V
1.5 k
GIVEN: VTH(N) = 1 V, ½ W/L nCOX = 250 A/V2, = 0 V-1.
4) Solve VDS:
ID = 1mA VDS = 2.5 V
5) Check:
ID and VDS are correct sign, and VDS ≥ VGS-VT(N) as required in saturation mode.
Slide 23EE40 Fall 2009 Prof. Cheung
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_4 V
3 V
1.5 k
GIVEN: VTH(N) = 1 V, K= 250 A/V2, = 0 V-1.
WHAT IF WE GUESSED THE MODE WRONG?
1) Since VGS > VTH(N), not in cutoff mode. Guess triode mode.
2) Write transistor ID vs. VDS:
3) Write ID vs. VDS equation using KVL:
0V4 DDS I k 1.5-V-
ID = 2·250·10-6(3 – 1 – VDS/2)VDS
Slide 24EE40 Fall 2009 Prof. Cheung
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_4 V
3 V
1.5 k
GIVEN: VTH(N) = 1 V, K= 250 A/V2, = 0 V-1.
4) Solve for VDS with quadratic equation by combining 2) and 3):
VDS = {4 V, 2.67 V}
5) Check:VDS > VGS – VT(N) = 2VNeither value valid in triode mode!Guess is incorrect.
WHAT IF WE GUESSED THE MODE WRONG?
Slide 25EE40 Fall 2009 Prof. Cheung
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_4 V
3 V
1.5 k
In this circuit, the transistor delivered a constant current IDSAT to the 1.5 k resistor.
This circuit acts like a constant current source, as long as the transistor remains in saturation mode.IDSAT does not depend on the attached resistance if saturation is maintained.
IDSAT1.5 k
Another Perspective
Slide 26EE40 Fall 2009 Prof. Cheung
G
D
S
ID
+
V GS
_
+
VDS
_+_
+_VDD
VGS
RL
IDSAT does depend on VGS; one can adjust the current supplied by adjusting VGS.
The circuit will go out of saturation mode if• VGS < VT(N) or• VDS < VGS – VT(N)
This can happen if VGS is too large or too small, or if the load resistance is too large.
IDSAT RL
Another Perspective
Slide 27EE40 Fall 2009 Prof. Cheung
ANOTHER EXAMPLE
G
D
S
ID
+
V GS
_
+
VDS
_
+_4 V
1.5 k
GIVEN: VTH(N) = 1 V, K= 250 A/V2, = 0 V-1.
1) What is VGS?No current goes into/out gate.VGS = 3 V by voltage division.Guess saturation (randomly).
2) Write transistor ID vs. VDS:
3) Write ID vs. VDS equation using KVL:
0V4 DDS I k 1.5-V-
2 k
6 k
Effectively the same circuit as previous example: only 1 voltage source in this case
mA1
V 1V 310250II 26tDsaD
VDS=2.75V consisitent with saturation mode
Slide 28EE40 Fall 2009 Prof. Cheung
The CMOS Inverter: Current Flow
VIN
VOUT
VDD
VDD00
N: offP: Triode
N: TriodeP: off
N: TriodeP: sat
N: satP: Triode
N: satP: sat
A B D E
C
ii
I
S
D
G
GS
D
VDD
VOUTVIN
Slide 29EE40 Fall 2009 Prof. Cheung
Another CMOS Example: The LATCH
VDD
VOUT
VDD
VOUT_INT
CLK
CLK
CLK
CLK
VIN
Data (VIN) is written to the internal node (VOUT_INT) when the clock is low. VOUT remains frozen.
When the clock is high. The (inverted) internal node voltage is written to VOUT. The internal node VOUT_INT remains frozen
Slide 30EE40 Fall 2009 Prof. Cheung
THE LATCH
VDD
VOUT
VDD
VOUT_INT
CLK
CLK
CLK
CLK
VIN
When CLK is low the left-hand transistors conduct. The right-hand transistors are open.
VOUT_INT is charged to VIN.
0 V
VDD 0 V
VDD
VOUT remains the same; there is no charging path.
Slide 31EE40 Fall 2009 Prof. Cheung
THE LATCH
VDD
VOUT
VDD
VOUT_INT
CLK
CLK
CLK
CLK
VIN
When CLK is high, the right-hand transistors conduct. the left-hand transistors are open.
VDD
VDD0 V
0 V
VOUT_INT remains the same; there is no charging path.
VOUT is changed to VOUT_INT.
Slide 32EE40 Fall 2009 Prof. Cheung
CONCEPT OF STATE
VDD
CurrentState
VDD
NextState
CLK
CLK
CLK
CLK
VIN
A latch stores a “1” or “0”.
The stored value is known as the “state”.
This is one of the basic elements needed to make a “state machine” (covered in EE 20 and CS 61C).
Slide 33EE40 Fall 2009 Prof. Cheung
LATCH AS GATEKEEPER
Combinatorial LogicSignal propagates all the way through
Includes our logic gates: NAND, NOT, etc.
Sequential ElementPrevents changes in output until signaled
A signal may have to go through a complex system of gates, with paths of different delays: possibility of false output!
Slide 34EE40 Fall 2009 Prof. Cheung
Amplifier Efficiency
Power Supply A
Power Supply B
LoadSource
SourcePi = (10-3V)2/105 =10-11 WLoadP0 = (8V)2/8 =8 W
Power SuppliesPs = 15W+7.5W = 22.5 W
AmplifierPd = 22.5W+10-11W-8W = 14.5 W
Amplifier
Amplifier Efficiency = 8/22.5 =36%
Slide 35EE40 Fall 2009 Prof. Cheung
Differential Signal and Common Mode Signal
Redefine the inputs in terms of two other voltages:
1. differential mode input vid vi1 – vi2
2. common mode input vicm (vi1 + vi2)/2
so that
vi1 = vicm + (vid/2) and vi2 = vicm - (vid/2)
icmcmiddo vAvAv
“common mode gain”
“differential mode gain”
Slide 36EE40 Fall 2009 Prof. Cheung
Common Mode Rejection Ratio
cm
d
A
Alog20)dBin(CMRR
Example
•Differential signal from sensor = 1mV (peak).We want outputs signal > 1V implies Ad> 1000•Common mode signal =100V (from power line).We want common mode signal < 0.1V impliesAcm <10-4
Therefore CMRR needs to be > 20log(107)= 140dB
Slide 37EE40 Fall 2009 Prof. Cheung
GivenVoff=2mVIB= 100nAIoff= 20nAAcm=1Ad=100Both input terminals to ground through 100k resistors
Use superposition
Vo = Ad(Vvoff+VIoff)+ Acmvicm= 100(0.001667+0.001667)+1(0.01)=0.3343V
Offset Voltage, Offset Current, and Bias Current