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UCSB HEP ASIC Class Slide 1 CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

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Page 1: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 1

CMOS Circuit Design, Layout and Simulation

Sam Burke

UCSB HEP Group

Page 2: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 2

References

• Text CMOS Circuit Design, Layout, and Simulation by R. J.

Baker, Li and Boyce IEEE Press Oct 2002 ISBN-81-203-1682-7

• URL http://cmosedu.com/cmos1/book.htm

Page 3: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 3

The Well

• P Type Wafer boron acceptor atoms (25

ohm*cm)

• Transistors Nmos Transistors on p-

substrate Pmos Transistors on n-well

• Diode formed between the n-well

and p-substrate

Page 4: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 4

Historical Methods

• Point Contacts 1948

• Grown Junctions 1950

• Alloy Junctions 1952

• Planar Technology or Junction Technology 1953

Page 5: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 5

A Little History

Page 6: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 6

Patterning

• Start with clean bare wafer

• Grow Oxide wet oxide dry oxide

• Apply Resist

• Photo-resist pattern

• Expose

• Develope

• Etch to remove oxide

• Ready for Diffusion

Page 7: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 7

Growing an N-Well

• Donor Atom Diffusion Donor valance=5

– Phosphorus Si valance=4

• N Well Resistivity 0.75 ohm*cm

Page 8: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 8

The N-Well

Page 9: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 9

The Well Resistor• R=[p/t]*L/W

R=Resistance p=resistivity

• R=Rsq*L/W Rsq=sheet resistance

(ohm/square)

• For N-Well p=0.75ohm*cm t=3um L=100um W=10um R=2500*100/10=25kohms

Page 10: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 10

Si Resistivity

• Experimental Data N-Type

donor concentration shown for resistor example

• Ref: Grove, A.S “Physics and Tech - -

Page 11: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 11

N-Well Cross Section

Page 12: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 12

L-Edit

• Demo the creation of an N-Well using L-Edit Error checking

Page 13: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 13

Design Process

Page 14: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 14

Well and Contacts

• N-Well contact on left metal1 active

• Bulk contact on right metal1 active P Implant

Page 15: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 15

PN Junction Depletion

• Carrier drift

Page 16: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 16

PN Junction Voltage

Page 17: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 17

Diode Junction Capacitance

Page 18: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 18

Diode V/I Equation

Page 19: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 19

Forward Biased Diode

Page 20: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 20

S-Edit

Page 21: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 21

T-Spice

Page 22: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 22

Net List of Diode Circuit

Page 23: Slide 1UCSB HEP ASIC Class CMOS Circuit Design, Layout and Simulation Sam Burke UCSB HEP Group

UCSB HEP ASIC Class Slide 23

Diode Storage Time