NANO IDEA Open Access

A High-Performance Rectangular Gate UChannel FETs with Only 2-nm Distancebetween Source and Drain ContactsXi Liu1* , Zhengliang Xia1, Xiaoshi Jin1 and Jong-Ho Lee2

Abstract

A novel high-performance rectangular gate U channel FET (RGUC FET) for extreme integrated distance betweensource and drain contacts is proposed in this paper. The RGUC FET represents nearly ideal subthreshold characteristicstill the distance between source/drain (S/D) contacts reduced to 2 nm. Different from the other recessed or U-shapedchannel-based FETs, the gate contacts do not need to be formed in the recessed region but only in a layer of spacerfor the insulation between the two vertical parts on both sides of the U channel. Its structural advantages make itpossible to be applied to manufacture integrated circuits with higher integration for extreme integrated distancebetween source and drain contacts. The electrical properties of the RGUC FET were scrupulously investigatedby studying the influence of design parameters including the horizontal distance between S/D contacts, theextension height of S/D region, and the thickness and material of the gate oxide layer. The electrical propertiesof the RGUC FET are verified by quantum simulation. Compared to the other non-planner channel multi-gateFETs, the novel RGUC FET is suitable for higher integration.

Keywords: Rectangular gate U channel, Extreme integration, Quantum simulation

IntroductionAs one of the most promising device used in nano-scaleintegrated circuits (IC), the junctionless field-effect tran-sistor (JL FET) which presents remarkable electricalcharacteristics compared to conventional junction-basedmetal oxide semiconductor (MOS) FETs, in addition toits simplicity of fabrication, has been deeply studied inrecent years [1–4]. While increasing the gate voltageforms the accumulation region in the channel, resultingto greater on current [5], the introduction of themultiple-gate (MG) FET strengthened the controllabilityof the source-to-drain current from the gate voltage,resulting to much better subthreshold properties of thedevice. The junctionless multiple-gate (JL MG) FETsalso have been widely studied for years [6–8]. Althoughthe vertical channel gate-all-around MOSFET shows anearly ideal I-V performance with a radius only severalnanometers, the vertical channel of it makes the source

and drain contact could not be manufactured in thesame layer, which makes the layout of ICs incompatiblewith the planner technology. Moreover, as the semicon-ductor fabrication has been forced to scale down thechannel length to be less than 10 nm, the MG FETs facethe short-channel effect again [9–11]. In order to over-come the short-channel effect, recessed channel MOS-FETs become a hot topic in recent years [12–16]. Themodeling and simulation work of recessed channelMOSFETs is also comprehensively carried out [17–20].A recessed channel MOSFET has both planner verticalchannel parts under both source and drain contacts anda horizontal planar channel part. It actually prolongedthe effective channel length compared to conventionalMOSFETs with only the horizontal planar channel. Forthe device with the same distance between source anddrain contacts, it can be more immune to theshort-channel effect compared to conventional MOSFETswith planar channel; however, the experimental datashows that the subthreshold swing of MOSFETs withrecess channel can not realize an ideal subthreshold swingwith sub 100-nm effective channel length. That is because

* Correspondence: liu.sut@live.com1School of Information Science and Engineering, Shenyang University ofTechnology, Shenyang 110870, ChinaFull list of author information is available at the end of the article

© The Author(s). 2019 Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, andreproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link tothe Creative Commons license, and indicate if changes were made.

Liu et al. Nanoscale Research Letters (2019) 14:43 https://doi.org/10.1186/s11671-019-2879-0

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although the channel length is prolonged, the gate con-trollability is not strengthened as MG FETs. It should benoted that, it is better to define a new key geometricalparameter related to the description of integration, insteadof the channel length. The distance between source anddrain contacts is more realistic and effective because thefinal goal of the design of the nano-scale device is therealization of the best performance in a limited given chiparea, and the actual device size is related to the channelwidth and the distance between source and drain contacts.In order to combine the advantages of both the MG FETsand recessed channel MOSFETs, in our previous work, weproposed saddle-shaped gate FETs with a U-shaped chan-nel [21–23], which promotes the gate controllability to the

horizontal channel part of the recessed channel from aplanar single-gate type to a 3-D triple-gate type. After that,we upgrade this 3-D triple-gate feature formed not only inthe horizontal channel part but also in both vertical chan-nel parts. This device is named as H gate U channel FETs,and the recessed channel is correspondingly upgraded to a3-D U-shaped tube channel too [24]. As mentioned above,the final goal of the design of the nano-scale device is therealization of the best performance in a limited given chiparea through optimization. To realize an optimizedhigh-performance device, both gate structure and thecorresponding channel structure should be well consid-ered and designed. Also the fabrication complexity shouldbe considered well. The devices mentioned above such as

a b

c d

Fig. 1 a 3D schematic view of the RGUC FET. b Profiles of the device cut through plane A of a. c Profiles of the device cut through plane B of a.d Profiles of the device cut through plane C of a

Liu et al. Nanoscale Research Letters (2019) 14:43 Page 2 of 7

the recessed channel device, the previously proposed sad-dle FETs, and HGUC FETs have a common ground, asandwich structure of gate oxide/gate/gate oxide shouldbe well formed in the small recessed region. This struc-tural feature limits its further promotion of integration. Itseems that a good way to promote the integration is tosimplify the structural feature in the recessed region andmaintain the gate control ability to the vertical channelpart and horizontal channel part of the U-shaped channelat the same time. In order to realize these device featuresand functions, in this paper, we proposed a novel rect-angular gate U channel FET (RGUC FET) for extreme in-tegrated distance between source and drain contacts. Ithas a U-shaped channel which can prolong the effectchannel length without increasing the distance betweensource and drain contacts. Compared to the otherU-shaped channel FETs, the RGUC FET is with a simplerinner structure in the recessed region of the U-shapedchannel; thereafter, it can realize simpler manufacture inthe inner part of the recessed region and smaller distancebetween source and drain contacts (higher integration).The proposed structure has better gate controllability andsmaller reverse leakage current accompanied with higherION/IOFF ratio. The distance between source contact anddrain contact can be scaled down to less than 2 nm. Thewhole electric properties are analyzed by quantumsimulations.

MethodsFigure 1a presents the 3D schematic view of the RGUCFET, and Fig. 1b to d are profiles of the device cutthrough planes A, B, C, and D shown in Fig. 1a. W isthe body width of the silicon, tb is the body thickness ofthe silicon, hin is the inner height of the spacer in therecessed region, hex is the height of the extensionsource/drain region, tox is the thickness of the gate oxidearound the silicon body, and tsp is the spacer thicknessof the insulator layer deposited in the recessed region ofthe U-shaped channel which equals to the distancebetween source contact and drain contact.Since the silicon body thickness is less than 6 nm,

quantum simulations are introduced in this paperinstead of classical simulations to obtain more precisesimulation results. All simulations are performed usingthe TCAD of SILVACO Atlas 3D device simulation,using the concentration-dependent mobility model,concentration-dependent Shockley-Read-Hall model,Auger recombination model, bandgap narrowing model,standard band-to-band tunneling model, and Bohmquantum potential model [25]. The simulation parame-ters are listed in Table 1. The two vertical body parts areactually cubes with four sides, the top surfaces of whichare covered with the source or drain region and the bot-tom surface are both connected to the horizontal body

part. The outer triple sides of the vertical body parts aresurrounded by the gate oxide and rectangular gatecontact, and the other inner side is connected to theinner spacer in the recessed region. The four sides of thehorizontal body are all surrounded by the gate oxide andthe rectangular gate contact. It is conjecturable that therectangular gate has a strong field-effect control abilityto both the horizontal body and the two vertical partsdue to the structure features mentioned above. And, theinner spacer actually prolonged the distance of theshortest path between source and drain contacts in thesilicon which could eliminate the short channel effectthat can not be avoided for multi-gate devices with planarchannel features. Compared to other 3-D channel devices[21–24], the proposed structure needs no gate formationin the recessed region, which largely reduces the complex-ity of the inner structure of the recessed region.

Results and DiscussionsThe Bohm quantum potential (BQP) model calculates aposition-dependent potential energy term using an auxil-iary equation derived from the Bohm interpretation ofquantum mechanics. This model is derived from purephysics and allows the model to approximate the quantumbehavior of different classes of devices as well as a range ofmaterials. The effects of quantum confinement on thedevice performance, including I-V characteristics, will thenbe calculated to a good approximation. Previous studiesshow that the gate leakage current is negligible for cases ofoxide thickness larger than 0.5 nm [7, 26].Figure 2a shows the comparisons of the drain-source

current gate-source voltage (IDS-VGS) characteristics ofthe RGUC FET with different hins on both logarithmicand linear scales. Figure 2b shows the comparisons ofsubthreshold swings (SS) and ION/IOFF ratio of the

Table 1 Parameter selection for RGUC FET in TCAD simulation

Parameters Values

Body width (W) 6 nm

Vertical body thickness (tbv) 6 nm

Horizontal body thickness (tbh) 6 nm

Spacer thickness between S/D region (tsp) 0.5 to 4 nm

Vertical length of the gate (tgate) 8 to 16 nm

Gate oxide layer thickness (tox) 1 nm

Extension height of spacer between S/Dregion (hex)

0 to 10 nm

Inner height of spacer in the recessedregion (hin)

3 to 10 nm

Doping concentration (ND) 1 × 1017 cm−3 to 2 × 1018

cm−3

Drain-source voltage (VDS) 0 to 1.0 V

Gate-source voltage (VGS) 0.4 to 1.0 V

Liu et al. Nanoscale Research Letters (2019) 14:43 Page 3 of 7

RGUC FET with different hins. With the increase of hin,the vertical path of the whole channel from source todrain is continuously increased, then the shortest effect-ive channel length increases gradually, and theshort-channel effect gradually weakens and is finallyeliminated. The SS can realize a nearly ideal value of 65mV/dec for hin reaches 10 nm. The ION/IOFF ratio alsoincreases about 35 times for hin increases from 2 to 10nm due to the continuously decreased SS. Theprolonged hin makes the distance of the shortest pathfrom source to drain increases from 6 to 22 nm, whichequals to 2 hin + tsp and is equivalent to the effectivechannel length of the proposed structure. Figure 2c andd show a 2-D electron concentration distribution in thesilicon body in off state for the device with 2 nm and10 nm hin, respectively. For the case of 2 nm, the highest

electron concentration in the horizontal body region isabout 1012 cm−3 and the distance between source/draincontact and the horizontal body region is very short.Thereafter, the source/drain bias seriously affect theelectron distribution in the horizontal body region; thesolution is to prolong the vertical channel which keepsthe source/drain away from the horizontal body region.For the case of 10 nm, in Fig. 2d, we can see that thehighest electron concentration in the horizontal body re-gion is decreased down to 109 cm−3, and it makes amore ideal fully depleted region for the off state whichbrings much lower level of leakage current.Figure 3a shows the comparisons of the IDS-VGS char-

acteristics of the RGUC FET with different tsps on bothlogarithmic and linear scales. Figure 3b shows thecomparisons of subthreshold swings (SS) and ION/IOFF

a b

c d

Fig. 2 a The comparisons of the IDS-VGS characteristics of the RGUC FET with different hins on both logarithmic and linear scales. b Thecomparisons of subthreshold swings (SS) and ION/IOFF ratio of the RGUC FET with different hins. c 2-D electron concentration distribution in thesilicon body in off state for the device with 2-nm hin. d 2-D electron concentration distribution in the silicon body in off state for the device with10 nm hin

Liu et al. Nanoscale Research Letters (2019) 14:43 Page 4 of 7

a b

c d

e

Fig. 3 (See legend on next page.)

Liu et al. Nanoscale Research Letters (2019) 14:43 Page 5 of 7

ratio of the RGUC FET with different tsps. With thedecrease of tsp, the distance between source and draincontacts are continuously decreased too. The leakagecurrent is mainly induced by band-to-band tunnelingcurrent. The tunneling probability is proportional to theband bending which can be equivalent to the electricfield intensity in a certain point. The total tunnelingcurrent is the sum of the tunneling current generated ineach point of the body region.Figure 3c and Fig. 2d show a 2-D electric field distri-

bution in the silicon body in off state for the device with2 nm and 0.5 nm tsp, respectively. For a larger spacerthickness or a smaller drain-source voltage (VDS) bias,the electric field intensity on the interface between thespacer in the recessed region is not strong enough toproduce a large amount of leakage current. The stron-gest electric field intensity appears near the interfacebetween the gate oxide and the vertical body part, whichis decided by VGD. However, if the source-to-drain dis-tance is decreased to less than 1 nm (less than the gateoxide thickness), the strongest field intensity appearsnear the interface between the spacer in the recessed re-gion and the two vertical body parts. It can be seen thatwhen tsp is less than 1 nm, for a larger VDS (0.5 V for ex-ample), the leakage current is almost independent withthe gate bias and mainly decided by the VDS. The SS isalmost independent with tsp and maintains a nearly idealvalue of 65mV/dec for a hin = 10 nm case until tsp is lessthan 2 nm. The ION/IOFF ratio maintains 10

8 till tsp = 2 nmand is seriously degraded for tsp less than 2 nm due to theleakage current increase induced by the strong electric

field appears near the interface between the spacer in therecessed region and the two vertical body parts. The electricfield intensity of the silicon body in the body region is com-prehensively enhanced for the 0.5 nm tsp case. Figure 3eshows 2-D electron concentration distribution in the siliconbody in off state for the device with 0.5 nm tsp. Comparedwith Fig. 2d, it is clearly seen that the electron concentrationin the horizontal body region is enlarged from 109 to 1010

cm−3. Besides, the dimension of 0.5 nm spacer thickness isvery close to a single-molecule layer, which may cause dam-age of the insulation property of the spacer layer to some de-gree. Due to the reason mentioned above, the tsp issuggested to be 2 nm for high-integration and low-leakagelow-power consumption design.Figure 4 shows the IDS-VDS of the proposed RGUC

FET with optimized structure under different.VGS values, the SS of which is about 63 mV/dec, and

the ION/IOFF is 109 ~ 1010. The saturated currentincreases as VGS increases.

ConclusionsA novel RGUC FET with high integration and high per-formance is proposed in this paper, which presentslow-subthreshold swings and higher ION/IOFF ratio. Thedistance between source/drain (S/D) contacts can bereduced to 2 nm, with almost ideal characteristics suchas SS, reverse leakage current, and ION/IOFF ratio. Allthe electrical properties are simulated with quantummodels to ensure more precise results.

AbbreviationsBQP: Bohm quantum potential; FET: Field-effect transistor; hex: Extension heightof spacer between S/D region; hin: Inner height of spacer in recessed region; IOFF:Off current; ION: On current; JL: Junctionless; MOS: Metal oxide semiconductor;ND: Doping concentration; RGUC: Rectangular gate U channel; S/D: Source/drain;SS: Subthreshold swing; tbh: Horizontal body thickness; tbv: Vertical body thickness;tgate: Vertical length of the gate; tox: Gate oxide layer thickness; tsp: Spacer thicknessbetween S/D region; VDS: Drain-source voltage; VGS: Gate-source voltage;W: Body width

AcknowledgementsThis work is supported by the Natural Science Foundation of Liaoning ProvinceNo.201602541, No.201602546.

FundingThis work is supported by the Natural Science Foundation of Liaoning ProvinceNo.201602541, No.201602546.

Availability of Data and MaterialsWe included a statement of availability of data and material for ourselvesand on behalf of our co-authors under the ‘Competing interests’. All availabil-ity o data and material are original work.

(See figure on previous page.)Fig. 3 a The comparisons of the IDS-VGS characteristics of the RGUC FET with different tsps on both logarithmic and linear scales. b Thecomparisons of subthreshold swings (SS) and ION/IOFF ratio of the RGUC FET with different tsps. c 2-D electric field distribution in the silicon bodyin off state for the device with 2 nm tsp. d 2-D electric field distribution in the silicon body in off state for the device with 0.5 nm tsp. e 2-Delectron concentration distribution in the silicon body in off state for the device with 0.5 nm tsp

Fig. 4 IDS-VDS characteristic of the proposed RGUC FET withoptimized device parameters

Liu et al. Nanoscale Research Letters (2019) 14:43 Page 6 of 7

DeclarationsWe have read Springer Open’s guidance on competing interests and includeda statement of all financial and non-financial competing interests for ourselvesand on behalf of our co-authors under the ‘Competing interests’.

Authors’ ContributionsAll the sections of the manuscript are contributed by all the authors. All authorsread and approved the final manuscript.

Authors’ InformationXi Liu received the B.S. and M.S. degrees in applied mathematics from DalianUniversity of Technology, Dalian, China, in 2004 and 2006, respectively. Shereceived the Ph.D. degree in semiconductor and display engineering fromKyungpook National University, Daegu, Korea, in 2010. She works in the Schoolof Information Science and Engineering, Shenyang University of Technology asan associate professor. Her research interests include design and optimization ofadvanced integrated circuits and semiconductor devices.Zhengliang Xia is currently working toward the M.S. degree in the Schoolof Information Science and Engineering, Shenyang University of Technology,Shenyang, China. His research interests include design and optimization ofMOSFETs and tunneling FETs.Xiaoshi Jin received the B.S. degree in physics from Dalian University of Technology,Dalian, China, in 2004, the M.S. degree in physics from Gyeongsang NationalUniversity, Jinju, Korea, in 2006 and the Ph.D. degree in semiconductor and displayengineering from Kyungpook National University, Daegu, Korea, in 2010. He worksin the School of Information Science and Engineering, Shenyang University ofTechnology as an associate professor. He has authored or coauthored more than 30papers published in refereed journals and has been granted more than 20 patentsin this area His research interests include semiconductor physics and devicemodeling, design of advanced semiconductor devices and ICs.Jong-Ho Lee received the Ph.D. degree from Seoul National University, Seoul,in 1993, in electronic engineering. In 1994, he was with the School ofElectrical Engineering, Wonkwang University, Iksan, Chonpuk, Korea. In 2002,he moved to Kyungpook National University, Daegu Korea, as a Professor ofthe School of Electrical Engineering and Computer Science. Since September2009, he has been a Professor in the School of Electrical Engineering, SeoulNational University, Seoul Korea. From August 1998 to July 1999, he was withMassachusetts Institute of Technology, Cambridge, as a postdoctoral fellow.He has authored or coauthored more than 200 papers published in refereedjournals and over 280 conference papers related to his research and hasbeen granted more than 100 patents in this area. His research interestsinclude CMOS technology, non-volatile memory devices, thin film transistors,sensors, bio interface, and neuromorphic technology. He has been served asa subcommittee member of IEDM, ITRS ERD member, a general chair ofIPFA2011, and IEEE EDS Korea chapter chair. In 2006, he was a recipient ofthe “This Month’s Scientist Award” for his contribution in the developmentof practical highdensity/high-performance 3-dimensional nano-scale CMOSdevices. He invented Saddle FinFET (or recess FinFET) for DRAM cell andNAND flash cell string with virtual source/drain, which have been applyingfor mass production.

Competing InterestsAll authors declare that they have no competing interests.

Publisher’s NoteSpringer Nature remains neutral with regard to jurisdictional claims in publishedmaps and institutional affiliations.

Author details1School of Information Science and Engineering, Shenyang University ofTechnology, Shenyang 110870, China. 2School of EECS Eng. and ISRC(Inter-University Semiconductor Research Center), Seoul National University,Shinlim-Dong, Kwanak-Gu, Seoul 151-742, Korea.

Received: 15 October 2018 Accepted: 27 January 2019

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AbstractIntroductionMethodsResults and DiscussionsConclusionsAbbreviationsAcknowledgementsFundingAvailability of Data and MaterialsDeclarationsAuthors’ ContributionsAuthors’ InformationCompeting InterestsPublisher’s NoteAuthor detailsReferences