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SoC 설계 기초. 성균관대 조준동 교수. 목차. 가 . SoC Design Flow 나 . HW/SW Co-design 다 . platform-based design 라 . Network-on-chip 마 . 저전력 설계. 가 . SoC Design Flow. 성균관대 조준동 교수. 목차. SoC 설계 동향 3G 를 위한 설계 방법 설계 플로루 지적재산을 이용한 설계 방법 다양한 설계 방법 형태. SOC. - PowerPoint PPT Presentation
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SoC 설계 기초
성균관대 조준동 교수
목차 가 . SoC Design Flow
나 . HW/SW Co-design
다 . platform-based
design
라 . Network-on-chip
마 . 저전력 설계
가 . SoC Design Flow
성균관대 조준동 교수
목차
SoC 설계 동향3G 를 위한 설계 방법설계 플로루 지적재산을 이용한 설계 방법 다양한 설계 방법 형태
SOC
What are you going to do with that many transistors?
Componentbased design
Real Components
Virtual Components
System on Multiple Boards System on a Chip
IP
Processor Performance
(~Moore’s Law)2016: 2500 MIPS
(Source: MorphICs)
Algorithmic Complexity(Shannon’s Law)
97 99 ‘01 ‘03 ‘05 ‘07
Log
Gro
wth
Processor
PerformanceW
AN/MAN B
andw
idth
100
10,000
1M
2x/3-6 months
2x/18 months
1000 x
Shannon Beats MoreShannon Beats More
속도
2GHz밴드폭
14.4Mbps 100 Mbps
10MB/200sec다운로드
Image Bit Rate 385kbps 24MbpsX2
175W
CPU 800 Mhz
15Mbytes
5-10GHz
1B gates
3-6Ghz
에너지 소모량 30-50W
Contents 700kbytes
100MB/10sec
3G 3.5G 4G
1999 2001 2003 2005 2007 2010
시장전망 ( 단말기 )
- 개인화 : Context-aware Sensor Networks
- 고속화 : NoC 기술 - 저전력화 : ACM, PSM, DVS, GC, LCC - 재사용화 : Hardware/Software Co-design
* 출처 ETRI, 2000
집적도 200M gates
0
100,000
150,000
200,000
250,000
300,000
350,000
2000 2001 2002 2003 2004 2005 2006
Year
Reven
ue(m
illion
$)
Technology RoadmapTechnology Roadmap
Radio systems
WiFi – 10-100Mbits/sec unlicensed band OFDM, M-ary coding
3G – .1-2 Mbits/sec wide area cellular CDMA, GMSK
Bluetooth – .8 Mbit/sec cable replacement Frequency hop
ZigBee – .02-.2 Kbits/sec low power, low cost QPSK
UWB – Recently allowed by FCC Short pulses (no carrier), bi-phase or PPM
Power Dissipation
1 mW
10 mW
100 mW
1 W
10 W
0 GHz 2 GHz1GHz 3 GHz 5 GHz4 GHz 6 GHz
802.11a
UWB
UWBZigBee
Bluetooth
ZigBee
802.11bg3G
Cost (projections)
$ .10
$1
$10
$100
$1000
0 GHz 2 GHz1GHz 3 GHz 5 GHz4 GHz 6 GHz
802.11a
UWB
UWBZigBee
BluetoothZigBee
802.11b,g
3G
Data rate
10 kbits/sec
100 kbits/sec
1 Mbit/sec
10 Mbit/sec
100 Mbit/sec
0 GHz 2 GHz1GHz 3 GHz 5 GHz4 GHz 6 GHz
802.11a
UWBZigBee
Bluetooth
ZigBee
802.11b
802.11g
3G
UWB
Integration on SOC on CMOS Process
‘Top Ten Obstacles to 3G Wireless Technology’
Stable StandardsIncreased DSP PerformanceSoftware SophisticationLower Power ConsumptionAdvanced Power ManagementIncreased Battery Capacity3G OSesEnhanced Radio TechnologyCost ConcernsInnovative Applications
from: Carl Panasik “Overcoming Obstacles to 3G Wireless Technology”, Communications System Design, January, 2001, pp. 11-12.. Reused with permission. Carl Panasik is in the Wireless Unit of TI.
Multimedia Cell phone Challenges
3G WCDMA communications channel Complexity 5x to 6x greater than GSM Higher throughput with lower power Wider bandwidth with increased linearity Multi-standard capability
Combined challenges of wireless video Managing BER impacts on video quality FEC -- forward error correction Managing bandwidth and video quality Higher power efficiency Higher integration -- digital logic, memory, mixed-signal, &
RF Lower cost
· SOC Design Trends
Expected to integrate more and more complex• Web-browsing, real-time video processing,
speech recognition and synthesis
Average operating power at or below 100mW and standby power levels at or below 2mW
Performance levels must increase from 300 million operations per second (MOPS) today to 2500 MOPS in 2016
Four main applications
Set-top box: Mobile multimedia system, base station for the home local-area network.
Digital PCTV: concurrent use of TV,3D graphics, and Internet services
Set-top box LAN service: Wireless home-networks, multi-user wireless LAN
Navigation system: steer and control traffic and/or goods-transportation
Achieving functionality while maximizing battery life and minimizing size
Medical
watch
Cellular phone
Digital still camera
Hearing
aid
Cochlear implant GPS
Portable
audio Digital radio
Noise cancellationheadphones
Implementation Choices for a 3G Device Cadence
Image processingI/O Channels
RF WIRELESS
RISC/DSP/ASICPixel Defect MaskingDemosaic, Gamma
RGB-YUV, JPEG I/O & Network Stack
SRAM/DRAM/FlashMEMORY
A/D
Mic
A/D
MEMORY
RISC/DSP/ASICG.723.1/ADPCM
Audio Compression
IrDA
Photo MEMORYFlash
Multilevel Flash Disk, DVD
BATTERY
CHARGER/PWR MGMT
UNTETHERED CAMERAAmp
LCD DisplayView Finder
Sensor
I/O
1394/FireWire
Blue Tooth
USB Node
V.90 Modem
ETHERNET
3G WCDMA
PCI
Video/Ch3 RF
Does the IP integrate throughout the flow?
What information is required to integrate
IP?
How can I use IP standards?
What is my IP supplier chain process?
How do I reuse my own IP?
If I change architecture,
what happens to performance?
Will this platform
meet cost targets?
What IP do I build, what IP do I
buy?What do I reuse?
What functions
do Iintegrate?
SoC Design Flow
Structured SoC Designs
Hierarchy: Subdivide the design into many levels of sub-modules
Regularity: Subdivide to max number of similar sub-modules at each level
Modularity: Define sub-modules unambiguously & well defined interfaces
Locality: Max local connections, keeping critical paths within module boundaries
The SoC platform
hardwareplatform
for (I=0; I<N; I++) a[I] = b[I]*c[I];...
applicationsoftware
System-on on-Chip components
Common Fabric for IP Blocks
Soft IP blocks are portable, but not as predictable as hard IP.
Hard IP blocks are very predictable since a specific physical implementation can be characterized, but are hard to port since are often tied to a specific process.
Common fabric is required for both portability and predictability.
Wide availability: Cell Based Array, metal programmable architecture that provides the performance of a standard cell and is optimized for synthesis.
Why SOC?
• SOC specs are coming from ICT system SOC specs are coming from ICT system engineers rather than RTL descriptionsengineers rather than RTL descriptions
•SOC will bridge the gap b/w s/w and their SOC will bridge the gap b/w s/w and their implementation in novel, energy-efficient implementation in novel, energy-efficient silicon architecture.silicon architecture.
•In SOC design, chips are assembled at IP In SOC design, chips are assembled at IP block level (design reusable) and IP interfaces block level (design reusable) and IP interfaces rather than gate level rather than gate level
Types of System-on-a-Chip Designs
임베디드 프로세서 (ARM) 0.5 MOPS/mW
신호처리 프로세서ASIPs, DSPs
3 MOPS/mW
신호처리ASIC
가용성
에너
지 효
율(M
OP
S/m
W)
0.1
1
10
100
1000
200 MOPS/mW
10-80 MOPS/mW
6
재구성 구조
Energy-Flexibility Gap
Physical gap
Timing closure problem: layout-driven logic and RT-level synthesis
Energy efficiency requires locality of computation and storage: match for stream-based data processing of speech,images, and multimedia-system packets.
Next generation SOC designers must bridge the architectural gap b/w system specification and energy-efficient IP-based architectures, while CAE vendors and IP providers will bridge the physical gap.
Circular Y-Chart
Implementing Digital Systems
The 100 Million Transistor Question
HOW BEST CAN WE USE THEM TO SOLVEOUR COMPUTING PROBLEMS ?
Answer I: Multiprocessor on a chip
Requirement: Efficient, parallelizing compiler
Problems: Enough parallelism in programs?Does not go fast enough for video applications, for instance.
Answer II: Giant FPGA
Requirement: CAD system for FPGAsProblems: May work well for bit- levelvideo computations, but in generalFPGAs are inefficient.
Answer III: H/W and S/W Co-design
ASIP Design
Given a set of applications, determine micro architecture of ASIP (i. e., configuration of functional units in datapaths, instruction set)
To accurately evaluate performance of processor on a given application need to compile the application program onto the processor datapath and simulate object code.
The micro architecture of the processor is a design parameter!
ASIP Design Flow
Alternatives for Semiconductor
Quantum ComputingDNA ComputingOptical ComputingMolecular Computing