SOC Consortium Course Material Memory Controller National Taiwan University Adopted from National Taiwan University SoC Design Laboratory

SOC Consortium Course Material

Memory ControllerMemory Controller

National Taiwan UniversityAdopted from National Taiwan University

SoC Design Laboratory

2SOC Consortium Course Material

Goal of This Lab

Familiarize with ARM memory interfaceKnow ARM Integrator memory map wellHow to access memory


Outline

The ARM Memory Interface [1]ARM Integrator System Memory Map [2] [3]


Simple Memory Interface

The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM).

8-bit memory types, so four parts of each type are required to form a 32-bit memory.

Since the bottom two address lines, A[1:0], are used for byte selection, they are used by the control logic and not connected to the memory.

Although the ARM performs reads of both bytes and words, the memory system can ignore the difference and always simply supply a word quantity.


Basic ARM Memory System

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

ROM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

D[7:0]

SRAM

control

D[7:0]

D[31:0] D[31:24] D[23:16] D[15:8] D[7:0]

A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2]

A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2]

RAMoe

RAMwe3 RAMwe2 RAMwe1 RAMwe0

ROMoe

ARM

D[31:0]

A[31:0] oe we

A[n:0]

oe we

A[n:0]

oe we

A[n:0]

oe we

A[n:0]

A[n:0]

oeA[n:0]

oeA[n:0]

oeA[n:0]

oe

A[31:0]

various


Control Logic

It decides when to activate the RAM and when to activate the ROM– A[31] = 0 => access ROM– A[31] = 1 => access RAM

It controls the byte write enables during a write operation– Word write / half-word write / byte write

It ensures that the data is ready before the processor continues


Simple ARM Memory System Control Logic

RAMwe0

RAMwe1

RAMwe2

RAMwe3

mclk

A[0] A[1]mas[0] mas[1]

RAMoe

ROMoe

A[31]

r/w

Write

Read


Transfer Widths

A[31] r/wmas[1]

mas[0]

A[1]

A[0]

Output signal

0 0 × × × × ROMoe

0 1 × × × × None

1 0 × × × × RAMoe

1 1 0 0 × ×None

1 1 1 1 × ×

1 1 1 0 × ×Word (RAMwe0, RAMwe1,

RAMwe2, RAMwe3)

1 1 0 1 0 ×Half word (RAMwe0, RAMwe1)

1 1 0 1 1 ×Half word (RAMwe2, RAMwe3)

1 1 × × 0 0 Byte (RAMwe0)

1 1 × × 0 1 Byte (RAMwe1)

1 1 × × 1 0 Byte (RAMwe2)

1 1 × × 1 1 Byte (RAMwe3)

Write

Read


DRAM memory organization

ras

cas

A[n:0]

dataout

array ofmemory

cells

mux

latch

latch

decoder

ras: row address strobe cas: column address strobe


Outline

The ARM Memory Interface [1]ARM Integrator System Memory Map [2][3]


Core Module Memory Map

The nMBDET signal is permanently grounded by the motherboard so that it is pulled LOW on the core module when it is fitted.

The REMAP bit only has effect if the core module is attached to a motherboard (nMBDET = 0).


Core Module Memory Map (cont.)

256MB

256KB

8MB

8MB


Core Module Alias Address


Memory Map for Core Module

REMAP = 0: Default following reset. Accesses to addresses 0x00000000 to 0x0003FFFF– S1[1] = ON: the access is to boot ROM– S1[1] = OFF: the access is to flash

REMAP = 1: Accesses to address 0x00000000 to 0x0003FFFF


System Memory Map (1/2)


System Memory Map (2/2)


References

[1] http://access.ee.ntu.edu.tw/course/SOC_LAB/index.html

[1] ARM System-on-Chip Architecture by S.Furber, Addison Wesley Longman: ISBN 0-201-67519-6.

[2] DUI0098B_AP_UG.pdf.

[3] DUI0126B_CM7TDMI_UG.pdf


Experiment Requirements

Try to compile the program of this experiment by using Thumb code to get the same result. Modify the memory usage if needed.

Make a table to show the statistics (memory and cycle requirement) about ARM codes and Thumb codes and compare their difference.

Documents

SOC Consortium Course Material Memory Controller National Taiwan University Adopted from National Taiwan University SoC Design Laboratory