SoC Design Flow

7/30/2019 SoC Design Flow

1/21

Jouni Tomberg / TUTJouni Tomberg / TUT 1126.03.200326.03.2003

SystemSystem--onon--Chip Design FlowChip Design Flow

Prof. Jouni TombergProf. Jouni Tomberg

Tampere University of TechnologyTampere University of Technology

Institute of Digital and Computer SystemsInstitute of Digital and Computer Systems

[email protected]@tut.fi


2/21

26.03.200326.03.2003 Jouni Tomberg / TUTJouni Tomberg / TUT 22

SoCSoC -- How and with whom?How and with whom?

SoC PlayersSoC Players

MarketsMarkets

FlowsFlows

BottlenecksBottlenecks

IP and platform metricsIP and platform metrics


3/21


DefinitionsDefinitions

Frontend designFrontend design Design from system level to cell library level netlistDesign from system level to cell library level netlist

Backend designBackend design Design from netlist level to Placed & Routed productionDesign from netlist level to Placed & Routed production

ready databaseready database

ASIC flowASIC flow Netlist handoff to ASIC vendor (takes care of the backend)Netlist handoff to ASIC vendor (takes care of the backend)

COT (Customer Owned Tooling) flowCOT (Customer Owned Tooling) flow P&R database handoff to foundry (takes care of theP&R database handoff to foundry (takes care of the

production)production)


4/2126.03.200326.03.2003 Jouni Tomberg / TUTJouni Tomberg / TUT 44

SoC PlayersSoC Players

Customer

(end user)

IP provider

Design

Serviceprovider

ASIC vendoror

Foundry

Standardfunctionblocks

Requirement specification

Physicalbackannotation

Netlist orP&Rdatabase

IC's

Productionrequirements


5/21


Need for System Level DesignNeed for System Level Design


6/21


Market SegmentsMarket Segments


7/21


Design Productivity GapDesign Productivity Gap


8/21


Typical Design Flow TasksTypical Design Flow Tasks

Implement

Verify

Models/IP

System/

Algorithm

Behaviora

l

RTL

Gate-leve

l

Transisto

r/

Physical

Define System

Create/select

Algorithms

Filter design

Protocol

Development

Verify system

function

Verify Algorithm

performance

System Simulation

HW/SW Coverification

System model

components

System environments

Reference Kits

Create behavioral

description

Code generation

Wordlength optimizatiuon

Architectural Tradeoffs

Partitioning

Verify behavioral

description (function

and performance)

Simulation

Testbench Generation

HW/SW Coverifiication

Behavioral models

RAM Models

Part models

Bus ModelsCores

Create RTL

description

Behavioral Synthesis

Code generation

Design Planning

Verify RTL

description

(function and

performance)

Simulation

Power Analysis

RTL quality analysisEmulation

RTL models

RAM models

Part models

Bus ModelsCores (functional &

timing Models)

Create Netlist

Optimize Netlist

Logic Synthesis

Datapath Synthesis

Test Synthesis

Power Optimization

Retiming

Verify Netlist

(function and

performance)

Simulation

Equivalence Checking

Static Timing Analysis

Power AnalysisTest Analysis/ATPG

Gate models

Bus Models

Synthesis/simulation

libraries

Create physicalrepresentation

Place & Route

Clock-tree synthesis

Power Routing

Transistor Optimization

Verify physical

design

DRC, LVS

Power analysis

Rail analysis

Static Timing analysis

Parasitic Extraction

Physical/transistor

models

Std Cell libraries

Gate Array libraries


9/21


Design FlowsDesign FlowsSource: T. Moxon / EEDesign, 2.1.2002


10/21


ASIC design flow interfacesASIC design flow interfacesDESIGN TEAM CUSTOMER ASIC VENDOR

Requirement spec

Technical info for quotation

ASIC quotation

Library & tools

Data sheet for acceptance

Verification for acceptance

(modeler/testbench/simul.results)

Netlist, test vectors, arch.plan

Backannotation from P&R

Acceptance for prototype production (sign off)

Prototype ASICs (/risk production)

Prototype acceptance

Mass production ASICs


11/21


Importance of SpecificationImportance of Specification


12/21


Design BottlenecksDesign Bottlenecks * Source EETIMES EDA 2000 Survey

32%

32%

26%

17%

17%

Design Creation

Place & RoutePost Layout Optimization

Parasitic Extraction

System or System-on-Chip

Simulation/Design Verification 51%

Layout Versus Schematic(LVS)Design Rule Check (DRC)

17%

Static Timing Analysis 16%

Synthesis 15%

Base = 545Delay Calculation 13%

0% 10% 20% 30% 40% 50% 60%

50 -70 % of project effort devoted to design verification!


13/21


Verification ImportanceVerification Importance


14/21


Project SchedulingProject Scheduling External constraintsExternal constraints

Targeted market entryTargeted market entry

ASIC vendorASIC vendor

Layout generation (P&R)Layout generation (P&R) Mask producingMask producing Prototype processingPrototype processing Prototype acceptancePrototype acceptance

Volume production starting delayVolume production starting delay Design constraintsDesign constraints

Design team experienceDesign team experience

Design tools / flows, vendor libraries, IP provider qualityDesign tools / flows, vendor libraries, IP provider quality

System specification iterationsSystem specification iterations

Design complexityDesign complexity

Verification complexityVerification complexity

Production test complexityProduction test complexity


15/21


Differencies between SoC and SoPCDifferencies between SoC and SoPC

design flowsdesign flows SoPC is a FPGA technology based user programmableSoPC is a FPGA technology based user programmablesolutionsolution

P&R and programming done by the user (vs. backend flow inP&R and programming done by the user (vs. backend flow inSoC)SoC) No delay on prototype productionNo delay on prototype production

No delay on mass production startNo delay on mass production start No NRE (production start) costsNo NRE (production start) costs

Production tests done by the IC vendorProduction tests done by the IC vendor Design resource and time savings in the design flowDesign resource and time savings in the design flow

Quick and cheap modificationsQuick and cheap modifications

On the other hand certain limitations on performance,On the other hand certain limitations on performance,integration capacity and mass production costs existsintegration capacity and mass production costs exists

compared to SoCcompared to SoC


16/21


Platform Based DesignPlatform Based Design

A platform should consist of a basic set ofA platform should consist of a basic set ofintegrated technologies that defines how theintegrated technologies that defines how the

system should function.system should function. Design platform / Verification platformDesign platform / Verification platform

Generic platformGeneric platform CPU, memory and standard peripheral fucntionsCPU, memory and standard peripheral fucntionsApplication specific platformApplication specific platform

Generic platform plus preGeneric platform plus pre--integrated IP blocks forintegrated IP blocks forthe given applicationthe given application


17/21


Platform driversPlatform drivers

Source: B. Altizer, L. Cooke, and G. Martin / EEDesign 7.11.2002


18/21


Platform AdvantagesPlatform Advantages Reduce integration risk by insuring that all IP worksReduce integration risk by insuring that all IP works

togethertogether

Reduce licensing and contractual negotiation timeReduce licensing and contractual negotiation time

per projectper project Reduce cost by allowing efficient reuse in multipleReduce cost by allowing efficient reuse in multiple

designsdesigns

It is estimated that in the near future each SoCIt is estimated that in the near future each SoCdesign will consist of 10 to 15 different IP blocksdesign will consist of 10 to 15 different IP blocksfrom 6 to 8 IP vendorsfrom 6 to 8 IP vendors

Suppose 6 to 8 weeks per IP vendor for evaluation,Suppose 6 to 8 weeks per IP vendor for evaluation,negotiation and integration of IP into the systemnegotiation and integration of IP into the system=> with 8 different IP vendors this means 64 weeks of=> with 8 different IP vendors this means 64 weeks ofhidden costhidden cost


19/21


IP Market DynamicsIP Market Dynamics Design dynamics (Dataquest 2002)Design dynamics (Dataquest 2002)

30% of a designs are composed of reused circuitry30% of a designs are composed of reused circuitry

12% of reused circuit is from outside sources12% of reused circuit is from outside sources=> 3.6% of circuitry is from third parties=> 3.6% of circuitry is from third parties

Contractual and legal issuesContractual and legal issues Legal issues remain a huge bottleneck in the IP purchase processLegal issues remain a huge bottleneck in the IP purchase process rights, responsibility, guarantee, business modelrights, responsibility, guarantee, business model

VCX trying to address this bottleneck (with standard Ts &Cs)VCX trying to address this bottleneck (with standard Ts &Cs)

Evaluation of IPEvaluation of IP Deciding if a core is viable is biggest technical challenge in IDeciding if a core is viable is biggest technical challenge in IP acquisitionP acquisition

process.process.

Opportunities in IP evaluation servicesOpportunities in IP evaluation services

Perceived instability of vendors..Perceived instability of vendors..

Most IP vendors are small and vulnerableMost IP vendors are small and vulnerable Partnerships and alliance can help to resolve perceived volatiliPartnerships and alliance can help to resolve perceived volatilityty

Software replacing hardwareSoftware replacing hardware Proliferation of processors in ICsProliferation of processors in ICs

Resulting in more functions being implemented in softwareResulting in more functions being implemented in software SW/HW coSW/HW co--design!design!


20/21


IP Market MetricsIP Market Metrics

46%CAGR46%CAGR

75% License Revenue 25% Royalty Revenue75% License Revenue 25% Royalty Revenue


21/21


ConclusionsConclusions

The main players in the SoC design flow are DesignThe main players in the SoC design flow are Designteam, IP provider, IC vendor (or Backend team +team, IP provider, IC vendor (or Backend team +

Foundry)Foundry) Efficient SoC design flow is based on IP reuse andEfficient SoC design flow is based on IP reuse and

platform based designplatform based design

The major bottlenecks are in the test and verificationThe major bottlenecks are in the test and verificationareaarea

The system level (specification, HW/SW coThe system level (specification, HW/SW co--design)design)and layout level links to RTL design play also anand layout level links to RTL design play also animportant role in a fluent design flowimportant role in a fluent design flow

Documents

SoC Design Flow