Soft Macrocell Model for Cortex-A15 User Guide - Arm Macrocell Model for Cortex-A15 User Guide Copyright © 2011 ARM Limited. All rights reserved. Page 7 of 20. Open Access 4 GETTING

Copyright © 2011 ARM Limited. All rights reserved. Page 1 of 20.

Open Access

Soft Macrocell Model

for Cortex-A15

User Guide

System Design Division

Document number:

Date of Issue: 29 September 2011

Authors: ARM SDPL

© Copyright ARM Limited 2010-2011. All rights reserved.

Abstract

This document describes several variants of a Cortex-A15 Soft Macrocell Module implemented using LogicTile Express 13MG (V2F-2XV6) development boards.

Keywords

Cortex, A15, SMM, FPGA, Versatile Express,

Soft Macrocell Model for Cortex-A15 User Guide


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Contents

1 ABOUT THIS DOCUMENT 3 1.1 Change history 3 1.2 References 3 1.3 Terms and abbreviations 4

2 SCOPE 5

3 INTRODUCTION 5 3.1 Hardware required 5

4 GETTING STARTED 7 4.1 Hardware assembly 7

4.1.1 Installing LogicTiles into V2M-P1 chassis 7 4.1.2 Upgrading the Power Supply and 12V power cables 7 4.1.3 Making the JTAG connection 8 4.1.4 Installing DDR2 SODIMMs 8

4.2 Installing the SMM file bundle on a host PC 8 4.3 Installing Boardfiles into the LogicTiles 8

5 SYSTEM OVERVIEW 9 5.1 General overview 9 5.2 SMM Features 9

5.2.1 Processor Configurations 9 5.2.2 Debug features 10

5.3 Detailed System Architecture 11 5.3.1 Dynamic Memory Controller (DMC) 12 5.3.2 System Configuration Controller (SCC) 12 5.3.3 Static Memory Controller (SMC) 12 5.3.4 Accelerator Coherency Port (ACP) 13 5.3.5 DMA Controller (DMAC) 13 5.3.6 ZBT RAM Controller 13 5.3.7 High-Definition LCD Controller (HDLCDC) 13

5.4 Clock architecture 14 5.4.1 Clock Domains 14 5.4.2 Default, minimum and maximum operating frequencies 14

6 PROGRAMMERS MODEL 15 6.1 Memory Map 15

6.1.1 DMA memory remap 17 6.1.2 SCC Register block 17

6.2 Interrupt and Event signal assignments 19



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1 ABOUT THIS DOCUMENT

1.1 Change history

Brief descriptions of major changes are described here:

Version Status Remark

1 First Release

2 Second Release With comprehensive assembly instructions

Table 1-1 Change history

1.2 References

This document implicitly refers to the following documents.

Ref Doc No Author(s) Title

ARM DUI 0447D ARM Ltd. Motherboard Express μATX V2M-P1

TRM

ARM DUI 0541A ARM Ltd. CoreTile Express A5x2 TRM

ARM DDI 0424B ARM Ltd. PrimeCell DMA Controller (PL330) Revision:r1p0 TRM

ARM DDI 0397F

ARM Ltd. AMBA® Network Interconnect (NIC-301) Revision:r2p0 TRM

ARM DDI 0418C ARM Ltd. PrimeCell® DDR2 Dynamic Memory Controller (PL341) Revision:r0p1 TRM

ARM DDI 0380G ARM Ltd. PrimeCell® Static Memory Controller

(PL350 series) Revision:r2p1 TRM

ARM DDI 0314H ARM Ltd. CoreSight Components TRM



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1.3 Terms and abbreviations

This document uses the following terms and abbreviations.

Term Meaning

ACP AXI Coherence Port

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

ATB Advanced Trace Bus

AXI Advanced eXtensible Interface

DAP Debug Access Port

DCC Daughterboard Configuration Controller

DCM Digital Clock Manager

DMA Direct Memory Access

DMAC Direct Memory Access Control

DMC Dynamic Memory Controller

ECC Error Correction Code

ETB Embedded Trace Buffer

ETM Embedded Trace Macro-cell

GIC Generic Interrupt Controller

HPM High Performance Matrix

LLPP Low Latency Peripheral Port

SCC System Configuration Controller

SCU Snoop Control Unit

SMC Static Memory Controller

SVN SubVersioN, a version control system

TCM Tightly Coupled Memory

TPIU Trace Port Interface Unit

VE Versatile Express

VIC Vectored Interrupt Controller



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2 SCOPE

This document describes features that are unique to the Cortex-A15 Soft Macrocell Model (SMM) implemented on one or more LogicTile Express 13MG (V2F-2XV6) boards. It will examine the contents of the SMM-A15, system interconnect, the clock structure, and specifics of the programmer’s model directly relevant to SMM-A15 operation.

Hereafter in this document, the LogicTile Express 13MG board is referred to as V2F-2XV6. The Cortex-A15 Soft Macrocell Model is referred to as SMM-A15.

3 INTRODUCTION

Three separate variants of the SMM-A15 have been made available:

Configuration

Number

SMM-A15

Variant Name

Cortex-A15 configuration

Hardware

Required

Notes

1 SMM-A15x1 Cortex-A15 MP1 no NEON no VFP

1x V2F-2XV6 Only synchronous AXI matrix, No ZBTRAM, No HDCLCD,

2 SMM-A15x1N Cortex-A15 1MPCore + NEON 2x V2F-2XV6 Subsystem asynchronous to core

3 SMM-A15x2N Cortex-A15 2MPCore + NEON 3x V2F-2XV6 Subsystem asynchronous to core

Table 3-1 SMM-A15 configurations

Throughout the remainder of this document, the term „SMM-A15‟ is used to denote any of these configurations, as selected by the user. Where necessary, the specific SMM variant name or Configuration Number from the above table is used.

3.1 Hardware required

The SMM-A15 is based on single or stacked V2F-2XV6 FPGA daughterboards, mounted on a Versatile Express V2M-P1 baseboard. The SMM-A15 cannot be used on any other motherboard, for three reasons: 1) The SMM-A15 does not have an external AXI expansion bus, which is the primary reason for putting an ARM Versatile Express daughterboard on a non-standard motherboard. The only peripheral connectivity is provided through the Static Memory Bus to the V2M-P1. 2) The inter-FPGA timing has been set for use on the V2M-P1 motherboard. 3) The interface specification for each component LogicTile in the SMM-A15 is not available.

The following diagrams illustrate the three SMM-A15 variants, as assembled. It should be noted that for the SMM-A15x2N, although two of the LogicTiles appear to have very similar content, they are subtly different and are not interchangeable once programmed.



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LogicTile

V2F-2XV6

V2M-P1 motherboard

IO FPGA

LX550T

SCU,

Memory,

Peripherals

HDRY HDRX HDRY HDRX

Tile Site 2 Tile Site 1

LX760

CPU

Figure 3-1 Configuration 1 : SMM-A15x1

LogicTiles

V2F-2XV6

V2M-P1 motherboard

IO FPGA

LX550T

NEON

(& part CPU)

LX550T

Memory,

Peripherals

LX760

Cortex-A15

CPU

LX760

SCU, GIC

L2 Cache

HDRY HDRX HDRY HDRX


Figure 3-2 Configuration 2 : SMM-A15x1N

LogicTiles

V2F-2XV6

V2M-P1 motherboard

LX550T

NEON1

(& part CPU1)

IO FPGA

LX550T

NEON0

(& part CPU0)

LX550T

Memory,

Peripherals

LX760

Cortex-A15

CPU1

LX760

Cortex-A15

CPU0

LX760

SCU, GIC

L2 Cache

HDRY HDRX HDRY HDRX


Figure 3-3 Configuration 3 : SMM-A15x2N



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4 GETTING STARTED

Follow all of the steps in this chapter to ensure that the SMM-A15 is fully installed and configured.

4.1 Hardware assembly

4.1.1 Installing LogicTiles into V2M-P1 chassis

Assemble enough V2F-2XV6 LogicTile boards onto a V2M-P1 baseboard as per section 3.1, and as required to build the chosen SMM-A15 variant. Note that if three LogicTiles are available, they can be left permanently installed on the V2M-P1 motherboard and any of the three SMM-A15 variants can be selected by reprogramming the LogicTiles via the USB interface on the motherboard. In this scenario, ‘safe’ binary images are loaded into unused tiles.

4.1.2 Upgrading the Power Supply and 12V power cables

The standard 60W, 12V ‘brick’ power supply unit supplied with V2M-P1 motherboards does not have sufficient capacity to support three LTE-13MG LogicTiles. Also, the coaxial 12V DC input jack on the back panel of the motherboard is not rated for the typical input current that the SMM-A15 requires. Ideally, an alternative PSU should be used, such as RS part number 667-7261. This is a 150W unit with a 4-pin output plug. An updated rear panel for the V2M-P1 is available with the mating 4-pin socket. It is possible to install the updated rear panel without removing the HPI-0190 or HPI-0197 PCBs from the V2M-P1 chassis/enclosure:

1. With the plastic top cover of the V2M-P1 removed, lean the rear panel away from the HPI-0197 PCB and slide the panel out.

2. Unplug the 4-way Molex connector which leads from the back panel to the ATX PicoPSU on the motherboard.

3. Attach the new back panel to the 4-way Molex connector.

4. Fit the new rear panel assembly into the lower plastic chassis tray – at an angle, bottom edge first.

5. Tilt the panel to the upright position, over the DVI and UART connectors

6. Connect the PCIe 12V power input socket on each LogicTile back to the spare Molex connector on the PicoPSU, using the jumper cables provided. The system will not boot if each LogicTile is not receiving its own 12V supply.

7. Route all of the 12V power wiring neatly around the enclosure, avoiding any possibility of shorts or damage to the wires.

The following photograph shows the assembled SMM-A15 system with the updated rear panel and 12V PCIe power wiring harness fitted. The 12V PCIe power wiring harness may differ, depending on which SMM-A15 variant you have.



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Figure 4-1 SMM-A15x2N system, assembled

Note that it is physically possible to use a full-size ATX power supply instead of the PicoPSU ATX module that is supplied with the V2M-P1. However, this is not advisable, since the Versatile Express system requires most of its power from the 12V rail, and relatively little current on the 3V3 and 5V rails. Conversely, ATX PSUs typically have large current capability on the 3V3 and 5V rails, but considerably less on the 12V. Unstable system operation is likely if an ATX PSU is used to power a Versatile Express system.

4.1.3 Making the JTAG connection

Regardless of which SMM-A15 variant is in use, the 2-way JTAG extender cable that connects the smaller back panel of the V2M-P1 motherboard to the daughterboard should always be fitted to the bottom LogicTile on Tile Site 2.

4.1.4 Installing DDR2 SODIMMs

Only the bottom LogicTile on Tile Site 2 needs to have a DDR2 SODIMM fitted, since the DMC is implemented in that board. The SODIMM should not be fitted to the top LogicTile on Tile Site 2, since this would interfere with the JTAG connector. Fitting a SODIMM to the LogicTile on Tile Site 1 has no effect.

4.2 Installing the SMM file bundle on a host PC

Install the SMM-A15 files to a PC running Microsoft Windows. This is usually delivered as a CD-ROM but it may also be possible to obtain the file set as a download from ARM.

4.3 Installing Boardfiles into the LogicTiles

Follow the .bit file installation instructions in the Release Notes document in the SMM-A15 file bundle. This file is in the root directory of the installation file bundle, and also forms part of the installation once installed on your PC:

…\sw\info\releasenotes.html



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5 SYSTEM OVERVIEW

5.1 General overview

The SMM-A15 is based on Cortex-A15 EAC r1p0.

The Versatile Express platform is the new generation FPGA development platform that offers higher bandwidth between the processor and the memory system.

The processor, memory controllers and the main system logic are implemented in FPGAs. The SMM and the motherboard are connected using the Static Memory Bus (SMB) interface. The majority of the slow speed peripherals (UARTs etc) are implemented on the motherboard via this interface.

Depending on which variant of the SMM-A15 is in use, there are many multiplexed connections between the LogicTile FPGAs.

5.2 SMM Features

In addition to the existing Cortex-A15 features, all variants of the SMM implement the following:

Internal bus matrix, synchronous to core clock

JTAG, Serial Wire and Trace support inside the FPGA and on the board

Asynchronous bridges to DDR memory and SMC interface

Up to 4GB of DDR2 using an appropriate DIMM. A 1GB DIMM is supplied as standard

SMC for driving standard peripherals on the V2M-P1 motherboard.

DMC for driving the on-board DIMM

Video/CLCD

DMA Controller

Configurations 2 and 3 of the SMM-A15 also contain:

Second „fast‟ internal bus matrix, asynchronous to core clock

16MB of on board ZBTRAM, synchronous to core

Internal HDCLCD controller

5.2.1 Processor Configurations

The following table lists the specification of the Cortex-A15 processor, as it appears in each variant of the SMM-A15:



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Processor feature Configuration 1 Configuration 2 Configuration 3

Number CPUs 1 1 2

L2 cache size 512K 512K 512K

L2 Tag RAM Slice 0 0 0

L2 Data RAM Slice 0 0 0

L2 logic gated clock Yes Yes Yes

ECC/Parity None None None

NEON No Yes Yes

VFP No Yes Yes

SPI number 224 224 224

Power-switch, clamp pins Yes Yes Yes

CCI No No No

Number of clusters 1 1 1

Table 5-1 Processor configurations

5.2.2 Debug features

Debug feature Configuration Note

ETM Present One for each processor

CoreSight DK Present Include CSTPIU, ITM, SWO, CSETB (64KB)

ROM table Two Primary ROM table for CSSYS

Secondary ROM table for processor system

Table 5-2 Debug features



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5.3 Detailed System Architecture

This section discusses the various features of the SMM-A15 design.

The following block diagrams show the internal components of each variant of the SMM-A15, prior to partitioning between the various FPGAs.

Cortex-A15

ATB

funnel

CSTPIU

SWJ-DP

CTM

CSSys

SWO

Cortex-A15 wrapper

AHB-AP

APB-AP

ROM

table

JTAG / SW

DBG APB

DAP

bus

Trace

Timestamp generator

NIC301 AXI bus matrix

SCC

Static Memory Bus

Timer Watchdog

Switches UART

LEDs KMI

SCI

MCI-SDRTC

SSPAACI

GPIO

CSSYS_M

(AHB32)

CSSYSAPB

(APB32)

Debug connectors

CORE0_M

(AXI64)

SCCAPB

(APB 32)

Cortex-A15 MP1

A15

ROM

table

CTI

PTMCTM

DRAM_S

(AXI64)

DMC

PL341

smm_a15_2xv6_toplevel

SMB_S

(AXI64)

SMC

PL354

SMBAPB

(APB32)

DMCAPB

(APB32)

DDR

2Clocks

V2

Base board

PL330

DMA

DMACAPB

(APB32)

DMA_S

(AXI64)

ACP

(AXI64)

Reset

&

clocks

Figure 5-1 System Level Design for Configuration 1 : SMM-A15x1



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ExtS

(AXI64)

smm_a15_Xxv6_toplevel

SCC

Static Memory Bus

760

Clock

&

Reset

Timer Watchdog

Switches UART

LEDs KMI

SCI

MCI-SDRTC

SSPAACI

GPIO

CSSYS_M

(AHB32)

CSSYSAPB

(APB32)

ZBTRA

M

interfac

e

CORE0_M

(AXI64)

SCCAPB

(APB 32)

ZBT_S

(AXI64)

Dummy

LINK_S

(AXI64)

ZBT

RAM

HDLCD


CLCDAPB

(APB32)

DRAM_S

(AXI64)

DMC

PL341

smm_550_toplevel

SMB_S

(AXI64)

SMC

PL354SCC

550

Clock

&

Reset

SMBAPB

(APB32)

CLCD_S

(AXI64)LINK_M

(AXI64)

DMCAPB

(APB32)

SCCAPB

(APB 32)

DDR

2

Clock

s

V2

Base board

PL330

DMA

DMACAPB

(APB32)

DMA_S

(AXI64)

ACP

(AXI64)

Cortex-A15

ATB

funnel

CSTPIU

SWJ-DP

CTM

CSSys

SWO

Cortex-A15 wrapper

AHB-AP

APB-AP

ROM

table

JTAG / SW

DBG APB

DAP

bus

Trace

Timestamp generator

Debug connectors

Cortex-A15 MP1/MP2

A15

ROM

table

CTI

PTMCTM

Figure 5-2 System Level Design for Configuration 2 : SMM-A15x1N and SMM-A15x2N

The design is based on the Cortex-A15 wrapper, CoreSight DK and the following system components:

5.3.1 Dynamic Memory Controller (DMC)

This is an asynchronous PL341 implementation with modified pad interface to register all I/O signals using IO pads registers.

5.3.2 System Configuration Controller (SCC)

The SCC provides a standard serial interface to a LogicTile Express 12MG (V2F-2XV6) Daughterboard Configuration Controller (DCC). The DCC uses this interface by issuing commands to receive/transmit information from/to the SCC registers in the FPGA.

The SCC registers provides configuration registers for system control. Please see 6.1.2 SCC Register block.

5.3.3 Static Memory Controller (SMC)

This is the Static Memory Controller used to communicate with the motherboard. The ARM PrimeCell PL354 is used in this design.



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5.3.4 Accelerator Coherency Port (ACP)

The processor ACP can be only accessed by the DMA controller.

The REMAP bits in the NIC301 matrix control the redirection of transfers from the DMAC to the ACP slave port. See section 6.1.1 DMA memory remap.

5.3.5 DMA Controller (DMAC)

The DMAC provides an AXI interface to perform DMA transfers and two APB interfaces that control its operation and setup. Only one APB interface which implements TrustZone® secure technology is connected, the other is unused.

5.3.6 ZBT RAM Controller

This is a bridge which converts 64 bit AXI transfers into ZBT SRAM transfers. It based on BP140 with extra AxiRegSlices on the data read side which increases performance. The ZBT SRAM operates synchronous to the AXI domain with no wait state and 2 cycles of latency.

The ZBTRAM memory can support a read only mode. This is controlled by a control bit in SCC_SYSCFG in the SCC register block. It is provided for testing hardware breakpoints.

Please note that this feature is not implemented in SMM-A15 configuration 1.

5.3.7 High-Definition LCD Controller (HDLCDC)

The HDLCD controller is used to drive a monitor that can support high resolutions. This is the same controller that is implemented in the test chip used on the CoreTile for Cortex-A5. Please refer to the A5 CoreTile TRM for programmers model information

Please note that this feature is not implemented in SMM-A15 configuration 1.



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5.4 Clock architecture

Regardless of which SMM-A15 variant is in use, the programmable clock generators on the lowest LogicTile on Tile Site 2 are used to generate all the required system clocks. These are configured by the DCC on that tile, from the text file e5x0rxpy.txt (where „x‟ and „y‟ are the revision numbers of the CPU core implemented in the SMM).

5.4.1 Clock Domains

The following clock domains are present in all of the SMM-A15 variants:

CLKIN

OSC3 is the source for CLKIN which is used to clock the CPU, CoreSight and slow subsystem components. To ensure reliable operation, this should not be changed from its default setting.

MCLK

OSC2 is a source for two DCM modules. The first DMC module generates MCLK, MCLKX2 and MCLK90 signals for the PL341 DMC controller. The second DCM is used to generate MCLK_OUT and this provides a clock to the DDR memory devices on the DIMM, which is in phase with MCLK.

SMCLK

SMCLK is used to drive the Static Memory Controller and Static Memory bus. SMCLK is generated using a fixed REFCLK24MHZ clock. The SMCLKIN feedback clock is used to register data from the Static memory bus slave implemented on the V2M-P1 motherboard.

TRACECLK

TRACECLK is directly connected to OSC4.

Configurations 2 and 3 of the SMM-A15 have additional clock domains:

ACLK

OSC0 is the source for an asynchronous fast clock which is used to clock the second bus matrix and associated peripherals.

CLCDCLK

CLCDCLK is directly connected to OSC1. It is the reference clock for the HDCLCD controller. The frequency of this clock must be adjusted to match the target screen resolution. Please refer to section 5.3.7 for further information.

5.4.2 Default, minimum and maximum operating frequencies



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Clock source Clock signal Clock domain Default Freq Min Freq Max Freq

OSC3 CLKIN CPU, CoreSight, ZBTRAM, slow subsystem

10MHz 10MHz 10MHz

OSC2 MCLK DDR 125MHz 110MHz 125MHz

REFCLK24 SMCLK/SMCLKIN Static Memory Bus 48MHz 48MHz 48MHz

OSC4 TRACECLK Trace 100MHz 2MHz 100MHz

OSC0 ACLK Fast subsystem 80MHz 2MHz 80MHz

OSC1 CLCDCLK CLCD 23.75MHz 2MHz 62.5MHz

Table 5-3 Default and maximum operating frequencies

6 PROGRAMMERS MODEL

6.1 Memory Map

The memory map as viewed from the processor is as follows:

Start Addr End Addr SMM-A15MP1 SMM-A15NMP1/2

Start End Peripheral Peripheral

0x0000_0000 0x03FF_FFFF SMC CS0 (alias) SMC CS0 (alias)

0x0400_0000 0x05FF_FFFF SMC CS6 SMC CS6


0x0800_0000 0x0BFF_FFFF SMC CS0 SMC CS0

0x0C00_0000 0x0FFF_FFFF SMC CS4 SMC CS4



0x1800_0000 0x1BFF_0000 SMC CS2 SMC CS2

0x1C00_0000 0x1FFF_FFFF SMC CS3 SMC CS3

0x2000_0000 0x2000_FFFF DAP ROM DAP ROM

0x2001_0000 0x2001_FFFF ETB ETB

0x2002_0000 0x2002_FFFF CTI CTI

0x2003_0000 0x2003_FFFF TPIU TPIU

0x2004_0000 0x2004_FFFF Funnel Funnel

0x2005_0000 0x2005_FFFF ITM ITM

0x2006_0000 0x2006_FFFF SWO SWO

0x2007_0000 0x21FF_FFFF Reserved Reserved

0x2200_0000 0x2200_0FFF CPU Integration ROM CPU Integration ROM

0x2200_1000 0x2200_FFFF Reserved Reserved

0x2201_0000 0x2201_0FFF CPU 0 CPU 0

0x2201_1000 0x2201_1FFF PMU 0 PMU 0

0x2201_2000 0x2201_2FFF Reserved CPU 1 (Optional)

0x2201_3000 0x2201_3FFF Reserved PMU 1 (Optional)

0x2201_4000 0x2201_4FFF Reserved Reserved



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0x2201_8000 0x2201_8FFF CTI CTI 0

0x2201_9000 0x2201_9FFF Reserved CTI 1 (Optional)

0x2201_A000 0x2201_BFFF Reserved Reserved

0x2201_C000 0x2201_CFFF PTM PTM 0

0x2201_D000 0x2201_DFFF Reserved PTM 1 (Optional)

0x2201_E000 0x29FF_FFFF Reserved Reserved

0x2A00_0000 0x2A0F_FFFF NIC301 GPV NIC301 GPV

0x2A10_0000 0x2A41_FFFF Reserved Reserved

0x2A42_0000 0x2A42_FFFF SCC (alias) SCC2 (760 device)

0x2A43_0000 0x2AFF_FFFF Reserved Reserved

0x2B00_0000 0x2B00_FFFF Reserved HDLCD

0x2B01_0000 0x2B09_FFFF Reserved Reserved

Start Addr End Addr SMM-A15MP1 SMM-A15NMP1/2

Start End Peripheral Peripheral

0x2B0A_0000 0x2B0A_FFFF DMC cfg DMC cfg

0x2B0B_0000 0x2BFF_FFFF Reserved Reserved

0x2C00_0000 0x2C00_FFFF CPU Periphbase Base CPU Periphbase Base

0x2C01_0000 0x2C01_FFFF GIC_D GIC_D

0x2C02_0000 0x2C03_FFFF GIC_C GIC_C

0x2C04_0000 0x2CFF_FFFF Reserved Reserved

0x2D00_0000 0x2D00_FFFF Reserved Reserved for peripherial in 550

0x2D01_0000 0x2DFF_FFFF Reserved Reserved for peripherial in 550

0x2E00_0000 0x2EFF_FFFF Reserved Internal SRAM

0x2F00_0000 0x2FFF_FFFF Reserved Reserved for peripherial in 550

0x3000_0000 0x3FFF_FFFF Reserved Reserved for peripherial in 550

0x4000_0000 0x5FFF_FFFF Reserved Reserved

0x6000_0000 0x7FF2_FFFF Reserved Reserved

0x7FF3_0000 0x7FF3_FFFF DMC sbcon DMC sbcon

0x7FF0_0000 0x7FFA_FFFF Reserved Reserved

0x7FFB_0000 0x7FFB_FFFF DMA PL330 DMA PL330

0x7FFC_0000 0x7FFC_FFFF Reserved Reserved

0x7FFD_0000 0x7FFD_FFFF PL354 cfg PL354 cfg

0x7FFE_0000 0x7FFE_FFFF Reserved Reserved

0x7FFF_0000 0x7FFF_FFFF SCC SCC1

0x8000_0000 0xFFFF_FFFF DRAM DRAM

Figure 6-1 Memory map



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6.1.1 DMA memory remap

The NIC301 Remap register at NIC301 base address + 0x0 allows configuring of accesses from the DMA master to the SMB and the DMC. This can be a direct access across the NIC301 or it can be routed via the processor ACP.

NIC301 Remap[1:0]

0x0000_0000-0x1FFF_FFFF

0x8000_0000-

0xFFFF_FFFF

0x80000_0000-

0xFFFFF_FFFF

2‟b00 SMC DMC DMC

2‟b01 SMC ACP ACP

2‟b10 ACP DMC DMC

2‟b11 ACP ACP ACP

Table 6-1 Remap options

6.1.2 SCC Register block

A number of registers are implemented for system control. The registers can be accessed by the APB bus as well as by the SCC interface. The SCC interface allows initialization of the SMM during the system power up sequence, in accordance with values that are stored in a daughterboard configuration file. See section 5.4 for details.

Offset Address Register Descriptions

0x000 Reserved Bits [31:5] Reserved

Bit[4:0] – Reserved.

0x004 Reserved Bit [31:0] Reserved.

0x008 SCC_CPU0CTRL Control bits for CPU0.

Bits [31:12] Reserved

Bit[11] Controls teinit

Bit[10] Controls vinithi

Bit[9] Controls cfgend

Bit[8] Controls cp15sdisable

Bit[7:1] Reserved

Bit[0] : Processor enable. If it is cleared, processor will be in reset state.

If this register is not setup by the board configuration file, these bits are reset as 0x1 (enabled), and cannot be changed unless LT_LOCK is written as 0xA05F.

0x00C SCC_CPU1CTRL Control bits for CPU1.

Bits [31:12] Reserved

Bit[11] Controls teinit

Bit[10] Controls vinithi

Bit[9] Controls cfgend



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Bit[8] Controls cp15sdisable

Bit[7:1] Reserved

Bit[0] : Processor enable. If it is cleared, processor will be in reset state.

If this register is not setup by the board configuration file, these bits are reset as 0x1 (enabled), and cannot be changed unless LT_LOCK is written as 0xA05F.




0x01C SCC_DMACTRL Bits [31:8] Reserved

Bits [7:0] : Set to 1 to mask write byte strobe signal from DMA controller. These bits are set 0x0 after reset.

If this register is not setup by board configuration file, it resets as 0x0, and cannot be changed unless LT_LOCK is written as 0xA05F.

0x020 SCC_ACPCTRL Bits [31:22]. Reserved

Bits [21:16] : Set up awuser signal on ACP bus to control write inner attributes, inner & outer shareability

Bits [15:6] Reserved.

Bits [5:0]. Set up aruser signal on ACP bus to control read inner attributes, inner & outer shareability

If this register is not setup by board configuration file, it resets as 0x0.

0x040 SCC_TUBE Text output register (for retargeting in simulation only).

0x100 SCC_DLL DLL lock register

Bits [31:24] DLL LOCK MASK[7:0] - These bits indicate if the DLL locked is masked.

Bits [23:16] DLL LOCK MASK[7:0] - These bits indicate if the DLLs are locked or unlocked.

Bits [15:1] : Reserved

Bit[0] This bit indicates if all enabled DLLs are locked:

0x104 SCC_LED Bits [31:8] Reserved

Bits [7:0] : These bits control the V2F LEDs

0x108 SCC_SW Bits [31:8] Reserved



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Bits [7:0] : These bits indicate state of the V2F user switches

0x120 SCC_LOCK Write: write 0xA05F to this register to unlock access to a number of APB register. Only lowest 16-bit is implemented.

Read : Return current value (bit [15:0])and Unlock status (bit [16]).

Reset value of this register is 0x00000000.

The write is only possible via APB bus.

0xFF8 SCC_AID SCC AID register is read only

Bits[31:24] FPGA build number

Bits[23:11] Reserved

Bit[10] if “1” SCC_SW register have been implemented

Bit[9] if “1” SCC_LED register have been implemented

Bit[8] if “1” DLL lock register have been implemented

Bits[7:0] number of SCC config register

0xFFC SCC_ID SCC ID register is read only

Bits[31:24] Implementer ID: 0x41 = ARM

Bits[23:20] IP Variant Number

Bits[19:16] IP Architecture: 0x5 =AXI

Bits[11:4] Primary part number: C0f = CortexA15

Bits[3:0] IP Revision number

Table 6-2 SCC Register block

6.2 Interrupt and Event signal assignments

The SMM-A15 implements a Cortex-A15 Generic Interrupt Controller (GIC) with 224 Shared Peripheral Interrupts (SPIs). SPIs start at ID32.

The SPIs are triggered by events generated on associated GIC interrupt input lines IRQS[223:0]. The table below shows SMM IRQS assignment and SPI map.

IRQS bit Interrupt ID Signal Description

42:0 74:32 IRQ[42:0]

43 external interrupts from a motherboard. For more information refer to Motherboard Express μATX V2M-P1 TRM.

63:43 95:75 Reserved

67:64 99:96 Reserved



Open Access

68 100 pmuirq[0] Cortex-A15 CPU 0 Performance Monitor

69 101 pmuirq[1] Cortex-A15 CPU 1 Performance Monitor

70 102 Reserved

71 103 Reserved

72 104 ctirq[0] Cortex-A15 CPU 0 Cross Trigger

73 105 ctirq[1] Cortex-A15 CPU 1 Cross Trigger

74 106 Reserved

75 107 Reserved

76 108 commtx[0] Cortex-A15 CPU 0 Comms Channel Transmit

77 109 commtx[1] Cortex-A15 CPU 1 Comms Channel Transmit

78 110 Reserved

79 111 Reserved

80 112 commrx[0] Cortex-A15 CPU 0 Comms Channel Receive

81 113 commrx[1] Cortex-A15 CPU 1 Comms Channel Receive

82 114 Reserved

83 115 Reserved

84 116 INTERRIRQ Cortex-A15 error indicator for L2 RAM double-bit ECC error and illegal writes to the GIC memory-map region

85 117 clcdintr Internal display interrupt

86 118 smc_int[0] Internal SMC memory interface 0 interrupt

87 119 smc_int[1] Internal SMC memory interface 1 interrupt

88 120 dma_irq[0] Internal DMA channel 0 interrupt

89 121 dma_irq[1] Internal DMA channel 1 interrupt

90 122 Reserved

91 123 Reserved

92 124 dma_irq_abort Internal DMA abort interrupt

223:93 255:125 Reserved

Documents

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