Software simulation of Virtual Memory using Demand Paging

Dharma Prakash Natarajan

Goals of the Project

• Construct the Virtual Memory Elements: Memory, Disk, Page Table,TLB.

• Generate the test program for matrix multiplication to create the address sequence. Row wise and column wise matrix multiplication reference strings are generated.

• Find out the TLB miss ratio

• Find out the Page fault ratio.

• Vary the associativity, TLB and memory size and study the effects on TLB miss ratio and Page fault ratio

• Study the effects of LRU, FIFO and Random replacement strategies on TLB miss ratio

High Level Picture

Program Basics

• Disk is created as an array each holding a page

• Memory is created as a vector of memory entries

• Page table is created as a vector of page table entries. Each page table entry contains valid bit, reference bit and

dirty bit

• TLB is created as vector of TLB sets

• Each TLB contains a vector of TLB entries. Each TLB entry contains valid, reference and dirty bits

•Main simulates the process execution

Test Program Matrix multiplication

Page 0Page 1

Page 19

Page 20Page 21

Page 39

Page 40Page 41

Page 59

20 x 20 matrix 20 x 20 matrix 20 x 20 matrix

Reference String for Row wise Matrix multiplication

0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29

Reference String for Column wise matrix multiplication

0 20 1 20 2 20 3 20 4 20 5 20 6 20 7 20 8 20 9 20

Results

Conclusion

• Mostly expected results on associativity, replacement strategy

•Test case not able to distinguish between FIFO and LRU

• Simulates only once process. Could be extended for multiple processes.

Context switch. Page table for each process

• Byte addressing could be used.

Can be used to simulate multiple levels of page tables.