Solstice-TDS™

The easy-to-use flow-based “Scenario” enables intuitive design to test conversion process that is also repeatable and self-documented. The Scenario can be saved as an ASCII command file to run in batch processes

Award Winning Software for Design to Test Pattern Conversion and Validation

•  Reduces test engineering time by generating test programs from electronic design automation (EDA) tool outputs, or from other ATE test programs

•  Increases engineering productivity by checking design and tester-specific rules upfront

•  Ensures pattern integrity with fast and easy-to-use instant pattern validation of test vectors pre- and post-conversion, which in most cases eliminates the need to re-simulate

•  When needed, the re-simulation capability is thorough and automated. Stimulus/response data are compact and streamed into a logic simulator to exercise the designer’s DUT model

•  Maximizes the return on your tester investment by optimizing use of tester resources and utilizing advanced tester features

D A T A S H E E T

Key Benefits

Source files of different formats (WGL, STIL, VCD, EVCD, other ATE formats) can be read, displayed, and edited in Solstice-TDS Waveform Editor. Hover the cursor over any area to reveal relevant information: scan bits, strobe points, pattern state, comments, labels, micro-codes, etc.

WaveMaker+ is the next-generation graphical user interface module in the Solstice-TDS software platform. Features include:

•  Scenario – A flow based canvas for users to construct their design-to-test flow. Scenarios are intuitive to build and require no documentation to understand and re-use

•  File Pane – Test files management is right at the users’ finger tip. No need to manually type, list, and move files

•  Waveform Editor – Working with test timing and pattern is easiest with their composition presented in waveform display. Timing and pattern can be edited directly in the waveform perspective. Search for edge, time, differences, errors, cycles, and a selected waveform signature

WaveMaker+

Databases and API Solstice-TDS’s strength is in its random-access databases where conversion processes don’t have to be repeated from scratch when fixing issues, but can be resumed at any check points.

•  SEF – Standard Event Format Database stores event-based data coming from logic simulation. E.g., VCD & EVCD.

•  WDB – WGL Database stores cycled-base test patterns coming from the standard WGL or from cyclized VCD/EVCD.

•  SDB – STIL Database. The next-generation WDB.

Solstice-TDS™

D A T A S H E E T

Testcycleinforma0on

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designandtest

Solstice Waveform Editor contains design and test data in one environment. All stimulus/response data can be changed by drag-n-drop of waveforms or via programmable API. Changes in data do not need to be re-compiled so users get immediate feedback on various experiments. ︎

Waveformsareeditableinplaceforimmediateresimula0on

The Power of Data Storage and Application Programming Interface (API) With its random-access SEF, WDB, and SDB databases, Solstice-TDS is able to provide important data analysis and efficient operations. Scan structures (cells, chains), comments in EDA files (STIL, WGL, VCD, EVCD), timeset names are all available for viewing and editing.

A rich set of API enables Solstice-TDS to work in concert with customer in-house tools and methodologies.

Data Conditioners Solstice-TDS has the most comprehensive library of conditioners for all test applications:

•  Interactively view simulation waveforms with zoom, pan, search, and measure capability in a simulator and tester independent format.

•  Create, compare, and analyze composite waveforms for conformance to design specifications.

•  Quickly check simulation waveforms for conformance to design specifications.

•  Perform dynamic timing verification or identify critical simulation timing, such as maximum delay, minimum setup/hold time, and maximum clock skew.

•  Identify abnormal design behavior, such as bus conflicts or race conditions.

•  Extract simulation stimulus and response from simulators, existing test programs, or data acquired with a logic analyzer for re-simulation or comparison.

•  Observe the effect of loading and tester skew on the design’s behavior.

•  Determine whether or not your design is testable early in the design process by ensuring that simulation stimulus can be reproduced and important circuit responses can be observed during the test.

•  Identify hazards which impact test yield. •  Determine the best strobe placement within test

cycles to maximize fault detection and increase test margin.

•  Add tolerance to waveforms for voltage, temperature, and process variations.

•  Guardband for rise/fall times, tester skew, and fixturing considerations.

•  Create or change patterns and signals attributes programmatically.

•  Add equations to static timing. •  Waveform-based cyclization.

Solstice-PV is a pattern validation module designed to read DFT or ATE test patterns into a TSSI database, then prepare them for editing, simulating and debugging. The database decouples the stimulus/response data from the testbench connectivity code and therefore, enables the size of the Verilog testbench to be independent from the size of the design. Hence, the compact testbench is consistently small and predictably fast to compile. 1.  Inputs: STIL, WGL, VCD, EVCD, IJTAG, SVF, and/or ATE patterns 2.  Generates a Verilog testbench to stream test patterns from the database to the DUT model and compare DUT responses 3.  Waveform editor can be used to interactively alter test patterns and re-simulate without the need to re-compile the testbench.

This capability enables rapid what-if analysis for debugging purposes

PLI

…Verilog

IPIP

IP

JTAG

WGLBIST

STIL

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Solstice-PV reads, converts, and integrates various patterns into an internal database. ︎

Solstice-PV In Converter

Stimulus/ Response

Data stream1

The Verilog testbench file is mainly for connectivity with the design netlist. Hence, it’s much smaller in size, and only neededed to be compiled once for simulations. ︎

2

︎Stimulus/Response data can be adjusted by waveform or

programmable API. Verilog PLI interface is used to stream new data to the logic simulator without the need for lengthy re-compilation. ︎

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TimeTable™ TimeTable is a Solstice-TDS module designed to cyclize event-driven simulation output (typically in VCD/EVCD format) by automatically discover timing and/or based on the exact timing specification provided by the user.

TimeTable is the first ever commercial vector translation tool to automate the comprehensive timing analysis and discovery to aid test engineers cyclizing their E/VCD files without cutting corners and losing important device transactions. Comprehensive time analysis is the key feature preventing patterns from failing on the tester, or worse yet, passing bad parts.

Solstice-TDS TimeTable auto-fills signal list from VCD/EVCD file, auto-detects test period, and auto-assigns device timing and format for the target tester. TimeTable is designed to assist verification engineers, product engineers, or test engineers in getting their ATE patterns generated correctly and rapidly.

Solstice-TDS™

D A T A S H E E T

Solstice-PV for Closed-Loop Pattern Validation

TSSI, Solstice-TDS, Solstice-PV, TimeTable, WGL, TesterBridge, WaveBridge, DVT, TVT, SEF, SDB, and WDB are trademarks of Test Systems Strategies, Inc. All other trademarks and registered trademarks are the property of their respective owners. © 1979-2016 Test Systems Strategies, Inc. All rights reserved. 06.20.

www.tessi.com Test Systems Strategies, Inc. 14789 SW Millikan Way, Beaverton, Oregon 97003 U.S.A. Phone: 503.626.8806 Fax: 503.626.8817 Email: sales@tessi.com

Solstice-TDS™

D A T A S H E E T TesterBridges and WaveBridges (“Bridges”)

Bridges are Solstice-TDS modules that generates test program files for a target test system. Common functionalities:

•  Quickly check waveforms for compatibility with the target test system. •  Automatically generate test programs which include timing, pin assignment, pattern data, and program templates in a

ready-to-compile format. •  Add test specifications to simulation waveforms. •  Determine the best strobe placement within test cycles to maximize fault detection and increase test margin. •  Add tolerance to waveforms for voltage, temperature, and process variations. •  Guardband for rise/fall times, tester skew, and fixturing considerations. •  Fully utilize tester resources including multiple time domains, multiple timesets, equations, pattern decoding, and scan. •  Automatically compress patterns using row repeats, loops, or subroutines or the combination, if available. •  Create quality test programs for at-speed testing, functional characterization, logic verification, and wafer probe. •  Create DC tables which identify simulation times and test vectors suitable for parametric testing. •  Create quality test programs from component simulations, Scan/ATPG and other DFT tools. •  Create a burst or combine waveforms from different sources enabling, for example, preamble waveforms to be executed

prior to ATPG patterns.

Tester-specific features can be configured in a targeted TesterBridge/WaveBridge such as:

•  Advantest V93000 Multi-Port, X-Modes, Modulo-x pattern compression •  National Instruments HWS format for LabVIEW •  Teradyne UltraFLEX Single, Duo, Quad mode

Supported Test Systems •  Advantest CTS, SZ, T65XX, T66XX, T2000, V93000 •  Chroma 33xx, 36xx •  Keysight •  LTX-Credence X-Series, Diamond, Quartet/Vista,

Sapphire, SC •  National Instruments STS Platform and PXI Instruments •  Teradyne J750, Flex & UltraFLEX •  Teradyne a5x, Catalyst, Tiger •  Teradyne Nextest Magnum, Maverick, Eagles •  All legacy testers

Solstice-TDS System Requirements

Hardware: RAM: 6GB+; Disk: 50GB+

Operating Systems: •  Linux 64-bit

-  Redhat/CentOS 6.x or later -  SUS 12.x or later

•  Windows 64-bit 7.x or later

Licensing: •  Floating or node-lock •  Flexera or RLM