Southern Taiwan University of Technology Department of Electrical Engineering A Failure-Detection Strategy for IGBT Based on Gate-Voltage Behavior Applied

Southern Taiwan University of Technology Department of Electrical Engineering

A Failure-Detection Strategy for IGBT Basedon Gate-Voltage Behavior Applied to a Motor

Drive System

Marco Antonio Rodríguez-Blanco, Member, IEEE, Abraham Claudio-Sánchez, Member, IEEE, Didier Theilliol, Luis Gerardo Vela-Valdés, Pedro Sibaja-Terán,

Leobardo Hernández-González, Member, IEEE, and Jesus Aguayo-Alquicira, Member, IEEEIEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL.58.NO.5,MAY 2011 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL.58.NO.5,MAY 2011

Teacher: Teacher: Ming-Shyan WangMing-Shyan Wang

Student: Min-Chen Jiang

MA020124MA020124

南台科技大學─電力電子研究室

Abstract

In this paper, a novel failure-detection technique and its analog circuit for insulated gate bipolar transistors (IGBTs), under open- and short-circuit failures, are proposed. This technique is applied to a three-phase induction-motor (IM) drive system. The detection technique is adapted to detect failures of short-circuit and open-circuit in the IGBT, which is based on gate-signal monitoring. The most important issue of this technique is the reduction of time for fault detection. This is very important in a failure-tolerant IM drive based on the material-redundancy approach or protection systems since the detection must be done before the device is damaged, in approximately less than 10 μs. The experimental test and simulations are presented in order to validate the proposed fault-detection technique, and it is validated, achieving replacement of the damaged element in the most suitable time.

112/04/20 2

南台科技大學─電力電子研究室112/04/20 3

Index Terms

Analog circuitsdriver circuits fault location insulated gate bipolar transistors (IGBTs) semiconductor-device measurements time delay

南台科技大學─電力電子研究室112/04/20 4

NOMENCLAT URE

AGD Gate–drain area.CGD Gate–drain capacitance.CGDJ Gate–drain depletion capacitance.COXD Gate–drain oxide capacitance.NB n-layer doping concentration.q Electron charge.RG Gate driver resistor.VGE Gate–emitter voltage.V ∗GE Gate–emitter voltage with attenuation.VT Threshold voltage.


Most inverter drives use IGBTs as the switching device for the

following reasons

1. The IGBT is available in high-voltage and high-current ratings

2. The IGBT’s ability to handle short- circuit current up to 10 μs plays a critical role for increasing the reliability of motor drive circuits

3. The easy control of gate-signal commutations


Fig. 1. Fault-tolerant schemes with dynamic material redundancy.


Fig. 1. The dynamic redundancy has found a special

application in the fault-tolerant electric systems due to its modular flexibility, as in the case of three-phase IM drive where the fault of power- electronic device can be tolerated without affecting the control algorithm.


Fig. 2. Fault-tolerant scheme for three-phase IM drive.


The detection and the location of the fault are the first and the most important events in a tolerant-system sequence, as shown in Fig. 3. After that, the tolerant mechanism is activated in order to guarantee process-operation continuity of the motor drive system used; the electrical isolation and the replacement of the damaged element are made possible by the activation of the isolation switches S(a,b,c) and connection switches S(a,b,c)(p,n)


Fig. 3. Fault-tolerant sequence for an IM drive system.


Fig. 4. IGBT equivalent circuit seen from the gate to emitter.


The analysis of this technique is derived from the equivalent circuit seen from the gate to source of the IGBT. The region from the gate to drain of the IGBT is modeled by CGD , which is the most vulnerable region to fail because there is a great mobil- ity of carrier in the channel during the IGBT turn-on transient. This region is formed by variable capacitance CGDJ , which models the depletion zone, and a fixed capacitance COXD , which models the oxide zone


Fig. 4 shows a simplified equivalent circuit that is seen from the gate to emitter obtained without taking into account the small modulation voltage of the base resistor and the small turn-on voltage of the diode of the internal bipolar junction transistor of the IGBT. Then, we assumed that the drain D and collector C terminals are equal. Therefore, the collector-to-emitter voltage VCE and the drain- to-source voltage VDS of the IGBT are considered equivalent


Equation (1) is taken from the IGBT physical model and describes the behavior of the depletion gate–drain region

GSDS

siBGDGDJ VV

NqAC

2

.. (1)


In the previous expression, the variation of some design and semiconductor-material parameters, such as the gate–drain area AGD and dielectric constant εsi , can cause a significant modulation of CGDJ into the depletion region. Variation of these parameters can appear in the IGBT with destructive effect

The modulation of CGDJ also affects the characteristic equation of CGD in (2), which is defined by the transient behavior of VDS and VGS during the IGBT turn on (VDS > VGS )


)(

./ GSDS

ifOXD

GSDSif

GDJOXD

GDJOXD

VVC

VVCC

CCGDC

(2)


dt

tdVC

dt

tdVC

dt

tdVCI GS

GDDS

GDGS

GSG

)()()(

The gate current IG is deduced from the equivalent circuit that it is seen from the gate to emitter of the IGBT in Fig. 1 and is given by

(3)


Fig. 5. Experimental gate charge.


In the previous expression, it can be noted that IG is directlyaffected by CGD , which causes a significant change underthe IGBT gate voltage. The changes of the IGBT gate are characterized by three phases due to capacitance variations, and it is shown in Fig. 5 for a specific experiment of a chopper circuit when a constant gate current IG is forced to circulate during the IGBT turn on to have a better definition of the aforementioned behavior phases.


The behavior during the turn on of the IGBT depends on theVGS and VDS voltage levels following different phases

Phase 1 (t1 < t < t2): At this point, VDS (t) is greater; then, the equivalent capacitance that it is seen from the gate to emitter of the IGBT only depends on CGS because at this point, CGDJ is smaller than COXD , and therefore, CGD is omitted to simplify the analysis.

Phase 2 (t2 < t < t3): This phase has the most complex behavior because at this point, a plateau zone in the gate signal is generated by the Miller effect causing the first and third terms of IG (t) in (3) to be neglected by simplicity; then, the gate current IG (t) is determined only by the negative slope of VDS , a magnitude of CGD when CGD = COXD + CGDJ .


Phase 3 (t3 < t < t4): During this phase and according to (2),the value of CGD can be considered equal to COXD because VDS (t) acquires a smaller value than VGS (t) during IGBT turn-on; then, the total equivalent capacitance that is seen from the gate to emitter is the electrical parallel of COXD and CGS .


Fig. 6. Simulation of gate-voltage signal varying AGD .


In Fig. 6, the fault zone is shown during IGBT turn on; the fault can be evaluated from VT (threshold voltage) to upper gate voltage, which can assure full evaluation of the depletion region (VDS < VGS ); taking into account most of the IGBTs, the VT parameter is approximately a quarter of the gate–emitter saturation voltage continuous VGES , which commonly is

±20 V, and the plateau zone of the gate voltage is almost constant when the gate voltage is 5 V. Then, the threshold levels can be defined from VT to VT +5 V in order to

assure the existence of a depletion region (Phase 2). Additionally, the Phase 2 behavior can also be used to avoid physical destruction of the IGBT and to activate quickly the tolerant mechanisms in fast dynamic systems, such as the IM drive.


Fig. 7. Experimental chopper circuit with resistive load.


Fig. 7 shows an experimental test obtained in the IGBT gate signal for fault-free case and faulty case by short circuit caused by overtemperature and limited to nominal current in order to avoid fault propaga- tion. The signal obtained for the faulty case during short-circuit failure can be generalized for whatever application since the CGDJ is reduced when AGD and/or εsi are decreasing, which normally occur when there are thermal stress in the IGBT


Fig. 8. Time diagram to determine the P 1 width and P 2 amplitude.


Fig. 9. Fault-detection scheme in the IGBT based on the measurement and evaluation in the turn-on transient period.


The P 1 pulsewidth is determined by a window detector, which is composed of a comparator circuit with hysteresis. This is capable of neglecting the turn-off phase, and thus, the limit of the detection window is established at the turn-on phase by means of two level comparators C 1 and C 2, which are tuned from the threshold voltage VT to VT +5 V in such a way that the width of P 1 may be proportional to the dynamics of the Phase 2 of gate signal VGE ∗of the IGBT. Note that VGE ∗is the

IGBT gate voltage but without the induced interference caused

by the emitter inductance Le .


Fig. 10. Decision criterion. (a) Threshold voltage level. (b)

Diagnostic matrix.


VGE = VG − K (VLe2 ) (4)

Where

VLe1 = (K − 1)VLe2 (5)

21

21

n)(1

)1(/ ee

if

eeif

LLnLLn

K

where n is the relationship Le2 /Le1 .


Fig. 12. Fault-detection circuit implemented in the IGBT gate driver of IM drive. (a) Fault-tolerant system. (b) Scheme implemented.


Fig. 13. Experimental test of detection circuit by different cases. (a) Failure by short circuit. (b) Failure-free. (c) Failure by open circuit.


Fig. 13 shows the experimental results based on the detection circuit proposed; the IGBT used is a discrete type IGBT (G4PH30K). The operating condition is set up by a collector current of IC = 10 A, and the test collector–emitter voltage VCE = 300 V. The failure-free and faulty conditions of the fault-detection circuit are emulated by reducing and extend- ing the gate-signal plateau. It is done by varying the gate resistance value RG significantly, e.g., the failure by short- circuit device is obtained by reducing RG = 0.1 Ω (RG1 ), the failure by open-circuit device is obtained by incrementing RG = 1 kΩ (RG2 ), and the failure-free condition is obtained by using RG = 100 Ω (RG3 ).


Fig. 14. Experimental results under short-circuit failure.


Fig. 14 shows the experimental results for current waveform applying the detection technique proposed for a failure by short circuit. The experimental conditions of the failure are as follows: Qcn fails by short circuit, the electrical isolation estimated is 5 ms after the fault detection, and replacement time of the damaged element is at the next zero crossing of the reference current of the motor.


CONCLUSION A fault-detection circuit based on the IGBT gate-

voltage behavior has been proposed, and in addition, this fault-detection circuit has been implemented in the gate drive focused on a motor drive. The delay time of the fault-detection circuit obtained is less than 3 μs; thus, this strategy is suitable for fault-tolerant motor drive since the nonlinearities of the inverter as death time, induced interference, and voltage peaks do not affect the fault-free operation of the fault-detection circuit in the inverter. A disadvantage of this strategy is that it is not generalized for every power device, although the proposed fault-detection circuit can also be applied with MOSFET because the current of the channel MOS in the gate voltage is similar. Another disadvantage is that the measurement of VLe2 that attenuates the induced interference adds an extra voltage sensor to the strategy proposed.


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Southern Taiwan University of Technology Department of Electrical Engineering A Failure-Detection Strategy for IGBT Based on Gate-Voltage Behavior Applied