SPAA TWO MARKS

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TWO MARKS NOVEMBER 2011

1. What are Special Purpose DSPs?

Hardware designed for execution of specific DSP algorithms (Digital

filters, FFT, etc.) or for specific applications (Telecommunication,

digital audio or control applications) are known as Special purpose

DSPs.

They are classified as follows:

Application specific DSPs

Algorithm-specific DSPs.

2. List out the differences between Harvard & Non-

Harvard architecture

HARVARD ARCHITECTURE NON-HARVARD/VON NEUMANNARCHITECTURE

Provides two separate memoryspaces for storing program anddata.

Provides single storage memoryfor storing program and data.

Pipelining is allowed in thistechnique.

Pipelining is not allowed in thisarchitecture.

Provides dedicated and fast MAChardware unit.

Does not provide MAC hardwareunit.

Used in DSPs and other processorsfound in latest embedded systemsand mobile communication

systems, audio, speech & imageprocessing systems.

Used in conventional processorsfound in PCs and servers, andembedded systems with only

control functions.

3. Give two examples of special instructions in DSP?

BANZ


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RPT

MAC

4. Compare fixed and floating point processors.

FIXED POINT PROCESSORS FLOATING POINTPROCESSORS

Fast operation Slow operationSmall dynamic range Increased dynamic rangeNo separate mantissa andexponent part

Mantissa and exponent part areseparated

Relatively economical Most expensive because of costlierhardware.

5. List our four Floating point processors.

TMS320C3X

TMS320C4X

TMS320C67XX

ADSP21XXX

6. What are the memories available on-chip in C50?

Program memory space (64 K word)

Local data memory space (64 K word)

I/O ports (64 K word)

Global Data Memory space (32 K word)

7. What are the different types of serial ports present in

C50?


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General purpose serial port

Time-division multiplexed (TDM) serial port

Buffered serial port (BSP).

8. What is auxillary register file and give its uses?

The auxillary register file contains eight memory-mapped

auxillary registers (AR0-AR7), which can be used for Indirect

addressing of the data memory or for temporary data storage.

The ARs are pointed to by a 3-bit auxillary register pointer (ARP)

that is loaded with a value from 0-7, designating AR0-AR7,

respectively.

9. Explain delayed conditional branch instruction.

To avoid flushing of pipeline and causing extra cycles, delayed

conditional branch instructions are provided by C5X.

Example:

BCNDD new_adrs, EQ

OPL #030h, PMST

In the above example, BCND instruction is a delayed branched

instruction wherein, the instruction following BCND is 2 words, and

hence only that 2-word instruction is executed before the branch is

taken, i.e., the two dead cycles following the BCNDD are filled with theOPL instruction. This means that the instructions get executed in 4-

cycles.


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10.What are the internal & external interrupts available

in C50?

INTERNAL INTERRUPTS:

Timer interrupt (TINT)

Serial port interrupts (XINT, RINT, TRNT, TXNT, BRNT and BXNT)

Host port interface (HINT)

EXTERNAL INTERRUPTS:

INT1 to INT16 (16 user-maskable interrupts).

In C5x, external interrupts are generated by external hardware

using INT1 to INT4.

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