space station - ntrs.nasa.gov

CONTRACT NAS9-9953 MSC 02471DRL NO: MSC-T-575, LINE IT"~M 72

SD 72-SA-114-1

SD 72-SA-01 14-1

MODULAR

space stationPHASE B EXTENSION

INFORMATION MANAGEMENT ADVANCEDDEVELOPMENT FINAL REPORT

Volume I: Summary

PREPARED BY PROGRAM ENGINEERINGJULY 31, 1972

(NASA-CR-128554) INFORMATION MANAGEMENTADVANCED DEVELOPMENT. VOLUME 1: SUMMARYInformation Management Advanced DevelopmentC.R. Gerber, et al (North American RockwellCorp.) 31 Jul. 1972 110 p CSCL 22B G3/31

Reproduced by

NATIONAL TECHNICALINFORMATION SERVICE

U S Deportment of CommerceSpringfield VA 22151 I Space Division

North American Rockwell

1 2 2 1 4 Lakewood Boulevard, Downey. C a I , f o r n i a 90241

/W I -9a8

CONTRACT NAS9-9953 MSC 02471DRL NO: MSC-T-575, LINE ITEM 72

SD 72-SA-0114-1

MODULAR

space stationPHASE B EXTENSION

INFORMATION MANAGEMENT ADVANCED DEVELOPMENT FINAL REPORT

Volume I: Summary

31 JULY 1972PREPARED BY PROGRAM ENGINEERING

Approved by

Ih

-~) iL/(/ James Madewell

DirectorSpace Applications Programs

Space DivisionNorth American Rockwell

1 2 2 1 4 L a k e w o Od B o u I e v a r d , D o w n e y , C a I i f o r n i a 9 0 2 4 1

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TECHNICAL REPORT INDEX/ABSTRACT

....... . IIr I I

I I I I DOCUMENT SECURITY CLASSIFICATIONITCCE LOF NUDBERNT

TITLE OF DOCUMENT LIBRARY USE ONLY

INFORMATION MANAGEMENT ADVANCED DEVELOPMENT FINAL REPORT,Volume I, Summary

AU THOR[S)

Gerber, C. R.,et.al.CODE

ORIGINATING AGENCY AND OTHER SOURCES DOCUMENT NUMBER

QN085282 Space Division of North American SD 72-SA-0114-1Rockwell Corporation, Downey, California

PUBLI CATION DATE CONTRACT NUMBER

July 31. 1972 NAS9-9953

FORM M 131-V REV. 1-68

DESCRIPTIVE TERMS

*MODULAR SPACE STATION, *INFORMATION MANAGEMENT,*ADVANCED DEVELOPMENT, *COMMUNICATIONS, *DATA PROCESSING,*SOFTWARE, *DATA BUS, *DATA STORAGE, *BREADBOARDS,*TECHNOLOGY, *SPECIFICATIONS

ABSTRACT

THIS DOCUMENT IS VOLUME I OF THE FINAL REPORT OF THE MODULAR SPACESTATION ADVANCED DEVELOPMENT STUDY. IT SUMMARIZES THE RESULTS OFAN 18-MONTH STUDY, HARDWARE DESIGN AND TEST PROGRAM WHICHINVESTIGATED AREAS OF INFORMATION MANAGEMENT TECHNOLOGY REQUIRINGADVANCED DEVELOPMENT.. THE TASKS INCLUDED THE CONSTRUCTION OFBREADBOARD MODELS OF THE 10 MEGABIT PER SECOND DATA BUS AND THEK-BAND COMMUNICATIONS TERMINAL ANTENNA-MOUNTED ELECTRONICS. THEREMAINING TASKS WERE STUDIES TO FURTHER DEFINE THE DATA PROCESSINGAND SOFTWARE ASSEMBLIES RESULTING IN PERFORMANCE SPECIFICATIONS ANDDEVELOPMENT PLANS/SCHEDULES FOR ADDITIONAL BREADBOARD OR PROTOTYPEEQUIPMENTS.

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Space Division0 A North American Rockwell

FOREWORD

This document is one of a series required by Contract NAS9-9953,Exhibit C, Statement of Work, for the Phase B Extension - Modular SpaceStation Program Definition. It has been prepared by the Space Division,North American Rockwell Corporation, and is submitted to the National Aero-nautics and Space Administration's Manned Spacecraft Center, Houston,Texas, in accordance with the requirements of the Data Requirements List,(DRL) MSC-T-575, Line Item 72.

This document is Volume I of the Modular Space Station InformationManagement System Advanced Development Technology Report, which has beenprepared in the following five volumes:

I IMS ADT Summary

II IMS ADT Communications TerminalBreadboard

III IMS ADT Digital Data Bus Breadboard

IV IMS ADT Data Processing Assembly

V IMS ADT Software Assembly

SD72- SA- 0114- 1

SD72- SA- O114- 2

SD72- SA- 0114- 3

SD72- SA- 0114- 4

SD72- SA- 0 1 4- 5

- iii-SD 72-SA-0114-1

PRECEDING PAGE BLANK NOT FILMED

Space Division9ft North American Rockwell

ACKNOWLEDGEMENTS

The following persons have participated in the conduct of the IMSADT tasks, and have contributed to this report:

C. W. Roberts Experiment/Electronics ManagerC. R. Gerber Information Systems Project EngineerB. A. Logan, Jr. Information SystemsE. Mehrbach Information SystemsD. W. Brewer Information SystemsV. R. Hodgson Information Systems

The-following subcontractors have supported the IMS ADT tasks inspecialized areas:

International Tel. & Tel.Nutley, New Jersey

B. Cooper, Proj. Mgr.

CommunicationsData Bus BB

Terminal B.B.

IntermetricsCambridge, Mass.

J. Miller, Prog. Mgr.

System Develop. Corp.Santa Monica, Calif.

R. Bilek, Prog. Mgr.

Gen'l Electric Corp.Valley Forge, Pa.

R. Kirby, Prog. Mgr.

NR-AutoneticsAnaheim, Calif.

J. Jurison, Proj. Mgr.

Data Processing Assy

Data Processing AssySoftware Assy

Bulk Storage Technology

Data Bus BBData Processing Assy

Preceding page blank I

SD 72-SA-0114-1


Space Division0 North American Rockwell

CONTENTS

INTRODUCTION1.1 OVERVIEW

COMMUNICATIONS TERMINAL BREADBOARD.2.1 SUMMARY .2.2 CTB GENERAL DESCRIPTION.2.3 TECHNOLOGY GOALS2.4 HISTORY .

DIGITAL DATA BUS BREADBOARD3.1 DACS REOUIREMENTS SUMMARY3.2 DACS BREADBOARD DESIGN

DATA4.14.24.3

PROCESSING ASSEMBLY DEFINITIONSUMMARY . .DPA DEFINITION .DPA ENGINEERING MODEL DEVELOPMENT PLAN

COMPUTER PROGRAM (SOFTWARE) ASSEMBLY DEFINITION5.1 SUMMARY . . . .

5.2 MSS SOFTWARE STANDARDS AND CONVENTIONS5.3 COMPUTER PROGRAM SPECIFICATION TREE.5.4 COMPUTER PROGRAM DEVELOPMENT PLAN5.5 COMPUTER-ASSISTED RESOURCE ALLOCATION AND

UTILIZATION . . .

DPA SUPERVISOR PROGRAM. . .

6.1 MSS OPERATIONS CONTROL CENTER PROCESSORSUPERVISOR COMPUTER PROGRAM SPECIFICATION(PRELIMINARY) . .

RECOMMENDATIONS FOR UTILIZATION OF ADTACCOMPLISHMENTS . . .

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- vii -

SD 72-SA-0114-1

Page

1-11-3

2-12-12-22-32-10

Section

1.0

2.0

3.0

4.0

5.0

6.0

7.0

3-13-13-5

4-14-14-84-19

5-15-15-25-35-13

5-13

6-1

6-1

7-1

9u North Amencan Rockwell


ILLUSTRATIONS

Figure Page

1-1 MSS Functional Allocations . . . . . 1-21-2 MSS Information Subsystem . . . . . 1-41-3 Advanced Development Technology Plan . . . . 1-51-4 Modular Space Station/Advanced Development

Interactions . 1-61-5 Subcontractor Organization . . 1-81-6 Advanced Development Work Package/TDL System . . 1-9

2-1 External Communication Link Requirements . 2-42-2 Communications Terminal Breadboard Block Diagram . . 2-62-3 CTB Hardware Identification . . . 2-72-4 Communications Terminal Breadboard System (CTB) . 2-82-5 CTB Antenna Mounted Electronics Subassembly Package -

Oblique View, Mounting-and Interconnect Face 2-9

3-1 DACS Work Breakdown and Flow . 3-23-2 Recommended DACS Configuration . 3-43-3 DACS Breadboard Configuration . . 3-10

4-1 Data Processing Assembly (DPA) . . 4-24-2 DPA General Diagram. . . . . . 4-34-3 Data Processing Assembly Distribution . 4-44-4 Data Processing Assembly Configuration Study . 4-64-5 Processor Utilization . 4-94-6 Basic Recommended Redundancy Configuration . . 4-104-7 Simplex Multiprocessor Schematic . . 4-124-8 Memory Hierarchy . . . . 4-134-9 Internal Bus Configuration . . 4-144-10 Detailed CP Subsystem Functional Allocations . 4-184-11 ADT Breadboards Related to ADT Plan . 4-234-12 Relationship of EEM Processor Development to ADT

Extension . 4-254-13 Procurement Options for a Dual Multiprocessor 4-29

5-1 Hierarchy of Plans and Specification . 5-105-2 MSS Software Specification Tree . . . 5-115-3 MSS Subsystems Operations . . . . 5-135-4 MSS Software Assembly Categorization . . . 5-165-5 Software Assembly Techniques . · . 5-175-6 MSS Supervisory Program Structure . . 5-18

Preceding page blank- ix -

SD 72-SA-0114-1


Figure Page

5-7 MSS Software System Authority and Coordination . 5-195-8 Multi-Model Development Flow .-5-205-9 MSS Development Schedule . 5-215-10 MSS Software Development Schedule . 5-22

6-1 General Supervisory Functions . 6-4

7-1 Advanced Development Task Extension(First Level Flow) . . 7-4

x 72-SA-0114-1

SD 72-SA-0114-1


TABLES

Table Page

2-1 External Communication Data Characteristics. . 2-54-1 Computation Requirements for Station Operations . 4-74-2 Redundancy Recommendations · . 4-114-3 Summary of Memory Hierarchy . . 4-154-4 Internal Bus Major Conclusions . . 4-164-5 Fault Tolerance Recommendations. . . 4-174-6 Technical Characteristics of the Central Processor 4-204-7 Technical Characteristics of the Preprocessor 4-215-1 Baseline Standards and Conventions . . . 5-47-1 Current ADT Accomplishments · . 7-17-2 Utilization of Results . . 7-2

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SD 72-SA-0114-1

Space DivisionNorthAmerican Rockwell

PRECEDING PAGE BLANK NOT FIL Ae

ABBREVIATIONS

Advanced Data SystemAdvanced Development TechnologyAdvanced Development Technology ExtensionAutomatic Frequency ControlAutomatic Gain ControlAutonetics (Division of North AmericanRockwell Corporation)

Bandpass FilterBits Per Second

Computer-Assisted Interactive ResourceSchedulingInternational Radio Consultative CommitteeCritical Design ReviewContract End ItemComputer Language for Aeronautics andSpace ProgrammingCommand Module (Apollo)Common Pool (of Data)Central Processor or Circular PolarizationComputer ProgramComputer Program Contract End ItemComputer Program Configuration ItemComputer Program Development FacilityComputer Program Integration Contractor(Agency)Computer Programming Test and EvaluationChange ReportCathode-Ray Tube (Display)Crew SubsystemCommunications Terminal BreadboardCentral Test Facility

DACSdBDBCUdBmdBWDCRDDBDemuxDMSDPADPSKDRSS

Preceding page

Data Acquisition and Control SubassemblyDecibelData Bus Control UnitDecibel Referred to One Milli-WattDecibel Referred to One WattDesign Change RequestDigital Data BusDe-Multiplex(er)Data Management SystemData Processing AssemblyDual Phase Shift KeyingData Relay Satellite System

blank - xSD 72-SA-0114-1

ADSADTADTXAFCAGCAN

BPFbps

CAIRS

CCIRCDRCEICLASP

CMCOMPOOLCPC.P.CPCEICPCICPDFCPIC (A)

CPT&ECRCRTCSSCTBCTF

Space Division9 % North American Rockwell

ECPEDFEEMEEMPEIRPEMCEMIEOSEOSSEPSETC/LSS or ECLSS

EVAEXTEb/No

FACSFDMFMFQT

G&CSGFEGHzGOA

HALHOLHOLMHz

IFIFRUIMIMSIMSIMIOCIOCBIOUI/OIPAIQLIRISS or IMS/SITT

K-wordsK-EAPS

K-bpsKHz

Engineering Change ProposalExperiment Data FacilityEngineering Evaluation ModelEngineering Evaluation Model ProcessorEffective Isotropic Radiated PowerElectromagnetic CompatabilityElectromagnetic InterferenceEarth Orbital ShuttleEarth Orbital Space StationElectrical Power SubsystemEnvironment Control and Life SupportSubsystemExtra-Vehicular ActivityExternalEnergy Per Bit to Noise Density Ratio

FacsimileFrequency-Division MultiplexFrequency ModulationFormal Qualification Test

Guidance and Control SubsystemGovernment Furnished EquipmentGiga-HertzGated Operational Amplifier

Higher-Order Aerospace Programming LanguageHigher-Order LanguageHigher-Order Language MachineHertz

Intermediate FrequencyIn-Flight Replaceable UnitIntermodulation ProductsInformation Management SystemInformation Management SimulationInitial Operational CapabilityInput-Output Control BlockInput-Output UnitInput-OutputIntermediate Power AmplifierInteractive Query LanguageInfra-RedInformation (Management) SubsystemInternational Telephone and Telegraph

Thousands of (Computer) WordsThousands of Equivalent-Add OperationsPer SecondThousands of Bits Per SecondKilohertz

- xiv -

SD 72-SA-0114-1

Gu 14North American Rockwell

LEM Lunar Excursion ModuleLM Lunar ModuleLNA Low Noise AmplifierLO Local OscillatorLPF Low Pass Filter

M1, M2 (Computer) Memory DesignationMbps Megabits Per SecondMCB Module Control BlockMHz MegahertzMOF Mission Operations FacilityMOL Manned Orbiting LaboratoryMSC Manned Spacecraft lenterMSFN Manned Space Flight NetworkMSS Modular Space StationMUX MultiplexermW Milli-WattsMW MicrowavemV Milli-Volts

NF Noise Figure

OBCO On-Board CheckoutOCC Operations Control Center (On-Board)ODM Operational Data ManagementOM Operating Memory

PA Power AmplifierPCM Pulse Code ModulationPDR Preliminary Design ReviewPL/1 Procedure LanguagePM Phase ModulationPN (PRN). Pseudo Random Noiseppm Parts Per MillionPQT Preliminary Qualification TestsPSK Phase Shift Keying

RAM Research and Applications ModuleRACU Remote Acquisition and Control UnitRCS Reaction Control SubsystemRF Radio FrequencyRHCP- Right-Hand Circular PolarizationRPU Remote Processing UnitRx Receive

S&C Standards and ConventionsSCCB Software Configuration Control BoardSCN Specification Change NoticeSD Space Division (of North American Rockwell

Corporation)SDC Systems Development Corporation

- xV -

SD 72-SA-0114-1

9 North American Rockwell

S/N Signal to Noise RatioSOW Statement of WorkSPL Space Programming LanguageSRD Step-Recovery DiodeSSCB Solid-State Circuit-BreakerSSS Structures SubsystemSTE Support Test Equipment

TAV Test and Validation (Programs)TBD To Be DeterminedTCXO Temperature-Controlled Crystal OscillatorTDA Tunnel Diode AmplifierTDM Time Division MultiplexingTDRS Tracking and Data Relay SatelliteTIP' Test and Integration PlanTLM, TM TelemetryTOOL Test Operations Oriented LanguageTRW Thompson Ramo Woolridge CorporationTT&C Telemetry, Tracking and ControlTWT Traveling Wave TubeTWTA Traveling Wave Tube AmplifierTx Transmit

USB (E) Unified S-Band (Equipment)UV Ultra-Violet

VDD Version Description DocumentVHF Very High FrequencyVSB Vestigal Side BandVSWR Voltage Standing Wave Ratio

- xyi -

SD 72-SA-0114-1


LIST OF INTERIM REPORTS

AA-101 DPA Flow Diagrams, September 1971

AA-102 DPA Throughput and Authority Analysis,February 1972

AA-103 DPA Configuration Selection, April 1972

AS-lOl Modular Space Station Computer ProgramStandards and Conventions, December 1971

AS-102 Modular Space Station Computer ProgramSpecification Tree, February 1972

AS-103 Modular Space Station Computer ProgramDevelopment, Test and ConfigurationControl Plan, May 1972

AS-104 Modular Space Station Computer-AssistedResource Allocations and UtilizationRecommendations, June 1972

CTB-101 Concepts for Multiple RF LinkMechanization, May 1971

CTB-103 Antenna-Mounted Electronics ComponentDesign, October 1971

CTB-105/106 CTB Integration and Test and OperationsManual, June 1972

DB-101 Parametric Data for Bus Design, May 1971

DB-103 Component Performance Requirements,Schematics and Layout Drawings,December 1971

DB-104 Digital Data Bus Breadboard Final Report,May 1972

DD-102 Modular Space Station Data Processing-Assembly Parametric Evaluation ofSubsystems Input/Output Interface,June 1971

- xvii -

SD 72-SA-0114-1

Space Division' North American Rockwell

DD-103

DP-101

DP-102

DP-103

DP-104

DP-105

DP-106

DP-107

DP-108

DP-109

DP-110

EL-277

IB-101

ICD #TRW 20549

ICD #AN 26465

MD-101 .

RF-101

Modular Space Station Data Acquisitionand Control Subassembly Model Configuration(SD 71-233), July 1971

Data Processing Assembly Configuration(Preliminary), June 1971

Data Processing Assembly SupervisorSpecification, May 1972

DPA Processor Final Description, May 1972

EEM DMS Processor Development Plan, June 1972

Data Acquisition and Control RedundancyConcepts, August 1971

Application of Redundancy Concepts toDPA, January 1971

Data Acquisition and Control SubassemblyBreadboard Design Requirements, October 1971

Data Bus Control Unit PerformanceRequirements, January 1972

Data Bus Control Design Reports, March 1971

DBCU Acceptance Report (to be published)

Bulk Storage Development Plan

DPA Internal Flow and Traffic Pattern,May 28, 1971

Interface Control Document - Data BusModem/RACU, Revision A, January 17, 1972

Interface Control Document - Data BusController Unit to Buffer I/O, RevisionJanuary 21, 1972

Mass Memory Parametric Data

Modular Space Station CommunicationsTerminal Breadboard Preliminary SystemSpecification, October 1971

- xviii -

SD 72-SA-0114-1

Space Division0 4 North American Rockwell

Central Processor Operational Analysis,September 30, 1971

Central Processor Memory Organization andInternal Bus Design, December 30, 1971

Automatic Control and Onboard CheckoutFinal Study Report

- xix -

SD 72-SA-0114-1

SA-101

SA-102

SD 71-227

Space Division9% North American Rockwell

1.0 INTRODUCTION

The NASA Modular Space Station Preliminary Definition Study (NAS9-9953)included a special emphasis task to develop selected breadboards and assemblyspecifications to evaluate and further define the advanced concepts incorpor-ated in the Modular Space Station Program (MSS) information subsystem (ISS).The Space Station Program requirements for near-continuous MSS-to-groundcommunications, for extended automation of spacecraft subsystem functions, andfor expanded autonomy to plan, schedule, and conduct a wide spectrum of exper-iment operations resulted in an ISS concept that included a K-band data relaysatellite communications link, a sophisticated on-board data management system,and an interactive man-machine decision-aid capability. Among other items,the ISS required a 10-megabit-per-second, time-shared data bus system; a dualmultiprocessor central computation facility with a complex software assemblyand a 25-watt K-band power amplifier.

Since much of the success of the Space Station Program relied upon thecapability of the on-board ISS, and since several of these concepts wereuntried or unproven at that time, the Information Management System (IMS)Advanced Development Technology (ADT) task was funded as a 17-month integratedeffort to develop or further define actual equipment breadboards that couldbe tested and evaluated by NASA (ISC), starting in July 1972. The ADT taskwas to run concurrently with, support, and track the MSS Preliminary DefinitionStudy; due to lead-time factors, the ADT task was extended in time beyond theMSS study itself so that refinements could be incorporated into the demonstra-tion breadboard equipments to more closely represent MSS requirements.

The influence of the MSS configuration can be seen by examining Figure

1-1. A central core module provides multiple docking ports to accept other

special-purpose modules. The core contains the guidance and attitude stabil-

ization/control and the fuel cell power equipments and is divided into two

isolatable pressure volumes separated by an airlock. At one end is the solar

array power module, which also contains repressurization stores. The four

standard modules are internally configured to provide the functions and work-ing/sleeping areas as labeled. An additional cargo module and one or more

research application modules (RAM),specialized for selected experiment disci-plines, can be docked to any of the five other ports.

There are several aspects that impact the ISS. First, except for the

power module, the basic configuration is that of two half-space stations,either one of which can maintain full operational capability even with one

pressure volume uninhabitable or unusable for some reason. It follows thatthe crew's command/control capability (represented by the control center areas

in SM-1 and SM-4) must also be dual and capable of operating independently in

case of failure or cooperatively under normal conditions. The control centerincludes the central computer, the operations console, the baseband RF commun-

ications, and the internal telephone/television distribution control.

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Second, the MSS is assembled in orbit by successive launches via theorbiter, a procedure that requires many days. The impact is that the ISS must(1) be operable as soon as SM-1 is joined to the core/power modules to auto-matically control the unmanned station to this point, (2) be extended to eachnew module as it is docked without modification other than connecting the databus, and (3) check out and verify the equipment functions of each module afterorbital assembly. This guideline of having one spacecraft subsystem verify,certify, and control all other subsystems is indeed unique, and it imposes afailure-tolerance requirement on the ISS that is one level greater than forthe other equipments.

Third, communication with the data relay satellite could not requirespecial attitude maneuvers or constraints to the station flight mode. Thiscommunication was implemented by installing two antenna packages on the out-board end of SM-1 and SM-4; the design concept was that the K-band poweramplifier and K-band receiver were to be mounted external to the pressurevolume (to reduce RF power losses due to cables, connectors, etc.), and thatthis unit would not have active thermal control. This concept, also unique,was to be demonstrated.

Figure 1-2 shows some of the more important design features of the MSS/information subsystem. Dual control centers, each having a central processor(which is, itself, dual redundant), are both linked by a quad redundant databus that provides a dual redundant connection to every piece of active equip-ment. Communications incorporate redundant K-band (1 duplex channel), S-band(3 duplex channels), and VHF (1 duplex channel).

1.1 OVERVIEW

The IMS ADT task was conceived to be one step of a long-range plan(Figure 1-3) to culminate in the delivery of a data management system (DMS)prototype, including the computer (multiprocessor), operations console,executive software, and automatic communications capabilities. This prototypeDMS would be used by NASA-MSC for conducting system integration/evaluationtests (including other spacecraft subsystems) and for developing the proced-ures, programs, and data base needed to automate, detect, and isolate failures,to conduct maintenance and repair simulations on all spacecraft subsystems,and to develop man-machine interactive operations and procedures. The dashedline at the left indicates the scope of the IMS ADT task in contributing tothis long-range plan.

The IMS ADT task was divided into seven subtasks (Figure 1-4) to estab-lish contract responsibilities. Their time-phased relationship to the ModularSpace Station Definition (4.1.2), Command/Control (4.1.4) and Design (4.1.6)tasks is indicated by the arrows. The ADT subtasks (4.2.1 through 4.2.7)included operating breadboard models of the 10-megabit-per-second data bus andthe K-band communications terminal antenna-mounted electronics. The remainingfive subtasks were studies to further define the data processing and softwareassemblies to result in performance specifications and development plans/sched-ules for additional breadboard or prototype equipments. The dashed-line titlesrepresent some of the expected future ADT subtasks that are considered time-critical to the Space Station Program.

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The contractor (NR-SD) elected to subcontract major portions of the ADTtask to encourage industry participation and maximize the benefit of consid-ering a variety of viewpoints from specialists. The contractual subtasks(4.2.1 through 4.2.7) were further divided into many small jobs, which werecompared to potential subcontractor or NR capabilities and then assembledinto work packages for negotiation and administrative control. NR-SDretained the role of systems engineering and technical management, andretained some technical jobs that could best be accomplished with the cooper-ation of the MSS Information Systems staff and other MSS subsystem designstaff. The remainder of the jobs were allocated to subcontractors as shownin Figure 1-5. The contracting agency selected TRW to supply the GFE equip-ment.

It was realized at the onset that the initially negotiated subcontractorwork packages (Statement of Work) would have unforeseeable impacts as the ADTand MSS design studies proceeded. To accommodate these impacts, NR used aflexible management approach, as shown in Figure 1-6. The initial work pack-ages, interim results of progressing studies, and modifications to the MSSGuidelines and Constraints were reviewed periodically by the NASA IMS WorkingGroup, in regular subcontractor technical interchange meetings and in sched-uled breadboard concept and design reviews. These meetings, attended by allinvolved subcontractors and by cognizant NASA-MSC personnel, provided a forumto critique the on-going efforts. Action items were made part of the minutesof these meetings, which in turn were reassessed and developed as technicaldirective letters to modify or clarify the individual dual subcontractors'statement of work without any cost impact. The success of this approach wasdue to the very cooperative participation of both subcontractor and NSCpersonnel.

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2.0 COMMUNICATIONS TERMINAL BREADBOARD

This section summarizes the results of an 18-month study and hardwaredesign and test whose final objective was to demonstrate a technique forintegrating the modular space station (MSS) external communications equipmentwith a high gain parabolic antenna and to demonstrate its capability toperform the MSS communications operations. This program includes preliminaryanalysis to define the design of an MSS concept that would be compatible withother program elements such as the earth orbital shuttle (EOS) and the trackingand data relay satellite (TDRS). Details of this analysis, the design conceptof an overall communications terminal breadboard (CTB), and the design detailsand test results of the delivered external RF package are included in VolumeII of the final report.

2.1 SUMMARY

The MSS total communications terminal includes a complex of equipmentoperating in three frequency bands - VHF, S, and K. Each band is used toprovide specific communications links with a multiplicity of externalterminals and a complex of baseband signals. These links and their signaltransfer requirements are defined in Table 2-1 and Figure 2-1.

Operation of the communications system to provide the capability formultiple link frequency performance is proposed by a design that incorporatesRF and baseband switching. This design is based on the MSS Phase B conceptto mount the K and S-band RF power amplifiers and RF receiver preamplifiersas close to their antennas as possible. In the case of the K-band system,this involves the location of these equipments on the external, steerable,parabolic antenna. By providing up and down conversion to the K-band trans-mitter and receiver from S-band, low-level RF signals can be routed fromthe internal S-band equipment over coaxial cables to the antenna mountedequipment. In a similar manner, the S-band system using S-band poweramplifiers and receiver front ends mounted close to the semi-directiveantennas can be fed at low levels via coaxial cables. Efficiency of overallsystems is thus improved by avoiding the RF cable losses that would resultat the higher powers and higher frequencies (for the K-band system).

These concepts required the development of a K-band transmitter/receiverpackage capable of being operated in a space environment and of beingmechanically and electrically interfaced with a five-foot parabolic antenna.Development of a concept for multiple RF link mechanization was also required.

The first task resulted in a concept for multiple RF link mechanization.Provision is made to switch between the five separate duplex RF channelswhich link the MSS to:

2-1

SD 72-SA-0114-1 .


1. Tracking and data relay satellite (TDRS)

2. Earth orbital shuttle (EOS)

3. Two research application modules (RAM's)

4. Ground stations of the MSFN

Both baseband and RF switching were considered necessary to provide properdata to the desired link. Utilization of a PIN diode RF switching matrixresults in a design concept for a lightweight, compact, reliable RF switchingsystem with presently available hardware. Baseband switching and multiplexingconcepts were also analyzed and recommended systems defined.

2.2 CTB GENERAL DESCRIPTION

A complete set of requirements were developed for a communicationsterminal breadboard (CTB) that can be used as a test bed for evaluation ofthe MSS terminal concept. Figure 2-2 shows the block diagram of this overallcommunication terminal breadboard. The antenna-mounted electronics subassemblywas designed, developed, and delivered as an operating unit to these require-ments. Implementation of a complete system requires the mechanization andinterconnection of other subassemblies that include an antenna system, S-bandconverters to and from baseband, multiplexing and demultiplexing equipment,and a baseband switching system. Requirements for all of these subassemblieswere developed and can be used to obtain available hardware. The antenna-mounted electronics subassembly is supplied with the necessary interconnectcables and control display unit to operate this equipment. Figure 2-3identifies all of this hardware. A concept of the overall breadboardconfiguration is displayed in Figure 2-4. The overall CTB requirementsdefinitions form the basis for ensuring that the ultimate CTB will representa logical development of requirements and concepts. It should be emphasizedthat the characteristics and definitions are by no means frozen. They mayvary to reflect any changes in the station concept as it evolves.

The antenna-mounted electronics subassembly contains a K-band (14.65 GHz)receiver mounted in an enclosure designed for operation in a space environment.The K-band equipment is designed to interface with S-band frequencies,specifically compatible with the LEM transceiver. Thus, a complete operatingbreadboard at K-band can be assembled by connecting and mounting the antennamounted electronics subassembly to an antenna and connecting the K-bandtransmitter input to the LEM transmitter output at 2.2825 GHz and the K-bandreceiver output to the LEM receiver input at 2.1018 GHz. Up and down conversionand the necessary amplification are provided in the K-band equipment package.

The antenna mounted RF electronics subassembly, shown in Figure 2-5,has the following major characteristics:

2-2

SD 72-SA-0114-1

Space DivisionOD North American Rockwell

Transmitter

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Receiver

Input frequency 13.6 GHz

Input RF signal level 83 dBm

RF bandwidth 200 MHz

Receiver system noise <7 dBfigure

Output frequency 2.1018 GHz

Output S-band power level -33 dBm (min.)

Output RF impedance 50 ohms

2.3 TECHNOLOGY GOALS

Detailed design of the antenna-mounted electronics subassembly was based

on the performance requirements that were structured from a set of technological

goals established by NASA. Evaluation of this equipment and its operation will

define the adequacy of these concepts for application to the MSS communicationsterminal design. An effective laboratory and operational test program and

the resultant evaluation will provide data for avoidance of future design and

operational problems.

The total CTB can be expanded to address other technical and operational

problems associated with future concepts and practices for the MSS communicationterminal. Addition of RF switching, S-band terminals, and the associated

baseband switching would allow evaluation of frequency spectrum management,simultaneous multiple links, and EMI problems.

2-3

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*One of the four voice channels - ground to MSS - is a high-fidelity channel 30-10, 000 Hz forentertainment.

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As indicated by the technology goals, CTB/antenna compatibility andtechniques for automatic checkout and control can be investigated by meansof the equipment specified herein.

2.4 HISTORY

At the inception of this program, the CTB was conceived as an S-bandsystem with a solid-state, 20-watt transmitter power amplifier. With thedevelopment of the TDRS concept as the high-data rate relay satellite for MSSto ground, it was decided to change the emphasis for operational frequencyto K-band - the TDRS frequency band. S-band equipment of the type proposedwas already available as off-the-shelf type equipment. K-band equipmentwith a 20-watt RF transmitter power output and low noise K-band receiverequipment needed to be developed and evaluated. These factors led to thedecision to design and build a K-band system after the statement of workhad been negotiated with ITT for the CTB. Final negotiations with MSC andITT resulted in reduction of analysis tasks and complete emphasis on thedevelopment, design, production, test, and delivery of the K-band, antenna-mounted RF electronics assembly. Full use was made of concept developmentactivity in the specification of K-band hardware. This more closely followedthe intent of the program - the demonstration of required new technologies.

2-10

SD 72-SA-0114-1

Space Division9ft North Amenrican Rockwell

3.0 DIGITAL DATA BUS BREADBOARD

3.1 DACS REQUIREMENTS SUMMARY

In the Modular space station, the data processing assembly (DPA) ishighly distributed. The concept of two. pressure volumes results in thedivision of the central processor between two control centers in such a waythat the computations associated with station operations and experiments canbe performed in either volume. Similarly, the subsystems and experiments aredivided between the two pressure volumes; and what is more, the subsystemsare distributed throughout the modules that make up a 6-man or a 12-manconfiguration. Some of these subsystems require on-the-spot computations;these are provided in the DPA design by remote processing units (RPU's).All subsystems require computational support from the DPA. Therefore, theDPA must acquire data from these distributed subsystems and return data,instructions, and commands.

A significant portion of the ADT effort has been devoted to the analysisand breadboarding of a data acquisition and control subassembly (DACS) toprovide the necessary interflow of data between the two. central processors,the subsystems and the experiment equipment. The DACS has been defined toinclude the digital data bus (DDB), the data bus control unit (DBCU), and theremote acquisition and control unit (RACU). Two of these have been analyzedand breadboarded as a part of the ADT effort; these are the DBCU and the DDB.

Figure 3-1 presents the task breakdown and flow which was followed inultimately delivering breadboards of the DBCU and the DDB. Note that a RACU/RPU breadboard is government-furnished equipment (GFE).

The primary objective of the DACS breadboard is to verify the digital databus concept for the modular space station. It will demonstrate the availabilityof technology to provide accuracy of data transfer, reconfigurability, failuretolerance, long useful life, and standardization of interfaces.

The data acquisition and control analyses began with a theoretical analysisof the parameters pertinent to the design and usage of data buses. The resultof this analysis was a design handbook covering the significant aspects of wide-band digital and analog data buses. A model was defined for the data acquisi-tion and control subassembly (DACS) breadboard. The purpose of this definitionwas to provide data to serve as a basis for the design of a DACS breadboard. Itidentifies the objectives of the breadboard, some potential vehicle relateddesign problems, and a simplified implementation concept.

The analysis of DACS redundancy concepts covers the advantages and dis-advantages of a general range of concepts and methods applicable to the DACS.Recommendations of methods were made and justified. The overriding require-ments were found to be the single and triple failure tolerance requirements and

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the physical separation of redundant subsystems into pressure isolatablevolumes.

The recommendations for the degree, level, and type of redundancy foreach DACS element are presented in Vol. III. These recommendations includethe split between hardware and/or software techniques, the utilization oferror protection coding, the replacement/repair methods and a definition ofthe replaceable items, and the rationale for each selected candidate DACSelement.

The following redundancy requirements were imposed on the stationsubsystems:

1. A capability must be provided for each non-critical functionto fail safe for the first failure.

2. For a critical function a capability must be provided for:

a. Full operation subsequent to a first failure (fail operational)b. Reduced or out-of-spec performance subsequent to a third

failure (fail emergency)

3. Time critical functions require active (on-line continuous operation)redundancy. Non-time critical functions require at least standbyredundancy (wired in and activated with automatic or manualswitchover.)

Figure 3-2 presents the recommended implementation of the DACS that willsatisfy the failure criteria (redundancy requirements). The RACU interconnectis shown for one complete critical subsystem functional loop model Type B.Only a small portion of the data bus assembly DB-1 is shown. The RACU inter-connect, as recommended and pictured, allows two of the RACU's and theirassociated subsystem functional loop to be in a standby mode while the othertwo are active. This is true for both time-critical and non-time criticalmodels of Type B.

The overall recommended DACS utilizes parallel and serial redundancyin many combinations. Distributed and functional redundancy are utilized tothe extent possible. BITE is used extensively to aid in failure detection andisolation. Serial redundancy is used for transient error protection throughoutthe subsystem. The DPA multiprocessor and its software is utilized for allhigher level BITE analysis, failure determination, fault isolation and crewnotification for repair by replacement.

This recommended DACS configuration is very sensitive to the two basicoverriding-requirements; these are the single- and triple-failure tolerancerequirements and the separation of all redundant items into two pressureisolatable volumes. The recommendations are also quite sensitive to the IFRUmaintenance philosophy and somewhat sensitive to the other critical functionrequirements.

3-3

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3.2 DACS BREADBOARD DESIGN

The DACS breadboard is an engineering model that is representative of theconcepts for the data acquisition and control function for the data processingassembly of the modular space station. NASA defines a breadboard as a unitwhich performs the same functions according to the same characteristics asthose defined by the hardware design.

A data acquisition and control subsystem is a semi-autonomous subsystemthat provides controlled communication between a large number of .remote.locations and a control location. Insofar as possible, the DACS breadboardis an engineering model representative of the concepts for the data acquisi-tion and control subassembly for the data processing assemEly of the ModularSpace Station. The DACS breadboard also provides a test bed for operationalperformance evaluation of numerous concepts for this type subsystem orientedtoward the specific needs and requirements imposed by the Modular Space Station.

The overall breadboard concept for the DACS is a highly flexible, con-figuration-independent, building-block approach. This approach allows a largenumber of different DACS configurations to be assembled as an operating dataacquisition and control subsystem breadboard. Each configuration concept canthen be operated, tested, and evaluated for overall DACS concept and performancesuitability.

Six basic types of units, plus additional test equipment comprise theDACS breadboard. These are the following:

a) Breadboard Modem Unit(s)b) Core Bus Interface Unit(s)c) Equipment Bus Interface Unit(s)d) Interconnecting Cable(s)e) Breadboard RACU(s)f) Breadboard DBCUg) Special Breadboard Test Equipment

The DACS breadboard was designed within the limits of the followingconstraints:

a) The DACS breadboard shall operate as a self-contained entity withoutthe need for external intervention but under external command, controland influence.

b) Operation of the DACS breadboard will be internally controlled by theData Bus Control Unit (DBCU).

c) All control interaction with the DACS breadboard from externalsources will be through the DBCU.

d) All breadboard performance evaluation will be provided externalto the RACU's, DBCU's, and the data bus breadboard units.

e) The breadboard shall operate with a fixed word length of 8 bits.f) The breadboard shall operate with a variable size message structure

in all modes, of from zero to 124 data words.g) _Hardware error detectionand encoding shall be provided.h) The breadboard units will contain provisions for both fixed and vari-

able coding and decoding of internal commands and data.

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SD 72-SA-0114-1

Space Division'0% 1North American Rockwell

i) All hardware breadboard units shall have a standard disconnect/inter-connect scheme for ease of assembly into various configurations.

j) A method (or methods) shall be provided for simulating faults withinthe breadboard units.

k) Provision for test equipment and/or panels, for determining breadboardperformance, shall be made.

1) All breadboards will be non-redundant; redundant breadboard operationwill be achieved through the use of multiple breadboard units inredundant configurations, and DBCU/Test Processor operational controlprograms and interaction.

m) RACU and DBCU breadboards shall have internal power supplies operatingfrom the primary power source.

The DACS breadboard was designed with the following considerations forhardware error protection.

a) Hardware shall be provided in both RACU and DBCU breadboard unitsto perform error protective encoding and detecting on a word or messagebasis. Correction is not necessary for the DACS breadboard since thiscan be evaluated off-line if desired.

b) The encoding or non-encoding of the data shall be selectable byexternal control.

c) Provisions shall be made to allow other coding schemes generated anddetected external to RACU or DBCU to be passed through the RACU orDBCU.

d) The data so encoded shall be passed through to external devices ineither the encoded or decoded from, or both, for other evaluation,and vice versa.

The data bus breadboard shall be designed within the limits of thefollowing constraints:

a) The data bus breadboard shall be a self-contained time-divisionmultiplexed communication link utilizing pulse code modulation overa hardwired transmission path.

b) Bi-phase level (Manchester) data encoding will be utilized by thebreadboard for transmitting data and control bits.

c) The nominal operating frequency is 10 megabits per second.d) The longest data source to sink distance is 400 feet.e) The longest non-interrupted line segment is 125 feet.f) The number of equipments utilizing the data bus assembly in the

operating system total less than 150.

The breadboard modem units was designed within the limits of the follow-ing constraints:

a) Breadboard modem units include all circuitry necessary for bi-phaselevel-modulation and demodulation, clock recovery from the bi-phaselevel modulated signal, bit timing, preamble decoding, and bus usageby a RACU or DBCU.

3-6

SD 72-SA-0114-1

9|, Space Division01% North American Rockwell

b) Breadboard modem units shall operate in a half or full duplex mode.c) Breadboard modem units shall have the capability whereby the output

power delivered to the line can be externally adjusted through alimited range including the minimum for data bus operation.

d) The breadboard modem unit interface with other DACS breadboard elementsconsists of serial digital NRZ data, serial digital clock signals andvarious DC control signals.

e) Equipments utilizing the breadboard modem units will be assumed inclose physical proximity, i.e., less than five feet from the modem.

The RACU breadboard was designed with the following constraints:

a) The RACU breadboard shall provide the standard interface between thedigital data bus modem breadboard and a simulated subsystem functionalloop.

b) The RACU breadboard shall contain the circuitry necessary to acceptstandard format serial digital data and clock signals from the bread-board modem, to convert the data to signals which are compatible withthe subsystem requirements, to generate the required control signalsfor both the subsystem and for data bus usage, to provide bufferstorage for subsystem data,. and to provide subsystem data to the buson command converted to a standard serial digital format.

c) The RACU breadboard shall be mechanized to respond to two types ofmessages as listed below:

(1) Message A - Transmit Data to DBCU(2) Message B - Receive Data/Commands from DBCU

Responses shall be of three types; no response, acknowledge response,and acknowledge and accept DBCU verification.

d) Each RACU breadboard shall have two input (receive) interfaces andtwo output (transmit) interfaces with the data bus breadboard modem(s).

e) The RACU/modem interfaces shall have..independent address recognitioncircuitry-but are not required to have independent control.

f) A provision shall be made for an external test interface in serialdigital form consisting of the data received via the data bus (output)and accepting data for transmission via the data bus (input).

g) The external serial digital test interface shall have provision forparity generation of data at its input or not, and similarly paritychecking the output data or not, externally selectable.

h) Internal data word buffer storage of 128 words minimum shall beprovided for input and output messages.

i) Data transfer to and from the breadboard modem shall operate at anominal frequency of ten megabits per second.

j) The RACU breadboard shall operate at appropriate time from three clocksources; either the receive clock from the modem, its own internalclock, or an external clock source via the test interface.

k) A subsystem functional loop simulator interface shall have provisionfor variable numbers of DC analog and discrete signals to bemultiplexed at varying sample rates, converted to digital form, andformatted.

3-7

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1) Special provision for local indication. of responses to non-datacommands from the DBCU should be considered.

m) Provision shall be made for an external preprocessor interface.n) RACU addresses shall be externally pre-set.o) All RACU operation will be under higher level control by the DBCU.

Operation will be specified by the DBCU commands in each message.RACU operational sequences can be performed by hardware and/orsoftware techniques.

p) A provision for variable decoding of DBCU commands shall be includedto allow changing RACU operational modes and command responses.

The data bus control unit breadboard shall be designed within the limitsof the following constraints:

a) The DBCU shall provide all command. and control capabilities for fullyexercising the DACS breadboard.

b) The DBCU breadboard shall contain the circuitry necessary to originateand control all messages for the DACS breadboard, to communicate withRACU breadboards via the breadboard modem units and data bus and tooperate the DACS breadboard with or without test processor interaction.

c) Two types of messages shall be originated by the DBCU breadboard aslisted below:

(1) Message A - Request Data from an RACU(2) Message B - Transmit. Data/command. to an RACU

d) The breadboard DBCU shall have dual, switch.selectable, interfacecapability for communicating with.breadboard modem units.

e) Provision shall be included for an external test I/O interface con-sisting of serial digital data for transmission to RACU's and datareceived from RACU's.

f) The external serial digital test interface shall have provision.,forparity.generation and detection of I/O data or not, externallyselectable.

g) Internal data word storage shall be..provided for message data sequencesand buffering (minimum size of. 128 words).

h) Data transfer to and from the breadboard modem units shall operateat a nominal frequency of ten megabits per second.

i) The DBCU breadboard shall operate at appropriate times from any ofthree clock sources; the receive clock from the modem, an internalclock source, or an external clock source via.the test interface.

j) Message-generation shall be under internal program control, includingsuch message options and factors as.message type, message size, RACUacknowledge,.command.verification, data retransmission, procedures foroperation with errors detected.and improper response conditions, andinteraction with external equipments.

k) The internal DBCU breadboard operational program shall be bothexternally selectable and changeable via the test processor, testpanel and breadboard user.

1) A test processor and test panel interface shall be provided forparallel and/or serial digital.data transfer and DBCU (and thereforeDACS breadboard) higher level control.

3-8

SD 72-SA-0114-1

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m) The DBCU breadboard-shall be capable-of providing internal operationstatus and.DACS breadboard operational status data to the test paneland/or test processor. This status data will include that obtainedfrom the RACU's, .data bus breadboard status, the DBCU status, theerrors detected, the operational DACS.control modes being utilized(see item j), and improper DACS.breadboard .operation.

Figure 3-3 illustrates a laboratory configuration of the DACS breadboard.It will be possible with this breadboard, then, to evaluate wideband digitaldata bus operation (10 Mbps), automatic fault detection and isolation, auto-matic reconfiguration, techniques for executive control of data traffic, etc.

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4.0 DATA PROCESSING ASSEMBLY DEFINITION

4.1 SUMMARY

The requirements for a long duration manned space station includecontinuous maintenance of operational capability with minimum crew partici-pation. This requirement can be achieved by automating operations of thesubsystem functions with use of a computer system, referred to as the dataprocessing assembly (DPA). Figure 4-1 represents the modular space station(MSS) DPA configuration. The computations required may be performed in anumber of ways. The concepts, performance mechanization, reliability, andcost are sensitive to the amount of automation required.

Volume IV of this report summarizes the efforts directed to defining theDPA data input/output requirements and traffic flow patterns, allocating oflogical and computational functions for the development of information flowdiagrams, and defining a DPA configuration.

The approach taken was to (1) define the computation and logicalfunctions which must be performed by the data processing assembly (DPA)for the orbital operations, (2) define in preliminary form the memory sizeand computer speed required to accomplish these functions, (3) allocatecomputations and logical operations to elements of the DPA, (4) developpreliminary flow diagrams which portray the information flow rates andfunctions performed by the DPA and its input/output interface with the MSSsubsystems and (5) define a DPA configuration.

Figures 4-2 and 4-3 present the configuration selected for the dataprocessing assembly. As noted, the station operations central processor islocated in the primary control module (SM-1). Supervisory control of theequipment in the power and core modules is provided via a radio link duringstation buildup prior to SM-1 arrival. A special component (buildup dataprocessor) is located in the core module for interfacing with the radio linkand DPA. This component will be removed or disengaged when SM-1 arrives andsupervisory control is exercised by the station operations control processor.

The baseline configuration is further shown to consist of remoteprocessing units (RPU's) performing subsystem functions and failure detection.A redundant bus network connects these and the remote acquisition and controlunits (RACU's) to the central processor. A multiprocessor organization hasbeen defined as the most suitable for the central processor. Redundancy atthe central control level is further supplied by another central computercontaining the critical operations functions and experiment support software.This second central processor is located in another pressure volume (SM-4)and is identical to the primary computer. The RPU's consist of uniprocessorswith special input/output processing or signal processing as required toaccommodate the subsystem functional requirements.

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Figure 4-4 shows the tasks, their relationships, and the subcontractorswho participated in each task. The impact of the simultaneous MSS Phase Bstudy is also indicated. It will be noticed in reading this report (VolumeIV) that many different values of memory size and operating speed are used.Basically, this is due to two factors: the DPA studies were impacted by thePhase B studies and the DPA studies were iterative (particularly as regardsthe selection of a DPA configuration). The most significant differencebetween two sets of DPA requirements is due to the ongoing requirements andsubsystems analysis in the Phase B study. Once past the insertion of thislarge delta, the differences in assumed requirements is minor (not more than10%) and does not significantly alter the DPA concept or the results of thestudy.

The study began with an analysis of the DPA requirements. This taskdefined the subsystems' functions which require data processing support;defined the mechanization required to provide data processing support foreach identified function; estimated the memory, speed, and input/outputdata rates required for mechanization of each function; and integrated thesubsystems' computation requirements to define a total set of MSS DPArequirements. Table 4-1 presents the performance requirements for stationoperations in parameters of processing speed, memory capacity, and data busrate. Shown are the basic requirements, the design margin, the growth margin,the initial design requirements, and the maximum design requirements.

The next task was the definition of the baseline DPA configuration. Thealternatives to be considered at each processing level were enumerated, andthe distribution of the signals (subsystem interfaces) was tabulated on thebasis of the physical distribution of the MSS subsystem. A tradeoff resultedin the selection of a central multiprocessor plus subsystem preprocessing asrequired. The multiprocessor-to-subsystem interfaces are to be implementedwith RACU's which communicate with the central processor via a digital,time-serial data bus.

The purpose of the information flow study was to define the MSS DPAinformation flow so that the DPA could be simulated with NASA's IMSIM. Amethod of flow diagram and attendant tabulations presentation was carefullyselected to provide a comprehensive data file of software and informationcharacteristics that will prove beneficial in the continuation of the advanceddevelopment tasks and related studies. This data file consists of descriptionsof each subsystem, baseline configuration data, buildup information, DPAcomputational loads and allocations, computer sizing information, messagetabulations, signal interface lists, and DPA parametric data requirements.

The objective of the DPA throughput simulation was to provide informationthat would facilitate a selection of the final DPA configuration for the MSS;in particular, to provide information pertaining to DPA component performancethat would yield a DPA configuration capable of accommodating imposed workloadswithin required response times.

The operational doctrine assumed to be in effect for the data bus is thatof polling. Polling control is assumed to be a function of the I/O unit andthe polling schedule is assumed to be on a fixed time basis per device. The

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Nine time slots (36 ms) were simulated; these were the initial nineslots of each one-second interval (250 slots) and were chosen for imposingthe largest operational load on the DPA. Processor utilization during theexecution of the simulation is shown in Figure 4-5. The simulations led tothe following conclusions: the central processor can effectively processexpected worloads; arithmetic unit speed of 750 KEAPS is adequate; the I/Oprocessor is under-utilized at 750 KEAPS; a data bus commutation cycle of250 slots per second is reasonable; the operating memory transfer rate of2 x 106 words per second is adequate; and the mass memory transfer rate of1 x 106 words per second is adequate.

The application of redundancy to the DPA stems from the failure criteriaestablished for the MSS. The redundancy study was directed toward applyingthe criteria to the DPA concepts and recommending a satisfactory operationalsystem. The recommended redundancy configuration is shown in Figure 4-6.The redundancy recommendations are shown in Table 4-2.

The objective of the central processor study was to determine theinfluence of the MSS central processor operational use and software organizationon the design of the hardware aspects of the central processor. The architectureof the central processor was recommended to be as shown in Figure 4-7. Theconcept of a higher order language machine (HOLM) was studied as a basis forstudying the central processor memory hierarchy and the internal bus design.Figure 4-8 shows the memory hierarchy which was studied for the MSS dataprocessing assembly; Figure 4-9 presents the candidate internal busconfigurations. Tables 4-3 and 4-4 summarize the conclusions reached duringthe study. Further analyses of fault tolerance for the central processorwere conducted for the HOLM. The conclusions of those analyses are presentedin Table 4-5.

Subsequent to the selection of a baseline DPA configuration, several ofthe influencing factors were changed as a result of the concurrent MSS PhaseB definition studies. Most notable of these factors were the new buildupsequence for the MSS, the redefined DPA failure and error tolerance criteria,and the redefined computational requirements. The DPA configuration wasredefined on the basis of these new factors and the studies that werecompleted (as shown in Figures 4-2 and 4-3). An analysis was also performedto determine the effects of a more efficient distribution of the processingtasks within the central processor between the arithmetic units and the input/output processors. Figure 4-10 presents a detailed allocation of the centralprocessor functions which resulted from this analysis.

4.2 DPA DEFINITION

The data processing assembly (DPA) provides the computing functionsneeded for a high degree of reliable automation in the modular space station(MSS). The central processors and preprocessors are key elements of the DPAand must perform reliably and effectively over the life of the station. Theprocessor performance requirements task covers the central processor and

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preprocessor in terms of their internal organization and required functionaland performance characteristics.

The central processor is a multiprocessor which possesses the featuresshown in Table 4-6. As noted, a conventional organization is preferred. Amemory hierarchy consisting of buffer memories in the processing elementsand of modular operating and mass memories is provided. The requirementscan be met with two arithmetic and input-output processing sets. Eachset contains dual units with capability of comparing memory addressing,controls, and processed results.

The central processor utilizes two operating memories for the mainstorage functions. These memories are supplied by paging techniques withinformation from a mass memory. Additional offline storage is provided byan archive memory. The key features of these are shown in Table 4-6.

An arithmetic unit provides one million equivalent adds per secondcapability. An extensive repertoire, including floating point, isincorporated into the design. Modes of operation include the normalcomputational and the executive. Privileged instructions only executablein the latter are used. Linkage to the executive mode is by interruptsand special instructions.

All input-output functions are controlled by the AU's by means of I/Ocontrol words and commands from the AU's. Once initiated, I/O actionsproceed independently of the AU's until completed.

Two transformer rectifier sets are used to convert the primary acvoltages to secondary dc voltages. A redundant power distribution capabilityis provided internal to the CP. Each set contains power circuitry in activeredundancy capable of using either of the secondary sources.

It was noted earlier that the state of art of smaller aerospace

computers is well advanced in preprocessing. The typical characteristicsachievable from these is shown in Table 4-7.

The physical values shown in Table 4-6 and 4-7 are achievable with

today's packaging capability. The processors are based upon the use of cased

devices on multilayer boards. The mass memory utilizes 2 mil plated wireand power strobing and high density devices with beam leads, hybrid thinfilm and ceramic substrates.

4.3 DMS PROCESSOR EEM DEVELOPMENT PLAN

The development and test plan for the DMS EEM processor presents the

schedule and identifies the major tasks. This plan is consistent with and

requires inputs and support from the space station information management

system (IMS) advanced development technology (ADT) program described inSD 71-240, Information Management Advanced Development Technology Extension

Study Plan, North American Rockwell, Space Division, October 1, 1971.

4-19

SD 72-SA-0114-1


Table 4.6. Technical Characteristics of the Central Processor

Type:

Multiprocessor, conventional organization, paralle, binary, 16/32 bitdata and instruction words

Operating Memory, M2:

Two required, plated wire, NDRO, each consists of five memory modules of13K x 33 bits maximum, one parity bit per memory word, one parity wordexclusive OR-ed with block address for every five memory words, echochecking of write operations, one microsecond cycle time with interleav-ing of.the five memory modules, maximum capacity of 18K x 33 bits pereach module.

Auxiliary Memories:

Mass Memory - M3, Virtual memory using paging methods, error detectionusing one parity bit per word and one parity word with address exclusiveORed per every four data words; echo checking of write operations, 2 milplated wire, NDRO, maximum capability of 1280K x 33 bits, modular designbased upon 64K modules.

Archive Memory - Magnetic tape storage with > 5x106 bits per cartridge.

Input-Output:

Two required, each contains dual IO units with comparator AU initiatedwith self-contained control, solid state buffer memory of nominal 2K x33 words and 200 nanosecond cycle time, interface with data bus controlunit, telemetry bus, and mass memory.

Arithmetic Set:

Two required, each contains dual arithmetic units with comparator, solidstate buffer memory of nominal 2K x 33 words and 200 nanosecond cycletime 1 million equivalent adds per second per set, fixed and floatingpoint with 100-200 instructions.

Physical Estimates:

Mass Memory Archive Memory Multiprocessor Set

Size (cubic inches) 3900 1200 1000

Weight (pounds) 180 40 290

Power (watts) 15 45 400

4-20

SD 72-SA-0114-1

Space Division• North American Rockwell

Table 4-7. Technical Characteristics of the Preprocessor

Type:

Uniprocessor, parallel-binary, 16 bits data, 16/32 bit instruction words

Memory:

Capacity - 20K word, 17 bit plated wire storage

One bit of parity per 16 bits

Cycle time - 1 microsecond

Input/Output:

One buffered 16 bit parallel input and output channel

Eight external interrupts

Instruction Repertoire:

Single and double word addressing

Single word non-addressing

Indexing

Indirect addressing

Add Times (Fixed Point):

Add - 4 microseconds

Multiply - 20 microseconds

Divide - 40 microseconds

Special Features:

Internal and external interrupts

General register file usable as index, base, or data register

Physical (20K x 17 Bits):

Size - 400 cubic inches

Weight - 15 pounds

Power - 50 watts

4-21SD 72-SA-0114-1

|^% Space Division90 %North American Rockwell

The IMS ADT program is structured to include hardware and softwarestudies leading to specifications and breadboard equipment for investigatingkey aspects of a spacecraft data handling system. These studies are necessaryto support the procurement of the EEM processor. The breadboards and softwaredefined in the ADT are required to enable concept evaluation and IMS integrationtesting.

The near-goal (1974) objective would be to assemble a prototype datamanagement system to be used to develop automated subsystem's operations,orbiter payload interface requirements and payload data management operations.Figure 4-11 relates the present ADT BB equipments to this objective by aseries of tasks. Figure 4-12 illustrates how these ADT extension (ADTX)tasks contribute to the definition and procurement schedule of an engineeringevaluation model (EEM) of the DMS multiprocessor.

A development program consisting of three phases will provide the EEMprocessor. Further, dependent upon the level of available funding, varioustypes of processor/breadboards may be procured.

Three possible breadboard processors are:

a. Simplex Model - I AU set; 1 IO set; 1 OM set andusable with the existing DACS breadboard

b. Multiprocessor Model - 2 AU sets; 2 IO sets; 2 OMsets and usable with the expanded DACS breadboard

c. Dual MP Model - Duplicate processors each consistingof 2 AU sets; 2 IO sets; 2 OM sets

The three phases and estimated durations are as follows:

Phase I: Requirements Analysis - 10 months

Phase II: Procurement

Simplex Model - 12 monthsMultiprocessor Model - 15 monthsDual MP Model - 18 months

Phase III: Testing

Simplex Model - 8 months (acceptance)Multiprocessor Model - 10 monthsDual MP Model - 12 months

Figure 4-12 showed the major milestones of the ADT extension study whichwill provide detailed definition of the central processor requirements andof the EEM processor requirements. This figure shows a requirement of 21months to define the requirements and perform the EEM processor design analysis.This period would be followed by procurement and testing of the EEM processor -requiring between 20 and 30 months depending on the option chosen.

4-22SD 72-SA-0114-1

Space Division

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In any event, it will be necessary to procure and evaluate a dualmultiprocessor model prior to the procurement of the MSS central processors.There are a number of ways to accomplish this goal ranging all the way fromsequential procurement of sufficiently many simplex models to all-outprocurement of a dual multiprocessor in one effort.

To illustrate some of the effects of these possible procurementplans, we begin by assuming:

1. MSS IOC at the end of 1984

2. 18 months for MSS subsystems integration

3. 6 months for flight article dual multiprocessoracceptance and qualification testing

4. 18 months for procurement of the MSS flight articledual multiprocessor

5. At least 12 months of evaluation testing with the EEMdual multiprocessor prior to procurement of the flightarticle dual multiprocessor

Based on these, we can schedule IOC of the EEM dual multiprocessorfor mid-1980. These assumptions and three procurement options are illustratedin Figure 4-13.

The first option represents sequential procurement of two simplex models(together forming a multiprocessor) followed by procurement of a secondmultiprocessor. This option will require the initiation of the requirementsdefinition-at the beginning of 1974. This option may also be characterizedas having the least risk and by having the lowest peak of funding spreadover 7.5 years.

The second option represents sequential procurement of two multiprocessors.Initiation of requirements definition could be delayed a year to the beginningof 1975, but this option would require higher funding peaks and higher-risk.

The third option represents procurement of a dual multiprocessor savinganother 15 months but requiring the highest funding peak and the highest riskof all the options.

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4-27SD 72-SA-0114-1

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5.0 COMPUTER PROGRAM (SOFTWARE) ASSEMBLY DEFINITION

5.1 SUMMARY

The modular space station (MSS) incorporates a very large digital computercomplex to assist the crew in accomplishing their assigned tasks. It was recog-nized from the inception of the Phase B study that the definition of the designrequirements for the computer complex would be sensitive to the software (com-puter programs) that was to run it. To emphasize the importance of the softwarein the MSS program, it was defined to be an assembly, on the same level, butseparate from the hardware assembly. It was also recognized that the assign-ment of functions to the several subassemblies (both hardware and software)would involve many tradeoffs to obtain a realistic configuration.

Therefore, the MSS software assembly was included within the advanceddevelopment task (ADT) as a series of interrelated studies in concert withsimilar data processing assembly (Volume IV) studies; these tasks weredeveloped and conducted by representatives from System Development Corporation,Autonetics, and Space Division as a cooperative effort. The intent of thesetasks was to develop uniform computer program standards and conventions forthe space station program, develop a computer program specification hierarchy,define a computer program development plan, make recommendations for theeffective utilization of all operating on-board space station program relateddata processing facilities, and develop a preliminary computer specificationfor the MSS CP executive program.

These five subtasks are by no means exhaustive of the necessary preliminarystudies of the MSS software assembly that need to be completed before any actualcomputer programs are written; they are, perhaps, the very tip of the iceberg ofsoftware cost avoidance. Historically, the costs of developing software forextensive computer systems have been buried under other titles and have seldomindicated that the man-hours and other cost dollars attributable to hardware(the computer system) are usually exceeded by the costs for the programs thatare to be run in the computer. Recognition of this situation caused NR-MSCto identify all the MSS software as a separate assembly of the on-boardinformation management system - to further identify and device means to avoidthe excessive cost buildup.

Identification of the components of software cost buildup strongly influ-enced the preliminary design of the MSS data processing assembly. Typically,the factors of limited computer speed and memory capacity were identified asa strong driver on software costs; the MSS DPA is, therefore, oversized interms of identifiable station operations needs (Refer to Volume IV of thisreport). Another factor listed by many was the lack of experienced computer

program designers; the MSS preliminary design was based upon the assumptionthat if the programs (routines) could be written in a higher-order language(HOL), in sufficiently small modules, this factor could be reduced considerably

Preceding page blank |5-1

SD 72-SA-0114-1


in influence. However, in order to accomplish this desirable objective, thetotal must be divided into very small work packages; governed by standardizedterminology and procedures; planned to be effected during a progressive,unhurried time scale; and controlled with the same attention to quality andspecificity as any of the hardware developments. It was to these points thatthe IMS ADT software assembly studies were addressed.

5.2 MSS SOFTWARE STANDARDS AND CONVENTIONS

The objective of this study was to define and rationalize an initial setof computer program standards and conventions for the information subsystem(ISS) of the modular space station (MSS) program.

For all large systems, software or hardware, the establishment andimplementation of standards and good operating practices and conventions isan ongoing process which continues to be refined throughout the life of thesystem. In this respect, the material presented is not intended to be finalor all inclusive. However, it is intended to identify those areas of profit-able standardization and good practice which can serve as a base for uniformdesign, development, and implementation.

Basic Definitions

As used in this document, a standard is a definite rule or procedurewhich has been established by authority. A convention is a customary oragreed-upon rule or procedure. These standards and conventions will be ofprime importance to computer programmers, system designers, and software sys-tem managers.

Software is defined as the computer programs and the programming aids anddocumentation required to produce and describe computer programs. This defin-ition includes not only the operational programs but also support programssuch as compilers, loaders, simulators, data reduction, analysis and documenta-tion.

Software techniques are the methods used to produce computer programs.They include state-of-the-art knowledge and all tools which are and have beenapplied in computer programming activities.

Common and/or frequently used areas of software technique applicationsare termed information processing functions. These functions identify a groupof actions and/or activities required to meet system software requirements.From a review of MSS operational and support elements, with possible softwareinvolvement, 14 basic information processing functions were identified. Theseare:

* Program production * Decision making· Program organization * Bookkeeping* Documentation * Timing* Program testing · Message formatting* File management · Simulation* Symbol manipulation * Personnel· Calculations * Management

5-2

SD 72-SA-0114-1

Space Divisionji• North American Rockwell

The standards and conventions presented are identified and discussedwithin a framework of 12 topic areas. Six of these are information processingfunctions, where a variety of software techniques are applicable and six arespecific software techniques. This structure was selected as the most optimumto cover the subject of software standards and conventions for the MSS program.

· Languages- * Symbols· Compilers · Units of measurement and coversiono Program production · Documentation* System organization · Testing and validation* Formats · Maintenance· Technology and abbreviations * Management

Table 5-1 summarizes the suggested baseline standard and conventions.The intent of this section is to define an initial set of computer programstandards and conventions that can serve as a beginning to the standards andconventions guidelines that will, be required for the MSS program.

5.3 COMPUTER PROGRAM SPECIFICATION TREE

The objective of this study was to:

1. Develop a computer program specification hierarchy anddescribe in detail each component in the hierarchy

2. Prepare a preliminary top-level computer program systemspecification containing system performance and designrequirements, system segment allocations and interfaces,identification of major contract end items, and require-ments for system testing.

Figure 5-1 illustrates the logical sequence of contract end items to beproduced and delivered and the responsible agency.

Figure 5-2 illustrates the detailed specification tree containing eachspecification as part of the DPA. For clarity, the computer program/moduleslistings have been indicated by symbol (A). Each symbol represents a numberof listings corresponding to the number of subprograms or modules containedin the Part II specification.

Figure 5-3 illustrates the functional data processing requirements forMSS subsystem operations, extracted from the complete Preliminary Top-LevelComputer Program System Specification of Volume V.

This specification establishes the top-level requirements for the perform-ance, design, test and qualification of a computer program identified as theModular Space Station Master Computer Program and defines in logical, and oper-ational language-the detail necessary to design, produce, and test this program.Data processing functions from all other subsystems are included in thisspecification.

5-3

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SPACE STATION SYSTEMREQUIREMENTS SPECIFICATION

SPACE STATION COMPUTER PROGRAMDEVELOPMENT PLAN

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COMPUTER PROGRAM SYSTEMINTERFACE SP ECIFI CATION

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Figure 5-1. Hierarchy of Plans and Specifications

5-10

SD 72-SA-0114-1

Space Division9D North American Rockwell

SPACE STATIONSYSTEM

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5.4 COMPUTER PROGRAM DEVELOPMENT PLAN

The computer programs required to perform all ISS functions and the soft-ware tools used to develop, test, and validate these computer programs consti-tute the MSS software assembly. Figure 5-4 identifies the five major subassemb-lies and illustrates an important aspect; namely, that the many modular routinesare categorized by similarity.

Figure 5-5 lists the numerous software techniques that apply to the fivesubassemblies to indicate the type of activity controlled as implemented bythe modular routines.

Figure 5-6 indicates how one subassembly (supervisory) would be assembledfrom small modules into routines, then into a master tape, and eventually intothe total software system (ISS software assembly). Note that to avoid confu-sion, the terms assemblies, subsystems, etc., are not per the MSS hardware"tree," but are conventional software terminology (A.N.S.I. x3.12-1970). Inthis sense, a computer program module is a single program, a small group ofcomputer programs that performs a single or basic operation.

To accomplish the development of the large order of computer programmingfor the MSS, it should be recognized that a strong, high-level authoritystructure is needed, particularly since there is a high degree of overlap andcommonality with other space programs. Both Skylab and the earth orbitalshuttle, as well as MSS and RAM, are integral parts of the whole space stationprogram. Figure 5-7 suggests that one way to provide orderly management andto avoid needless duplication of effort would be to enforce, at the highestlevel, the same emphasis on interprogram coordination and commonality forsoftware and hardware.

Figure 5-8 illustrates the recommended development flow for the MSSmaster tape and MSS subsystems operations tape; it is felt these softwaresubassemblies must be flexible to follow the changes and modifications inrequirements as the program develops. It is felt that three versions(V1 , V2, V3) will be adequate. The remaining software could utilize a single-version approach. Figure 5-9 shows the time-phased software developmentschedule and indicates that to achieve an MSS IOC in 1983 that the initialversion of DPA software requirements should be available in 1977-78. Figure5-10 continues the software development schedule milestones in greater detail.Note that the Version 3 software is used (per MSS program philosophy) toperform the vehicle subsystems installation, checkout, and acceptance and thusmust be available about 1981-82.

5.5 COMPUTER-ASSISTED RESOURCE ALLOCATION AND UTILIZATION

Recommended data processing techniques and procedures for the planning,scheduling, and allocation aspects of an operational modular space station(MSS) total system are presented as conceptual and capability requirements inVolume V. Specific examples of recommended concepts and capabilities,. inrespect to MSS requirements, are discussed and illustrated with the recommenda-tions. Following the recommendations, an implementation summary is presented.

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MSS system allocation, scheduling, and planning requirements include thosenecessary to perform mission and experiment operations both on-board the spacestation and all supporting ground-based facilities. These requirements arepresented under the three subheadings of: (1) Users, (2) Processed Data, and(3) Resources.

Volume V also presents a condensed but comprehensive discussion of pastand current computer-assisted allocation, scheduling, and planning technology.Past technology is discussed primarily in respect to problem areas and experi-ence with implemented systems. Current technology is discussed in respect tothe approaches being utilized and the basic operations performed.

The major resources that will require allocation and scheduling duringspace station missions are (1) data processing capabilities, (2) on-boardconsumables, (3) on-board and ground-based sensors, and (4) personnel skills.Discussions of utilization implications for these resources are presented inthe following sections.

In discussing the data processing resources that must be employed for thespace station program, it is important to note the distinction between the useof on-board computer-assisted methods to perform the scheduling function itself,as compared to the scheduled employment of these data processing resourcesto support station operations and experiments. Implications of these two areasare as follows:

1. Performance of scheduling function. It is envisioned that theon-board scheduling functions will be performed on the stationoperations central processor of the data processing assembly.There are two functions which involve resource allocation, bothof which are noncritical information subsystem operations.Characteristics of these functions are as follows:

Required RequiredFunction Operating Mass Anticipated

Memory Memory OperationsPlanning and

scheduling 2K words 21K words Background

Logisticsinventorycontrol 2K words 8K words 2.3 KEAPS

It should be noted that these on-board estimates were predicatedon a large proportion of the scheduling function being performedon the ground. Sizings were based upon the assumption that long-range and comprehensive weekly and monthly planning and schedul-ing activities will be performed on the ground with necessarydata transmitted (data link or shuttle delivery) to the spacestation. The on-board planning and scheduling routines will pro-vide for control, manipulation, and modification of the groundgenerated data.

5-23

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It is quite possible that a heavier load of on-board schedulingrequirements than those indicated above may be imposed on thespace station, especially if it can be shown that interactiveon-board scheduling is an efficient means for controlling theutilization of station resources. This would raise the storageand speed estimates, and thus impose increases in the overallmemory and speed requirements for the central processors (CP's).The tradeoffs and implications of heavier on-board schedulingrequirements will be discussed in subsequent sections of thisreport.

2. Employment of data processing resources for operations andexperiments support. The emphasis throughout the ADT efforthas been on the analysis and sizing of the station operationscentral processor. Since station operations have been com-paratively well defined, specific estimates of the loadsimposed on the DPA by the seven operational subsystems werecompiled and used to size the speed requirements of the CP,as well as for sizing of operational, mass, and archivalmemory requirements. The assumption has been that experimentsupport will be performed by the second CP (the experimentscentral processor), but that the architecture and componentparameters of this second CP will be identical to that of theoperations CP.

Conceptually, the MSS system will differ from previous space projects inthat major portions of the orbiting station's mission management functionswill be performed cn-board the station. The ground-based mission control andexperiment control centers will monitor, back up, and supplement the on-boardmission management, plus serve as points of coordination for system users.Recommendations for computer-assisted allocation, scheduling, and planningtechniques presented in this section are based on the assumption that theabove described operating philosophy will be implemented.

To meet the planning, scheduling, and allocation requirements of the totalMSS operational system, a computer program system which provides a centralizedsource of scheduling information which may be changed or queried on demand isrecommended. Significant features of this scheduling system should be:

* General applicability* User-orientede Accommodation of constraints and prioritiese Conflict identification and resolution* Generation and maintenance of current data buses

The total scheduling system should consist of compatible installations on-board the space station and at the ground-based mission control center. Input/output terminals will be located at each installation and consist of interactivedisplay consoles equipped with functional keys, alphanumeric keyboards, light-pens, and channel selection keys to provide access to and control of the database.

5-24SD 72-SA-0114-1

Space Division9us North American Rockwell

The data base should consist of the following basic categories of data:

1. Environment. Current condition information on all systemparameters

2. Task. Information on requested scheduled activities andrequired resources

3. Event. Information on past and predicted future events;performance, execution times, resources utilized andrelationships to other events

4. Display. Preformatted displays which can be requested bythe system operators.

On-line access to the large data base is the basic operating concept ofthe system. As new data become available, or as changes in scheduling require-ments and resource conditions occur, on-line access to the data base providesconsole operators on board the station and at mission control the most effec-tive means of facilitating their decision-making responsibilities, while atthe same time, increasing the span of control over the resource allocationand schedule implementation functions. Interaction with the operational database is an integral part of this process. The system outputs "working" dis-plays of operator selected data, providing computer-generated responses as theinteractive console operator performs additions, deletions, and modificationsto the data base being presented.

Major capabilities of the system will be as follows:

1. Data base formulation. Provides on-line input of system envir-onment, scheduling requirements, selection and scheduling criteria,non-space station associated support requests, and batch input ofspace station information and post-event reports.

2. Data retrieval. Provides access to the data base through variousmedia.

a. TV displays: space station characteristics, ground-stationcapabilities, space station activity plot, ground-stationactivity plot, space station schedules, ground stationschedules, priority lists, and parameter entry displays fordata control functions

b. Printed listings: space station schedules, ground-stationschedules, space station characteristics, ground-stationcapabilities, priority lists, and printouts depicting resultsfrom data base editing functions

5-25SD 72-SA-0114-1


c. Teletype format paper tape: space station schedules foruse by the operations control center, supporting stations,and other system users

3. Data base control. Provides control of the information in thedata base by utilization of alphanumeric keyboards and light-pendevice for interaction with TV displays, user-oriented data andcontrol cards for batch input or requests or non-event associatedactivities, and magnetic tape and/or disc files for batch inputof event summary data.

4. Scheduling. The scheduling capability provided by the system willallow a maximum of user control over the selection and schedulingof required support activities. There should be two basic modesof scheduling within the system - discrete and algorithmic.

The discrete mode is defined here as the human process of selectingor scheduling one identifiable activity.

Conversely, the algorithmic mode is defined as the computer pro-gram processing of selecting and/or scheduling one or moreidentifiable activities during one continuous operation.

The discrete mode provides the capability of retrieving informa-tion on a particular event or activity, querying the system asto conflicts or constraints concerning that activity, and assign-ing a desired status.

The algorithmic mode provides facilities for (1) scheduling anaggregate of activities which have previously been "requested"as a function of the discrete mode, and (2) scheduling of spacestation functions which are selected by the program on the basisof scheduling requirements defined in the system environment.The first method searches the data base for all activitiessatisfying operator-selected conditions (e.g., time span, ground-station, space station, support type, etc.) and whose schedulestatus is "requested." For each "requested" activity encountered,the function will change its status to "scheduled" if no resourceconflict exists. If a conflict exists, a conflict summary print-out will be generated Conflict resolution is performed as afunction of the discrete mode of scheduling.

The second method searches the data base for space station activ-ities which satisfy the scheduling requirements defined in thesystem environment and which are not in conflict with activitiesalready scheduled, and assigns a status of "scheduled" to eachselected task. In addition, this method schedules "requested"tasks where possible. When requirements cannot be satisfied, aconflict summary printout is generated. Again, subsequent con-flict resolution may be performed as a function of the discretemode.

5-26

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5. General file editing. Provides the console operator with generaldata base maintenance functions:

a. Delete, add, or modify individual support activities

b. Delete a series of support activities

c. Slide the support times associated with a series of spacestation passes forward or backward in time

d. Purge the data base, deleting support activities prior toa specified time

6. Display control. Provides the capability to assign any displayappearing on an interactive console to any channel on the TVvideo drum for subsequent call-up by monitor positions.

7. Data base protection. Certain data base protection features areprovided to reduce the possibility of both interactive consoleoperators attempting to modify support activities that cover thesame time span. Requests for certain functions in the systemwill be honored only when another console is quiescent, effect-ively locking out the other console for the duration of thatfunction. Examples of functions falling under this restrictionare purges of the data base, input of new pass summary informa-tion, slides of activities, and input of station post-pass reports.Generally, this restriction will apply to any function which wouldeffect massive data file restructuring.

Additionally, alarms will be displayed to the interactive consoleoperator when he attempts to modify support activities whose starttimes are later than the beginning of the next daily schedule tobe generated.

The same basic system capabilities should be provided for the on-board and ground-based portions of the total system. However,capability and capacity should be implemented to meet the followingoperational philosophy:

a. On-board space station planning, scheduling, and allocationfunctions should be confined to a specific operational timespan. This time span should be of sufficient duration tomeet all but long-range planning needs.

b. Ground-based planning, scheduling and allocation functionsshould consist of support and verification of those per-formed on the space station plus long-range planning withoptimization study and analysis, i.e., the ground-basedscheduling system should function operationally to supportthe space station, but should also be used to perform long-range studies of new and/or modified system requirements.

5- 27SD 72-SA-0114-1

Space Division01% North American Rockwell

6.0 DPA SUPERVISOR PROGRAM

The supervisory function is essentially that of keeping a data processingsystem usefully occupied. This requires scheduling and activation of the var-ious software tasks that perform all the system functions. This, in turn,involves monitoring events, allocating resources, and providing proper inter-faces among separate software modules, among hardware modules, and between thesoftware and hardware. The supervisor must also respond to anomalous events,or errors, and initiate procedures to correct errors, isolate failures and,when possible, reconfigure the system to keep operating in spite of failures.In addition, the supervisor should maintain records for later analysis toidentify hardware and software deficiencies that produce errors or otherwiseadversely affect system performance. Since the supervisor itself is an over-head item that does not directly perform system functions, its intrusions(time and facilities used) should be kept to a minimum.

6.1 MODULAR SPACE STATION OPERATIONS CONTROL CENTRAL PROCESSOR SUPERVISORCOMPUTER PROGRAM SPECIFICATION (PRELIMINARY)

6.1.1 Scope

This specification establishes the requirements for the supervisory soft-ware in the data processing assembly of the modular space station. In itspresent form, the specification is restricted to that part of the softwarethat resides in the central processor dedicated to station operations.

6.1.2 Requirements

6.1.2.1 System Considerations

The supervisor will be controlling the activity and assignment of allhardware and software elements within a central processor and will monitor thestatus of all elements of the DPA. All software elements will be well testedand essentially debugged. The software will consist of application programswritten to support MSS operations, the supervisor program being described, andvarious utility programs and subroutines available to all programs. All pro-grams will be broken into independently executable modules, each of which willhave a module control block (MCB) that will provide the supervisor with inform-ation needed to respond to and control each module. All internal applicationdata will be either public or private, the public data being available in

essentially fixed locations and the private data for use within a module or forcommunicating between modules being in blocks temporarily assigned to the givenmodules by the supervisor. Data for communication with elements of the DPAoutside a central processor will be kept in buffers set up by the supervisor andmaintained by the input/output processor programs.

6-1

SD 72-SA-0114-1

Space DivisionBy North American Rockwell

Since the programs will all be cooperative and essentially debugged, itis not certain how much protection will be necessary for the information inmemory. A certain amount of protection will be necessary for maintaining theintegrity of critical programs and data, and checks may be necessary for somereading and many writing operations between M1 and M2 memories to preventerrors from propagating. The supervisor will be involved in such security,but the division of these functions between hardware (to save time) and soft-ware (for flexibility) is yet to be determined.

The module control blocks will have at least the following informationfor the supervisor:

(a) Code name of the program module. Indication of whether it isa subroutine.

(b) Activation indicator. A set of n bits to allow the conditionalscheduling of this module by other modules or I/O operations.

(c) The number and identity of fixed-size data blocks required bythis module for variable storage and intermodule communication.

(d) Which data blocks may be released on completion of this module.

(e) Code names of the program modules, each with a correspondingactivation bit, which are to be successors of this module. Ifthis module is a subroutine, the name (return module) will beprovided by the module scheduling this subroutine. If a codename in (e) is that of a subroutine, another name must be pro-vided for the subroutine's return.

(f) Delay times. If the module to be scheduled is not time-dependent,this delay may be zero, implying it can be scheduled without hav-ing to wait for the passage of time.

The input/output (I/O) section of the central processor will be executingI/O programs in parallel with the arithmetic units. It will communicate withthe supervisor by means of I/O control blocks (I/OCB) which will contain atleast the following information:

(a) Identification of the source (input) or destination (output) ofthe information being transmitted and the route (DDB).

(b) The location and size of the buffer in M2 containing the inform-ation.

(c) An indication of the last word communicated (either a counter ora pointer to the buffer).

(d) Indications of any errors in the transmission, the numbers andsources of the errors.

(e) The name of the program module to be scheduled on completion ofthe I/O operation and activity and completion indicators.

6-2SD 72-SA-0114-1

Space Division9d • North American Rockwell

The I/OCB's will be initialized by the supervisor to start an I/O opera-tion. The I/O processor will maintain them from then until the data transmissionis completed or the supervisor terminates the operation. Certain I/OCB's will bepermanently scheduled to receive inputs that are initiated by elements of theMSS outside the DPA. Any error indications detected by the I/O processor willinitiate a recovery attempt which, if unsuccessful, will treat the error as afailure.

6.1.2.2 Performance Requirements

This section establishes the functions that must be performed by thesupervisor. These are divided into the four general areas as shown in Figure6-1. The performance requirements are detailed in Volume V, with only theimportant features discussed below.

Status Monitor. The supervisor must be aware of the current status of allDPA elements. A monitor program shall maintain status tables from which theresource allocation and scheduling programs can obtain the information necessaryfor their decisions. In addition, the monitor will alert the crew and/or othersubsystems of the MSS of any significant status changes that will affect stationoperations. A portion of the monitor shall be permanently scheduled on a peri-odic basis. It will perform checks on the hardware that is not automaticallytested (e.g., comparators, parity checkers and other testing circuits) or hasjust been entered into service (either a new module or one just repaired).Requests for particular responses will be sent to each element of the DPA(RPU's, RACU's, and the alternate central processor set) and the lack of therequired response within a prescribed time will be treated as an error. Inparticular, the operation and experiment processors must monitor each other sothat the experiment processor can take over station operation if the otherprocessor fails. Note that some of this system testing might be done withhardware.

Status Tables. Every in-flight replaceable unit (IFRU) in the DPA shallhave associated with it an entry that contains the following items to be main-tained by the monitor:

(a) Activity status (active or standby)(b) Functional status (functional, failed, under repair test)(c) Number of transient errors in a given period(d) Allowable transient errors in a given period(e) Time period for above (but only if different for different

IFRU's)

The supervisor shall respond to three kinds of requests for its services;

direct requests from active program modules, indirect requests from I/O proces-sor, and emergency requests through interrupts. The normal means for activationof the supervisor will be through a direct call by one of the active applicationsprogram modules. In the multiprocessing environment, there are three possibili-ties, and the processor receiving the supervisor call first must inhibit theother processor from also responding to a supervisor call until the activesupervisor has determined the situation. Having determined the situation andperformed the necessary checks, the supervisor will remove the calling module's

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MCB from the waiting list, reset its activation indicators, and perform thememory management, I/O and scheduling functions specified in the supervisorcall.

A program module releases a temporary data block when the information itcontains is not needed by any of its successors. The memory space for thisdata block becomes available to other modules. The supervisor shall keep alist of these available blocks and add to this list any released by a modulewhen it calls the supervisor. Those data blocks not released shall be retainedfor use by successor modules.

The major scheduling decisions will be built into the application pro-grams. Each program module will call for its successor(s) to be activated, andthe MCB for each program module will contain an activation indicator specifyinghow many (and which) modules will have to call for it before it is activated.Each subroutine module scheduled through the supervisor will have its successor(return) specified by the module that calls it. Input/output operations willbe treated as other program modules except their data blocks will be calledbuffers and their successors will be determined indirectly. Periodic modules,will, in addition, have a time delay inherent in their MCB's or set by othermodules.

The supervisor shall maintain an internal clock that will be periodicallysynchronized with an external clock (either part of the MSS or a time signaltransmitted by a ground station). In addition to the master clock, the super-visor shall provide interval timers for the various time intervals required bythe scheduler. These may be separate hardware countdown timers (noninterrupt-ing) or timers maintained by the supervisor by reference to a single countdowntimer. The supervisor shall also maintain countdown timers for the varioustesting functions required (e.g., program module timing, timing of responsesfrom other DPS or MSS elements, etc.).

The supervisor shall maintain a list of available resources, includingall elements of the DPA and time, and associate these resources with programmodules to assure efficient use of these resources in the execution of thefunctional applications programs. The monitor shall indicate whether a par-

ticular DPA element is operational. The resource allocator shall keep trackof which program modules on the waiting list require what resources and shallassign currently unassigned resources in such a manner as to make the mostefficient use of these resources. The resources to be allocated consist of:

time, processors, and data blocks for program modules; I/O processor, DDBchannels, RPU's, RACU's for I/O programs; and M2 or M3 memory space for pro-grams to be loaded or data to be saved.

The monitor and recorder functions shall maintain proper status history

records to support the resource allocation algorithms in both system degrada-tion and system recovery. Whenever there is a change in the operationalresources (an element fails or a repair element added), the resource allocation

algorithms must be aware of the event (through access to the monitor's statustables) and adapt accordingly. These algorithms will be sensitive to thesequence of events as well as the current status and must adapt in such a

manner as to:

6-5SD 72-SA-0114-1

9 s North American Rockwell

(a) Guarantee crew safety and MSS integrity(b) Support critical MSS functions(c) Guarantee proper operation of the DPA(d) Support the experiment data processing

The supervisor shall keep track of available memory data blocks. If anyof the program modules in the waiting list require the allocation of data blocks,the available data blocks shall be distributed among them in the most efficientmanner. All program modules on the waiting list are automatically ready forexecution if they need no additional data blocks. Those program modules on thehighest priority waiting list shall be allocated data blocks first, if there areenough available to make them ready. The allocation algorithm shall avoid thedeadlock problem of partial allocation to several programs from a limited avail-ability list.

The supervisor shall allocate the I/O processor to a particular I/O opera-tion by activating the associated IOCB. The I/O processor shall maintain itsown scheduling and timing by reference to the active IOCB list. Buffers willalready have been allocated for I/O by the modules which scheduled the I/O; thedata blocks allocated to those modules become the bpffers for the I/O processor.The I/O processor will take care of all the I/O error detection and recovery.

The supervisor shall provide for integrating all working elements of theDPA into a working system and to isolate all failed elements in a manner thatwill not adversely affect other subsystems of the MSS. This implies theability to bring the system into operation from a cold start as well as accept-ing the replacement of a repaired IFRU that had previously failed, or a newIFRU to allow modular expansion of the system. The isolation of an elementapplied in the proper sequence to all elements allows safe shutdown of theentire system. These functions will require some assistance from the hardwareand, in fact, the DPA is designed to take much of the burden from the super-visor software.

Data Base Requirements. The amount and format of the supervisor's database is not yet determined, but the following items shall be included.

(a) Status tables. A table showing the status of each element inthe DPA shall be maintained.

(b) Module control blocks. A table describing each software modulein the program system shall be maintained. Each entry in thistable shall consist of a module control block. Either copiesof or points to MCB's shall be maintained in a waiting list inpriority queues for all modules scheduled and waiting for exe-cution.

(c) I/O control blocks. A table describing each I/O process shallbe maintained. Each entry in this table shall consist of anI/O control block. Either copies of or pointers to IOCB'sshall be maintained in an active I/O list for communication withthe I/O processor.

6-6SD 72-SA-0114-1


(d) Data blocks and buffers. The data blocks and buffers (whichmay be interchangeable, the name applied implying use by aprogram module or an I/O program) are properly part of theapplications programs; but the supervisor shall maintain alist of pointers to all data blocks/buffers with an indica-tion for each whether or not it is allocated to a programmodule or I/O program.

The supervisor shall be coded in machine or assembly language. This willassure the maximum efficiency in the use of the data processor's features toattain speed of execution and completeness of error checking. The requirementsfor change in such a program are less extensive than those for applications pro-grams, therefore a higher order language does not offer as much advantage.Also, many of the executive functions are highly machine dependent, which makeshigher order languages, in general, unsuitable.

The supervisor is unique in that it can include features to aid in test-ing not only itself, but also all other program modules. Some of the errordetection, status monitoring, data recording, and memory protection featuresincluded in the executive can be expanded to aid in program bug detection.These features can be useful in the development of the supervisor itself, butwill be even more useful in the development of the application programs. Thedebugging features of the supervisor should therefore be developed early anddesigned in such a manner as to be easily removable or reducible. Thus, theywill not use up time and memory overhead as the system becomes operational andthe debugging and testing features can be left on the ground.

6-7SD 72-SA-0114-1


7.0 RECOMMENDATIONS FOR UTILIZATION OF ADTACCOMPLISHMENTS

It was indicated in the introduction that the present ADT effort does notcomplete the definition of the MSS information subsystem, and that future stud-ies and evaluations would be needed to define the equipment and software speci-fications. There is, however, much that can be learned by using the presentbreadboards and studies. Table 7-1 lists the current ADT accomplishments asreported in this document.

Table 7-1. Current ADT Accomplishments

Communications terminal MSS - Representative K-band ElectronicsCommunication System Specification

Digital data bus MSS - Representative cabling configuration10 x 106 bit/sec capabilityIntegrated with RACU, RPU, DBCU, and test

processor (DACS)

Data processor DPA System Specification and DPA SupervisorySpecification

Bulk memory technology evaluationMSS subsystem support requirements definitionMemory and internal traffic studies

Software DPA throughput simulationData organization studiesSoftware standards and conventionsProcessing flow charts (subsystem support)

Table 7-2 indicates the possible utilization of the equipment breadboardsfor (1) stand-alone testing of the design concepts, and (2) combined testingfor defining interface and integration requirements. Stand-alone testing wouldbe accomplished using laboratory and simulated environments and situations todetermine the strengths and/or shortcomings of these particular breadboardequipments for certain applications. It should be emphasized that these equip-ments, while developed to demonstrate MSS concepts, are by no means limited in

application to that vehicle. The shuttle, sortie modules, RAM (and certainunmanned satellites) and ground-support installations can certainly be influ-enced and benefit from these evaluations.

A second point of emphasis is that the NR-MSC breadboards are functional

and performance duals with the McDAC-MSFC breadboards, and that the implementa-

tion approach (mechanization) is different in both cases (DACS and CTB). Thereis an excellent opportunity to conduct parallel, comparative tests, using the

same conditions and procedures on the similar equipments. The purpose would

7-1SD 72-SA-0114-1

Space Division•s~ North American Rockwell

Table 7-2. Utilization of Results

PERFORMANCE AND INTEGRATED EVALUATIONS USING CURRENT BREADBOARDS

K-BAND ELECTRONICSI CURRENT HARDWARE BREADBOARDS

DATA ACQUISITION/CONTROL

Design Concept and Performance Testing to Determine:

Equipment and assembly performanceThermal and thermal/vacuum environment effectsFault detection and reconfiguration control operating limitsRedundancy and error protection features

Refinement of System Specification

Development of OBCO Software Requirements

Development of Integrated System Test Plan

System Evaluations Using Augmented BreadboardsIntegration tests to determine:

Communications terminal plus DACSECLSS subsystem breadboard plus DACS OBCO parameters and proceduresSolar panel prototype plus DACS Automation algorithmsRemote processor plus G&C Develop interface specifications

Experiment Technology Investigations

DACS plus experiment sensors Experiment sensor monitoring,(simulated or prototype) control, automation, data flow,

data forms, rates, quantities

Man-Machine Technology Investigations

DACS plus console plus subsystem Subsystem fault isolationbreadboards Communication scheduling/control

Vehicle power managementSubsystem configuration control

Payload Technology Development

DACS plus console plus experimentor Experimentor data "quick-look"sensors and editing

Experimentor scheduling/controlSensor configuration/data quality

7-2

SD 72-SA-0114-1


not be to "prove" which was best, but to determine which features are mostapplicable to given situations. From this additional knowledge the equipmentand interface specifications for flight hardware (shuttle, sortie, RAM) can bedeveloped with assurance.

Combined testing of these breadboards and other equipment developmentswould have even more beneficial results. No spacecraft subsystem is independ-ent of other subsystems, and very certainly, it is the data and control systemthat links them together. Automation of many spacecraft functions requirethat certain parts of conventional subsystems must operate cooperatively andthis will have considerable influence on the design requirements for theseequipments. Again, it is the DACS/DMS capabilities that are needed to augmentthe interaction. Using the DACS breadboards as a "test bed" results in muchuseable knowledge being obtained to develop the vehicle system specifications.

Even more useful is the ability to use DACS or the DMS to investigate therole of the crew to manage the vehicle, its operations, and the related exper-iment operations. The present DACS, together with a console (not part of ADT)provides a flexible, efficient test bed by which to develop the software anddisplay formats needed for a man-directed information system. It has beenreiterated on numerous occasions that the DPA software, and the crew-interactiveprocedures, are the least well-defined and most difficult of all the ISS defin-ition requirements. Figure 7-1 indicates that the next phase of the IMS ADTprogram should consider developing the man-machine interface (console and port-able control unit), and continue the software development in terms of languages,algorithms (particularly for automation of other subsystems), and extend thestudies to allocate functions to the different elements of the total informa-tion management system. Space Division Report, SD 71-240, "Information Manage-ment Advanced Development Technology Extension Plan," (1 October 1971) expandsthe details of the recommended actions.

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Documents

space station - ntrs.nasa.gov