• Title of project:

– Special Manpower Development Project in VLSI Design & Related Software, SMDP-VLSI Phase-2 (Dept. of ECE, MNIT Jaipur)

• Amount sanctioned:

– Appx. 12 Lakhs/yr; 78 Lakhs total

• Date of award, period: Dec. 2005, 2006-2013

• Funding agency:

– Ministry of Comm. & IT, Govt. of INDIA (MoCIT)

• Partner institute if any: None

• Names of PI, Co-PIs:

– PI/Co-PI: Dr. Vineet Sahula, Dr. D. Boolchandani

– Members: Dr. L. Bhargava, Dr. C. Periasamy

• Objective(s): Manpower training

• Key deliverables: Designs, Chips, trained manpower (UG/PG)

• Major equipment purchased:

– Embedded SW; Logic Analyzer (in process- TEQIP); FPGA/SoC boards

– Xilinx boards & others provided as grant-in-aid as Synopsys, Cadence CAD SW (MoCIT, Govt. of INDIA)

• Importance to society/country (2-3 bullets)– IT Hardware, trained manpower

– Design/product possibility of prototyping electronic hardware

– Emerging as research/development centre in a specific area- Analog Synthesis; System level design/modeling; Low energy

electronic systems’ prototyping

• Major innovation, if any– Proposed Analog macromodels

– Proposed SoC communication modeling approach

– A chip designed at MNIT Jaipur & fabricated at IMEC Belgium; tested in house at MNIT Jaipur

• Patent filed, if any

• Photograph of set up/product developed

• Snapshot of key analysis (for theoretical projects)– Proposed Analog macromodels, variability aware accurate models for analog synthesis

– Proposed SoC communication modeling approach, with analytical solution to solve Markov/GSMP models

• Main result (s), outcome– Trained manpower- 05 PhDs; 200+ MTechs; 50 BTechs

– Design/fabricated Hamming CODEC chip

• Publications from project– 20+ Journal and 50+ refereed conference papers

Special Manpower Development Project in VLSI Design & Related

Software, SMDP-VLSI Phase-2

PI/Co-PI: Dr. Vineet Sahula, Dr. D. Boolchandani,

Members: Dr. L. Bhargava, Dr. C. Periasamy

Dept. of ECE, MNIT Jaipur

Funded by: Ministry of Comm. & IT, Govt. of INDIA (MoCIT)

2006-2013

Equipment/Software acquired in Grant-in-aid from MoCIT

(centrally purchased by CEERI, Pilani for IITs/NITs)

• Servers/workstations-

– high end servers/workstations provided in grant-in-aid by MoCIT

– 3 servers+ 9 workstations

• Industry standard CAD tools-suites

– Synopsys, Cadence, Xilinx, Magma, Mentor Graphics,

Equipment/Software purchased/acquired by MNIT Jaipur

• 20 desktops, WIPRO provided by institute (MNITJ)

• Analog/RF design suite from AGILENT under TEQIP

• Embedded design Software– Granted by ARM company, Bangalore

– Granted by Texas Instruments, Bangalore

• Xilinx boards- Vertex-7 and Z-7000 Purchased under TEQIP

• ARM based CORTEX-M boards purchased under TEQIP as well as in grant-in-aid from ARM Inc.

• Texas Microcontroller boards as grant-in-aid from Texas Instruments, Bangalore

Journal Papers Published

• More than 20 in refereed/indexed journals

Journal Papers PublishedIndexed & reputed (IEEE, IET, Springer, SPIE etc.)

1. M PRASAD, V SAHULA, V. K. Khanna. ZnO etching and microtunnel fabrication for high-reliability MEMS acoustic sensor, IEEE

Transaction on Devices & Materials Reliability, 2013 (Early access). TDMR-2012-10-0098

2. Patil, V. Sahula and A. S. Mandal. Features classification using geometrical deformation feature vector of support vector machine

and active appearance algorithm for automatic facial expression recognition, Springer's Journal of Machine Vision and Application,

(accepted), 2013.

3. Lokesh garg and V. Sahula. Efficient CMOS subthreshold leakage analysis with improved stack based models in presence of

parameter variations, IET Electronic Letters, 2013. Print: 0013-5194, Online: 1350-911X

4. J B Sharma, K K Sharma, Vineet Sahula. Digital image dual watermarking using self-fractional fourier functions, bivariate

empirical mode decomposition and error correcting code, Journal of Optics, Pages 1-14, Springer-Verlag, 2013. ISSN: 0972-8821

(print version), ISSN: 0974-6900 (electronic)

5. M PRASAD, V SAHULA and V. K. Khanna.Design and fabrication of Si-diaphragm, ZnO piezoelectric film-based MEMS acoustic

sensor using SOI wafers, IEEE Transactions on Semiconductor Manufacturing, 2013, vol. PP, no. 99. ISSN: 0894-6507

6. Rajesh A. Patil ; Vineet Sahula ; Atanendu S. Mandal. Features classification using support vector machine for a facial expression

recognition system, Journal of Electronic Imaging, 21(4), 043003 (Oct 01, 2012). doi:10.1117/1.JEI.21.4.043003, ISSN: 1017-

9909, E-ISSN: 1560-229X

7. M PRASAD, R P YADAV, V SAHULA and V. K. Khanna. Controlled Chemical Etching of ZnO Film for Step Coverage in MEMS

Acoustic Sensor, IEEE Journal of micro-electro-mechanical systems, 2012, vol. 21, no. 3, pp. 517-519. ISSN: 1057-7157

8. D. Boolchandani, Lokesh Garg, Sapna Khandelwal, and Vineet Sahula. Variability aware SVM macromodel based design

centering of analog circuits, Springer’s Journal on Analog Integrated circuits & signal processing, October 2012, Volume 73, Issue

1, doi:10.1007/s10470-011-9799-y, pp 77-87. ISSN: 0925-1030 (print version) ISSN: 1573-1979 (electronic version)

9. M. Prasad, R. P. Yadav, V. Sahula and V. K. Khanna. FEM simulation of platinum-based microhotplate using different dielectric

membranes for gas sensing applications, Sensor Review (Journal), Volume: 32 Issue: 1 2012, pages 59-65 – emeraldinsight.com.

ISSN: 0260-2288

10.D. Boolchandani, Abrar Ahmed, and V. Sahula, Efficient kernel functions for support vector machine regression model for analog

circuits’ performance evaluation, Springer’s Journal on Analog Integrated circuits & signal processing, Volume 66, Number 1,

January 2011 , pp. 117-128(12). ISSN: 0925-1030 (print version) ISSN: 1573-1979 (electronic version)

Journal Papers PublishedJournals- others

1. Namita Sharma, Vineet Sahula, C. P. Ravikumar. Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation, International Journal of Advanced Studies in Computers, Science and Engineering, vol. 1, issue-4, pages 33-39, ISSN 2278-7917, 2012.

2. Mahanth Prasad, Robin Bhateja, R.P. Yadav, V. Sahula and V.K. Khanna. A Novel Design and Mathematical Model for Sensitivity of a MEMS based Piezoelectric Acoustic Sensor, International Journal of Applied Engineering Research, Volume 6, Number 18 (2011) special issues, pp. 2211-2216. Print ISSN 0973-4562, Online ISSN 1087--1090

3. Mahanth Prasad, R. P. Yadav, V. Sahula and V. K. Khanna. Design and Simulation of Double-spiral Shape Micro-heater for Gas Sensing Applications, Sensors & Transducers Journal, Vol. 129, Issue 6, June 2011 pp.135-141. ISSN: 2306-8515, e-ISSN 1726-5479

4. D. Boolchandani, and V. Sahula, Efficient Kernel Functions for Support Vector Machines based feasibility classification for Analog Circuits macromodeling, Journal of Design, Analysis and Tools for Integrated Circuits and Systems (IJDATICS), July 2010, VOL. 1, NO. 1, JUNE 2011 (full-text-pdf). ISSN: 2071-2987

5. U. Deshmukh and V. Sahula. Performance evaluation of Arbitration schemes of bus-based communication architectures based on Interactive Generalized Semi Markov Process Model (IGSMP). International Journal of Simulation- Systems, Science and Technology - IJSSST: Vol. 11, No. 3, May 2010, ISSN 1473-804x Online, ISSN 1473-8031 Print. ISSN 1473-804x Online, ISSN 1473-8031 Print

6. C. Periasamy and P. Chakrabarti, “Effect of temperature on the electrical characteristics of nanostructured n-ZnO/p-Si heterojunction diode,” Journal of Science of Advanced Materials, Vol.5, pp-1384-1391 (2013).

7. Runa Chakrabarti and C.Periasamy “Comparative Study on Structural and Optical Properties of Nanostructured ZnO Thin films Grown by Thermal Evaporation andSol-gel Techniques." Journal of Materials Focus. Vol.2, pp-392-398 (2013).

8. Aniruddh Bahadur Yadav, C. Periasamy, P. Chakrabarti,S. Jit, “Hydrogen Gas Sensing Properties of Pd/NanocrystallineZnO Thin Films Based Schottky Contacts at Room Temperature” Advanced Science, Engineering and MedicineVol.5, No 2, pp. 112-118, 20131

9. Aniruddh Bahadur Yadav, C.Periasamy, P.Chakrabarti and S.Jit, “Room- Temperature Hydrogen Gas Sensing Properties of Pd/ZnO Thin Films Grown on n-Si Substrates by Thermal Evaporation and Sol-Gel Techniques: A Comparative Study” Indian Journal of Pure & Applied Physics (IJPAP). (In Press)

Conference Papers Published with support of SMDP-VLSI Lab

• More than 60 in refereed conferences

• More than 30 in other conferences/workshops

Refereed Conference Papers in 20131. Mahanth Prasad, V. Sahula and V. K. Khanna. Design and fabrication of Si-diaphragm for ZnO-based MEMS

acoustic sensor, 17th International Symposium on VLSI Design and Test, 2013, Jaipur (poster).

2. Saima Cherukat and V. Sahula. Process Variation Tolerant SRAM Design for Ultra Low Power Applications, , 17th

International Symposium on VLSI Design and Test, 2013, Jaipur.

3. Nupur Navlakha, Lokesh Garg, Dharmendar, Vineet Sahula. Architectural Level Models for Subthreshold Leakage

Power Estimation of SRAM Arrays with its Peripherals, 17th International Symposium on VLSI Design and Test,

2013, Jaipur.

4. Mahesh Soni and V. Sahula. Power Delay Product Optimal Design of Ternary ALU using Carbon nanotubes, All

India Conference on “Global Innovations in Computer Science & Engineering and Information Technology”

being organized during April 12 -13, 2013 at AICON-2013, Durg.

5. R. Kumawat, V. Sahula, M. S. Gaur. Probabilistic Modeling Approaches for Nanoscale Devices, International

conference on circuit, power and computing technologies ICCPCT-2013, 21-22 March 2013, Kumaracoil, TN,

India.

6. R. Kumawat, V. Sahula, M. S. Gaur. Reliable circuit analysis and design using nanoscale devices, International

Conference on Communication and Electronics System Design, Jaipur, Jan. 2013, Proc. of SPIE Vol. 8760

87602C-1, doi: 10.1117/12.2012516.

7. Shashikant Sharma and C. Periasamy and Manisha Pattanaik and Balwinder Raj “Activation Noise Aware Ultra

Low Power Diode Based Multi-Threshold CMOS Technique for Static CMOS Adders” International Conference

on Microelectronics Communication & Renewable Energy, Kerala, 4-6 June 2013. Published in IEEE Xplore.

8. Shashikant Sharma, C. Periasamy and P. Chakarbarty," Numerical Study and Analysis of n-ZnO/p-Si

Heterojunction Based UV-Visible Photodetector", IEEE International Conference on Control, Computing,

Communication and Materials (ICCCCM-Aug-3-4, 2013), Allahabad, India. Best paper award.

Refereed Conference Papers 2010-20121. Lokesh garg and V. Sahula, Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage

power , International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD),

Spain 19-21 Sept. 2012, Seville, Digital Object Identifier: 10.1109/SMACD.2012.6339387 , PAGES 253-256.

2. Mahesh Soni, R. Kumawat, V. Sahula and M. S. Gaur. Reliability Evaluation of Redundancy based Fault Tolerant Techniques at Nanoscale,

Reliability Aware System Design and Test, Hyderabad, January 7-8, 2012.

3. R A Patil, G Gupta, V Sahula and A. S. Mandal. Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration,

25th IEEE International Conference on VLSI Design, (VLSID), 2012 INDIA, Digital Object Identifier: 10.1109/VLSID.2012.47 , pages 62-67.

4. Mahanth Prasad, R. P. Yadav, V. Sahula, V. K. Khanna. Design and mathematical model of a ZnO-based MEMS acoustic sensor, Proc.

SPIE Proceedings on 16th International Workshop on Physics of Semiconductor Devices, Kanpur, Volume 8549, December 19-22, 2011;

doi:10.1117/12.925318.

5. Mahanth Prasad, R. P. Yadav, V. Sahula, V. K. Khanna. Design and simulation of Pt-based microhotplate, and fabrication of suspended

dielectric membrane by bulk micromachining, Proc. SPIE Proceedings on 16th International Workshop on Physics of Semiconductor

Devices, Kanpur, Volume 8549, December 19-22, 2011; doi:10.1117/12.925318.

6. D. Mathur, S. K. Bhatnagar and V. Sahula, LTCC Technology for Wireless System in Package Architecture: Issues & Challenges, IMAPS

System-level package workshop, Dec. 2011.

7. Patil, R.A.; Sahula, V.; Mandal, A.S., Facial Expression Recognition in Image Sequences Using Active Shape Model and SVM, Fifth IEEE

UKSim European Symposium on Computer Modeling and Simulation (EMS), Digital Object Identifier:10.1109/EMS.2011.25, Year 2011 ,

Page(s): 168 – 173. (presented at CimSim, Langkawi, Malaysia, Sept. 2011).

8. Rajesh A Patil, V Sahula, AS Mandal. Automatic detection of facial feature points in image sequences, International Conference on Image

Information Processing (ICIIP), 2011, Digital Object Identifier: 10.1109/ICIIP.2011.6108957 , pages 1-5.

9. R A Patil, V Sahula, A S Mandal. Bayesian versus support vector machine based approaches for facial feature classification in image

sequences, IEEE International Conference on Computer and Communication 2011 India, (ICCCT), Digital Object Identifier:

10.1109/ICCCT.2011.6075168 , Pages 174-179.

10. D Mathur, S K Bhatnagar, V Sahula, Nondestructive method for measuring dielectric constant of sheet materials, TENCON 2011 IEEE

Region 10 Conference, Digital Object Identifier: 10.1109/TENCON.2011.6129282 , pages 1105-1109.

Conference Papers 2010-2012 …11. Alok Sharma and V. Sahula. Reconfiguration approaches for power aware prototyping: Case study of ATM cell assembler,

National Conference on VLSI Design, CEERI Pilani, India, 12-14 Oct. 2011.

12. Lokesh Garg, Pramod Khandelwal, D. Boolchandani and V. Sahula. Improved sampling methodology for variability aware sizing of analog circuits, National Conference on VLSI Design, CEERI Pilani, India, 12-14 Oct. 2011

13. R A Patil, V Sahula, A S Mandal. Automatic recognition of facial expressions in image sequences: A review, IEEE International Conference on Industrial and Information Systems (ICIIS), 2010, India, Digital Object Identifier: 10.1109/ICIINFS.2010.5578670 , pages 408-413.

14. D. Boolchandani, Lokesh Garg, Sapna Khandelwal and Vineet Sahula. Variability Aware Yield Optimal Sizing of Analog Circuits using SVM-Genetic Approach, XIth IEEE International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, Tunisia 4-5 Oct. 2010, Digital Object Identifier: 10.1109/SM2ACD.2010.5672332, pages 1-6.

15. U. Deshmukh, Prafull Agarwal and V. Sahula, Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture, IEEE Computer Society International Symposium on VLSI, Kefalonia, Greece, 5-7 July 2010.

16. P K Jha, V Sahula. Omnipotent and mortal training of a nanocell model to emulate the functionality of a logic gate, India Conference INDICON, 2010, Digital Object Identifier: 10.1109/INDCON.2010.5712699 , pages 1-6.

17. R. Patil, A. S. Mandal and V. Sahula, “Automatic facial expression recognition: A Review”, IEEE International Conference on Industrial and information systems (ICIIS), NITk Surathkal, July 2010.

18. R. Kumawat, V. Sahula, M. S. Gaur and V. Laxmi, Modeling and Reliability Evaluation of logic Circuits at Nanoscale, RASDAT Workshop (co-located with VLSI Design Conf.), January 7-8, 2010.

19. D. Boolchandani et al., Chaotic Neural Dynamics as evinced from scalp electroencephalography (EEG) 13th Congress of the European Federation of Neurological Societies (EFNS) ITALY European Journal of Neurology, / 2009

20. D. Boolchandani et al., D-MANAV : An Electronic Device for Unmanned Railway Crossing. IETE Journal of Education India 49, Issue3, pp 89-94 / 2008

PhD Theses Completed/Continuing

• 4 Theses completed

• 10 are continuing

PhD Theses Titles-Dr. Vineet Sahula as Supervisor

Name of the

candidate

Title of the thesis Year

completed

Ulhas

Deshmukh

On Performance Evaluation of SoC Communication Architectures 2010

D.

Boolchandani

On Macro Modeling of Analog Circuits Using Support-Vector-Machines (SVMs)

With Efficient Kernels

2011

Mahanth

Prasad

Design, Process Development and Characterization of ZnO-Based MEMS

Acoustic Sensor (jt pupervisor- Dr. V. K. Khanna)

2013

Dhirendra

Mathur

Investigations of New Approaches of Design and Applications of Microstrip

Patch Antennas for System-on-Package Applications and Implementation of a

2.45GHz

Rectenna Circuit

2013

(submitted)

Jankiballabh

Sharma

Novel approaches for watermarking images & application to image fusion: Use

of self-fractional Fourier transforms

2013

Rajesh A. Patil Algorithms for Machine Vision and Their Hardware/software Implementation Continuing

Renu Kumawat Nano-Scale Reliable Memory Architectures Continuing

Lokesh Garg Variability Aware System Level Design Continuing

Lintu Rajan Algorithms & Architectures for Cognitive Computing Continuing

PhD Theses Titles-Dr. D. Boolchandani as Supervisor

Name of the

candidate

Title of the thesis Year

completed

Seema Yardi Lab on Chip : Detection of Pathogen From Body Fluid/water/food Using

Optical Sensing

Continuing

Tarun Varma Fabrication and Characterization of Zinc Oxide Thin Film for Opto

Electronic Device Applications.

Continuing

Vimal Agrawal Photonic Integrated Circuits Continuing

Sapna

Khandelwal

Reliability and Process Aware SVM Based Macro Models for Analog

Circuits

Continuing

Yashwant

Singh

Design of Low Leakage SRAM Circuits With Improved Yield and

Reliability

Continuing

PhD Theses Titles-Dr. C. Periasamy as Supervisor

Name of the

candidate

Title of the thesis Year

completed

Shahikant Design, Fabrication and Characterization of Nanostructured ZnO Thin Film

Based Electronic Devices.

Continuing

MTech Theses Completed/Continuing

• About more than 200 theses completed since 2005 MTech VLSI Design programme started

• Currently, 30 theses students are continuing as full time; appx. 5 as part time

Select MTech Theses Titles-Dr. V. Sahula as Supervisor

Name of the candidate Title of the thesis Year

completed

Amit Kumar Secondary effects in nanoscale devices 2012

Anuj Solanki Variability aware Memory yield enhancement 2012

Mahesh Soni Memory synthesis using nanodevices 2012

Rajesh Sahu Analog synthesis into nanometer 2012

B. Gopikrishna Design & Verification of Mobile High definition Link Interface 2013

A. Mallikarjuna

Reddy

IMPLEMENTATION OF eMMC 5.0 FEATURES FOR THE MOBILE

STORAGE IP

2013

Ramesh Kumar Design an Ultra Low Power Low Phase Noise Lc Voltage Controlled

Oscillator

2013

K. Swaraj Gowtham Efficient utilization of power in a Phase-Locked Loop Design 2013

Saima Cherukat Modeling and Design in Ultra Deep SubMicron Technology- (a) Variation

robust ultra low power Novel SRAM Cell (b) Proposing Models and order

reduction of models for SoC interconnects

2013

Select MTech Theses Titles-Dr. D. Boolchandani as Supervisor

Name of the candidate Title of the thesis Year

completed

Monika Katta Power optimization of Analog circuits using Geometric

Programming.

2012

Yashwant Singh Design of Low Leakage SRAM Circuits. 2012

Pramod

Khandelwal

Exploration of Sampling Methods

for Accurate Analog Behavioral Model.

2012

Shivani Yadav Modeling and Simulation of

CMOS Logic Circuits Using ANN & ANFIS

2012

Select MTech Theses Titles-Dr. L. Bhargava as Supervisor

Name of the candidate Title of the thesis Year

completed

Vidhi Agrawal Hardware Implementation of binary LDPC Encoder 2012

Ashish Sharma Hardware Implementation of binary LDPC Encoder 2012

Noor-Ul-

Mustafa

Hardware Implementation and Performance Analysis of Non

Binary LDPC Decoder

2012

Select MTech Theses Titles-Dr. C. Periasamy as Supervisor

Name of the

candidate

Title of the thesis Year

completed

Mr. Nannepamula

SureshGround Bounce Noise aware Forward Body Biased MTCMOS

Circuit Techniques for Combinational Circuits

2013

G.Gnanadeep

ReddyA Power Efficient High Performance Flip Flop Design Using

Conditional Pulse Enhancement Technique

2013