SPICE OrCAD WinSPICE Fuller.ppt - RIT - Peoplepeople.rit.edu/lffeee/SPICE_OrCAD_WinSPICE_Fuller.pdf · 2-9-2010 SPICE_OrCAD_WinSPICE_Fuller.ppt. SPICE Examples OUTLINE Introduction

SPICE Examples

ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING

SPICE Using OrCAD PSPICE, WINSPICE or LTSPICE

Dr. Lynn FullerMicroelectronic Engineering

Rochester Institute of Technology

© February 9 2011 Dr. Lynn Fuller Page 1


Microelectronic Engineering

Rochester Institute of Technology82 Lomb Memorial DriveRochester, NY 14623-5604

Tel (585) 475-2035Fax (585) 475-5041

Dr. Fuller’s Webpage: http://people.rit.edu/lffeeeEmail: [email protected]

Dept Webpage: http://www.microe.rit.edu

2-9-2010 SPICE_OrCAD_WinSPICE_Fuller.ppt

SPICE Examples

OUTLINE

IntroductionWinSpiceOrCAD PspiceLT SPICESimple ExampleDevice ModelsComparion of 1st, 2nd and 3rd Generation Models




Comparion of 1 , 2 and 3 Generation ModelsFamily of Curves, Id-Vgs, Sub-Vt

Verification of Resistor and Capacitor ValuesRing Oscillator Gate Delay td

Circuit ExamplesTwo Phase ClockOp Amp

SPICE Examples

INTRODUCTION

SPICE (Simulation Program for Integrated Circuit Engineering) is a general-purpose circuit simulation program for non-linear DC, non-linear transient, and linear AC analysis. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, transmission lines, switches, and several semiconductor devices: including diodes, BJTs, JFETs, MESFETs, and MOSFETs. Circuits with large numbers




BJTs, JFETs, MESFETs, and MOSFETs. Circuits with large numbers of all types of components can be simulated.

SPICE input files and output files are simple text files (e.g. name.txt)

Input files include a TITLE, circuit description NET LIST, analysis directives (COMMANDS), and lists of other text files to include (INC) such as model libraries (LIB) and an END command.

SPICE Examples

INTRODUCTION

PSpice Lite 9.2 is one of the OrCAD family of products, from Cadence Design Systems, Inc., offering a complete suite of electronic design tools. It is free and includes limited versions of OrCAD Capture, for schematic capture, PSpice for analog circuit simulation and Pspice A/D for mixed analog and digital circuit simulation. PSpice Lite 9.2 is limited to 64 nodes, 10 transistors, two operational amplifiers and 65 primitive digital devices. See page 35 (xxxv) of the PSpice Users Guide.




LT SPICE – is a free SPICE simulator with schematic capture from Linear Technology. It is quite similar to PSpice Lite but is not limited in the number of devices or nodes. Linear Technology (LT) is one of the industry leaders in analog and digital integrated circuits. Linear Technology provides a complete set of SPICE models for LT components.

WINSPICE – is a low cost fully capable SPICE simulator for windows computers. The full version is approximately $75. It does not include a schematic editor. (but

schematic editors are available from third party software providers)

SPICE Examples

EXAMPLE OF SIMPLE SPICE INPUT FILE

DR FULLER - SIMPLE EXAMPLE TITLE* THE FIRST LINE IS THE TITLE* LINES THAT START WITH * ARE COMMENT LINES AND DO NOTHING* UPPER AND lower case text ARE TREATED THE SAME* CIRCUIT IS DESCRIBED BELOW (NET LIST)R1 1 2 3K ; resistor R1 between node 1 and zero has value 2000 ohmsR2 1 0 2KVS 2 0 DC 5 ; Voltage source V1 is a DC source of 5 volts*




** REQUESTED ANALYSIS (DIRECTIVES OR COMMANDS).DC V1 0 5 .1 ; find all node voltages and branch currents for V1 starting at 0 and * incrementing by 0.1 volts ending at 5 volts.PLOT DC V(1)**.INCLUDE File_name.txt ;(none for this example)*.END

SPICE Examples

CREATING THE INPUT FILE

The input file can be generated from a schematic capture program, or just typed in a text editor such as “Notepad” or “WordPad”

Simple Resistor DividerR1 1 2 3KR2 2 0 2K

R1

3K2 1




R2 2 0 2KVS 2 0 DC 5.DC VS 0 5 0.1 .PLOT DC V(1).END

0

5V

VS

R2

2K

+

-

SPICE Examples

WINSPICE3

WinSpice3 is a general-purpose circuit simulation program for non-linear DC, non-linear transient, and linear AC analyses. Circuits may contain resistors, capacitors, inductors, mutual inductors, independent voltage and current sources, four types of dependent sources, lossless and lossy transmission lines (two separate implementations), switches, uniform distributed RC lines, and the five most common semiconductor devices: diodes, BJTs, JFETs, MESFETs, and MOSFETs.

It can be downloaded and installed onto personal computers at http://www.winspice.com . When the full version v1.05.01 is installed, it should




http://www.winspice.com . When the full version v1.05.01 is installed, it should be updated to v1.05.07, which is the latest version available for now.

WinSpice basically Spice3F4 for Windows 32bit systems. However, it contains several enhancements over the original Berkeley Spice3F4.

WinSpice iteself does not contain a schematic editor (capture/edit). However, 3rd part schematic editors can be linked to WinSpice. A schematic editor which uses WinSpice for its simulation engine is available at http://www.5spice.com/. These editors provide a convenient way to draw a schematic and create a net list.

SPICE Examples

RUNNING WINSPICE

Once WinSpice is installed click on your shortcut or start WinSpice from the start programs menu.

A dialog box and WinSpice -> prompt should appear.

Type source path_to_your_input_file.txt Press Enter

SPICE will run




SPICE Examples

OrCAD PSpice Lite 9.2

PSpice Lite 9.2 is one of the OrCAD family of products offering a complete suite of electronic design tools. These products are available from Cadence Design Systems, Inc. PSpice Lite 9.2 includes limited versions of OrCAD Capture, for schematic capture, PSpice for analog circuit simulation and Pspice A/D for mixed analog and digital circuit simulation. PSpice Lite 9.2 is limited to 64 nodes, 10 transistors, two operational amplifiers and 65 primitive




analog and digital circuit simulation. PSpice Lite 9.2 is limited to 64 nodes, 10 transistors, two operational amplifiers and 65 primitive digital devices. See page 35 (xxxv) of the PSpice Users Guide.

SPICE Examples

BEFORE YOU START

It might be good to set up some folders for your SPICE projects

C:/SPICE

Other FilesI put a SPICE folder on my C:/ drive




Models

Project1

Project N

and created sub folders for projects,

models and other files, etc.

SPICE Examples

START SCHEMATIC CAPTURE OrCAD PSpice Lite 9.2

Start >Programs>Orcad Family Release 9.2 Lite Edition>Capture Lite Edition




SPICE Examples

OPEN A NEW BLANK PROJECT OrCAD PSpice Lite 9.2

Select New>Project

Give it a name

Select Analog or Mixed A/D




Browse to the folder location

you set up

Select create a blank project

SPICE Examples

CREATE SCHEMATIC OF THE CIRCUIT OrCAD

PSpice Lite 9.2

Place Parts

Place Wires

Place Ground use 0/Source symbol




Place Ground use 0/Source symbol

Label Nodes

Add Probes

Change Names of Devices

Change Device Properties

Show Name and Value, etc.

Note: SPICE requires one node to be labeled zero, either place a ground symbol labeled

zero or use node label N1 icon alias = 0 (then you do not need a ground symbol)

SPICE Examples

RC DIVIDER CIRCUIT

3V

R1

20K

VC

+

R2

10K

Calculate VC

Change the battery to a 3 volt

step function and plot VC




0

-

10K step function and plot VC

versus time.

Change the battery to a

sinusoidal voltage source and

sketch VC versus frequency

SPICE Examples

DC SPICE ANALYSIS OrCAD PSpice Lite 9.2




SPICE Examples

TRANSIENT ANALYSIS OrCAD PSpice Lite 9.2




SPICE Examples

AC ANALYSIS OrCAD PSpice Lite 9.2




SPICE Examples

MOSFET, BJT AND DIODE MODELS

Orcad PSpice has many model libraries that can be included with a SPICE input file. You could also create your own models as a simple text file and include that file with a SPICE input file for either PSpice or WinSpice.

In SPICE a transistor is defined by its name and associated properties and its model. Its name and associated properties is given in the input file net list. Its model is given in the included library or model file or pasted into the input file.

For example:




For example:* SPICE Input FileM2 3 2 0 0 RITSUBN7 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=1.0 nrs=1.0 D1 5 6 RITMEMDIODEQ1 3 2 0 QRITNPN**

SPICE Examples

MOSFET, BJT AND DIODE MODELS

* The Included Model File

*2-15-2009

.MODEL RITSUBN7 NMOS (LEVEL=7

+VERSION=3.1 CAPMOD=2 MOBMOD=1

+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 NSS=3E11

+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7

+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95

+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5





+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)

*

.model RITMEMDIODE D IS=3.02E-9 N=1 RS=207

+VJ=0.6 CJO=200e-12 M=0.5 BV=400

*

.MODEL QRITNPN NPN (BF=416 IKF=.06678 ISE=6.734E-15 IS=6.734E-15 NE=1.259

+RC=1 RB=10 VA=109)

SPICE Examples

SIMULATION PROGRAM FOR INTEGRATED CIRCUIT ENGINEERING

MOSFET Device models used by SPICE (Simulation Program for

Integrated Circuit Engineering) simulators can be divided into three

classes: First Generation (Level 1, Level 2, Level 3 models), Second

Generation (BISM, HSPICE Level 28, BSIM2 models) and Third

Generation (BSIM3, Level 7, Level 49, etc.models) The newer

generations can do a better job with short channel effects, local




generations can do a better job with short channel effects, local

stress, transistors operating in the sub-threshold region, gate leakage

(tunneling), noise calculations, temperature variations and the

equations used are better with respect to convergence during circuit

simulation.

SPICE Examples

MOSFET SPICE MODEL LEVELS

1st Generation

2nd Generation




2nd Generation

3rd Generation

note: PSpice does not recognize level 49, WinSpice does not recognize level 7

SPICE Examples

RIT MOSFET SPICE MODELS

*SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 2-5-2010*LOCATION DR.FULLER'S COMPUTER DESKTOP/SPICE/MODELS/FULLER_RIT_MOSFET_MODELS.txt*SEE: http://people.rit.edu/lffeee/CMOS.htm**LIST OF DEVICES/MODELS INCLUDED IN THIS LIBRARY** RITMEMDIODE DIODE MODEL FOR EMCR870 MEMS FABRICATION COURSE* RITPMOS7 LEVEL 7 MODEL FOR PMOSFET MADE IN RIT PMOS PROCESS* RITPMOS49 LEVEL 49 MODEL FOR PMOSFET MADE IN RIT PMOS PROCESS* RITSUBN1 LEVEL 1 MODEL FOR NMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBP1 LEVEL 1 MODEL FOR PMOSFET MADE IN RIT SUB-CMOS PROCESS




* RITSUBN1 LEVEL 1 MODEL FOR NMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBP1 LEVEL 1 MODEL FOR PMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBN3 LEVEL 3 MODEL FOR NMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBP3 LEVEL 3 MODEL FOR PMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBN7 LEVEL 7 MODEL FOR NMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBP7 LEVEL 7 MODEL FOR PMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBN49 LEVEL 49 MODEL FOR NMOSFET MADE IN RIT SUB-CMOS PROCESS* RITSUBP49 LEVEL 49 MODEL FOR PMOSFET MADE IN RIT SUB-CMOS PROCESS* CMOSN LEVEL 2 MODEL FOR NMOSFET ORBIT SEMICONDUCTOR* CMOSP LEVEL 2 MODEL FOR PMOSFET ORBIT SEMICONDUCTOR* EENMOS LEVEL=2 MODEL FOR NMOSFET USED IN EEEE481 ELECTRONICS I* QRITNPN BJT MODEL USED IN EMCR482 ELECTRONICS II** note: Level 7 and Level 49 are the same except for two extra parameters in level 49* PSpice does not recognize level 49, WinSpice does not recognize level 7*

SPICE Examples

LEVEL=1, RIT SUB-CMOS 150 PROCESS

**2-15-2009.MODEL RITSUBN1 NMOS (LEVEL=1 +VTO=1.0 LAMBDA= 0.031 PB=0.95 CGSO=3.4E-10 CGDO=3.4E-10 +CGBO=5.75E-10 RSH=1082 CJ=6.8e-4 MJ=0.5 CJSW=1.26e-10 +MJSW=0.5 JS=3.23e-8 TOX=150E-10 NSUB=1.45e17 NSS=3E11 +TPG=+1 XJ=0.18U LD=0.15U UO=363)*




**2-15-2009.MODEL RITSUBP1 PMOS (LEVEL=1 +VTO=-1.0 LAMBDA= 0.05 PB=0.94 CGSO=5.08E-10 CGDO=5.08E-10 +CGBO=5.75E-10 RSH=33.7 CJ=5.01e-4 MJ=0.5 CJSW=1.38e-10 +MJSW=0.5 JS=6.43e-8 TOX=150E-10 NSUB=7.23e16 NSS=1E11 +TPG=-1 XJ=0.28U LD=0.22U UO=463)**

SPICE Examples


*

*1-15-2007 FROM DR. FULLER'S SPREAD SHEET

.MODEL RITSUBN3 NMOS (LEVEL=3 TPG=1 TOX=1.5E-8 LD=2.95E-7 WD=3.00E-7

+UO= 263 VTO=0.5 THETA=0.046 RS=27 RD=27 DELTA=2.27 NSUB=1.45E17

+XJ=1.84E-7 VMAX=1.10E7 ETA=0.927 KAPPA=0.655 NFS=3E11

+CGSO=3.4E-10 CGDO=3.48E-10 CGBO=5.75E-10 XQC=0.4)

*




*

*1-17-2007 FROM DR. FULLER'S SPREAD SHEET

.MODEL RITSUBP3 PMOS (LEVEL=3 TPG=-1 TOX=1.5E-8 LD=3.61E-7 WD=3E-7

+UO=275 VTO=-0.93 THETA=0.237 RS=33.7 RD=33.7 DELTA=2.35 NSUB=7.12E16

+XJ=2.26E-7 VMAX=7.02E6 ETA=0.897 KAPPA=4.481 NFS=3E11

+CGSO=4.15E-10 CGDO=4.15E-10 CGBO=5.75E-10 XQC=0.40)

*

SPICE Examples


*1-15-2007

.MODEL RITSUBN7 NMOS (LEVEL=7 VERSION=3.1 CAPMOD=2 MOBMOD=1


+VTH0=1.0 U0= 650 WINT=2.0E-7 LINT=1.84E-7




*




*

*1-17-2007

.MODEL RITSUBP7 PMOS (LEVEL=7 VERSION=3.1 CAPMOD=2 MOBMOD=1

+TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 NSS=3E11 PCLM=5

+VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 NGATE=5E20

+RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94

+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94


*

SPICE Examples


*1-15-2007

. .MODEL RITSUBN49 NMOS (LEVEL=49



+XWREF=2.0E-7 XLREF=2.95E-7

+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7








*1-17-2007

.MODEL RITSUBP49 PMOS (LEVEL=49



+XWREF= 2.0E-7 XLREF=3.61E-7



+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94

+CGS0=4.5E-10 CGD0=4.5E-10 CGB0=5.75E-10)

SPICE Examples

2.0 um MOSIS SCNA20 Process Level 2 Model

*3-23-2009*From Dr. Pearson's VLSI Class*SPICE Level 2 Parameters for Supertex's (formerly Orbit Semiconductor's)*2.0um MOSIS SCNA20 Process (from N7CK production run)*.MODEL CMOSN NMOS LEVEL=2 PHI=0.7 TOX=4.08E-8 XJ=0.2 TPG=1+VTO=0.8096 DELTA=4.586 LD=2.972E-7 KP=5.3532E-5+UO=632.5 UEXP=0.1328 UCRIT=3.897E4 RSH=6.202+GAMMA=0.5263 NSUB=5.977E15 NFS=5.925e11 VMAX=5.83E4+LAMBDA=3.903E-2 CGDO=3.7731E-10 CGSO=3.7731E-10+CGBO=3.4581E-10 CJ=1.3679E-4 MJ=0.63238 CJSW=5.1553E-10




+CGBO=3.4581E-10 CJ=1.3679E-4 MJ=0.63238 CJSW=5.1553E-10+MJSW=0.26805 PB=0.4 *Weff=Wdrawn-Delta_W*The suggested Delta_W is 2.00E-9*.MODEL CMOSP PMOS LEVEL=2 PHI=0.7 TOX=4.08E-8 XJ=0.2 TPG=-1+VTO=-0.8483 DELTA=1.952 LD=3.431E-7 KP=1.779E-5+UO=210.2 UEXP=0.4659 UCRIT=1.324E5 RSH=0.10960+GAMMA=0.5263 NSUB=5.977E15 NFS=5.925e11 VMAX=5.83E4+LAMBDA=6.372E-2 CGDO=4.3558E-10 CGSO=4.3558E-10+CGBO=3.5957E-10 CJ=3.1646E-4 MJ=0.59954 CJSW=3.4394E-10+MJSW=0.21153 PB=0.9 *Weff=Wdrawn-Delta_W*The suggested Delta_W is 5.72E-8

SPICE Examples

RIT METAL GATE PMOS

*1-17-2010

.MODEL RITPMOS7 PMOS (LEVEL=7 VERSION=3.1 CAPMOD=2 MOBMOD=1


*+XWREF= -0.5E-6 XLREF=4.41E-6

+VTH0=-0.8 U0= 600 WINT=2.0E-7 LINT=2.26E-6 NGATE=5E20


+CJSW=4.97E-10 MJSW=0.5 PBSW=0.88

+CGS0=1.09E-10 CGD0=1.09E-10 CGB0=6.90E-10)




+CGS0=1.09E-10 CGD0=1.09E-10 CGB0=6.90E-10)

*

*1-17-2010

.MODEL RITPMOS49 PMOS (LEVEL=49 VERSION=3.1 CAPMOD=2 MOBMOD=1


+XWREF= -0.5E-6 XLREF=4.41E-6

+VTH0=-0.8 U0= 600 WINT=2.0E-7 LINT=2.26E-6 NGATE=5E20


+CJSW=4.97E-10 MJSW=0.5 PBSW=0.88

+CGS0=1.09E-10 CGD0=1.09E-10 CGB0=6.90E-10)

*

SPICE Examples

OTHER DEVICE MODELS

*The following is the model for MbreakN

.MODEL MbreskN NMOS (LEVEL = 1 VTO = 0 KP=20.000000E-06 GAMMA = 0 PHI = 0.6

+LAMBDA = 0 IS = 10.000000E-15 JS = 0 PB = 0.8 PBSW = 0.8

+CJ = 0 CJSW = 0 CGSO = 0 CGDO = 0 CGBO = 0

+TOX = 0 XJ = 0 UCRIT= 10.000000E+03 DIOMOD=1 VFB=0 LETA=0

+WETA = 0 U0 = 0 TEMP= 0 VDD = 0 XPART = 0 ) ** Diode Model from MEMS Fabrication EMCR870.model RITMEMDIODE D IS=3.02E-9 N=1 RS=207




.model RITMEMDIODE D IS=3.02E-9 N=1 RS=207+VJ=0.6 CJO=200e-12 M=0.5 BV=400** From Electronics I EEEE481.model EENMOS NMOS LEVEL=2+VTO=0.7 KP=25E-6 LAMBDA=0.02 GAMMA=0.9 TOX=90E-9 NSUB=3.7E15** From Electronics II EEEE482 BJT Model.MODEL QRITNPN NPN (BF=416 IKF=.06678 ISE=6.734E-15 IS=6.734E-15 NE=1.259 RC=1 RB=10 VA=109)

SPICE Examples

SIMULATIONS USING 1st GENERATION MODELS




1st Generation - Level 2 Model1st Generation - Level 1 Model

SPICE Examples

SIMULATIONS USING 3rd GENERATION MODELS




3rd Generation - Level 7 ModelMeasured

SPICE Examples

MEASURED COMPARED TO SIMULATION

Level 7




Level 1

Level 7

SPICE Examples

MEASURED Ids – Vgs and gm

gm

Id-Vgs

Level = 1Measured




gmId-Vgs

Level = 7

Level = 1

SPICE Examples

SIMULATION of Sub-Threshold Ids-Vgs Curve

Level = 1Measured




Level = 7

Measured

SPICE Examples

ALD1103

From Data Sheets




From Data Sheets

From SimulationGiven model on left with L=10u and W=1000u

Note: not a very good match. Increase L?

SPICE Examples

CONCLUSION FROM DC MODEL COMPARISON

Third generation MOSFET models such as Level 7 for OrCAD PSPICE or Level 49 models for WinSpice give better results than any of the 1st or 2nd generation models. These models are different for different processes (such as RIT’s Sub-CMOS 150 or RIT’s Adv-CMOS 150 processes)




SPICE Examples

FAMILY OF CURVES USING WINSPICE

nmos family of curves.incl Fuller_RIT_MOSFET_MODELS.txt*m1 2 1 0 0 cmosn W= 10u L= 5uvd 2 0 dc 5vg 1 0 dc 5***************************dc sweep analysis****

1

Vg=1

+

-

Vd = 0.1

+

-

M1

2




***dc sweep analysis****.dc vd 0 5 10m vg 0 5 .5************************.end

Vg=1

0

SPICE Examples

SPICE SIMULATION OF MOSFET ID VS. VGS

IDS VS. VGS FOR RIT SUB-CMOS NMOSFET, Dr. Lynn Fuller, 1-15-2007*LINE ABOVE IS TITLE**START WIN SPICE AND ENTER LOCATION AND NAME OF INPUT FILE*THIS FILE IS ID-VD-N.TXT*EXAMPLE: winspice> source c:/spice/ID-VD-N.txt**THE TRANSISTOR MODELS ARE IN THE FILE NAMED BELOW.INCLUDE E:\SPICE\WINSPICE\RIT_MICROE_MODELS.TXT**CIRCUIT DESCRIPTION**VOLTAGE SOURCESV1 1 0 DC 0.1V2 2 0 DC 1




V2 2 0 DC 1**TRANSISTORSM1 7 2 0 0 RITSUBN49 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=0.025 nrs=0.025**CURRENT METERS (VOLTAGE SOURCES OF VALUE = ZERO)*VD1 1 7 DC 0**REQUESTED ANALYSIS*.OP.DC V2 0 5 .025.PRINT DC I(VD1).PLOT DC I(VD1) DERIV(I(VD1)).END

1

2

V2=1

+-

V1 = 0.1

+-

M1

VD1=0 +-

7

0

SPICE Examples

NMOS INVERTER WITH RESISTER LOAD

INVERTER USING RESISTOR LOAD FOR RIT SUB-CMOS NMOSFET, Dr. Lynn Fuller, 1-15-2007

*LINE ABOVE IS TITLE

*

*START WIN SPICE AND ENTER LOCATION AND NAME OF INPUT FILE

*THIS FILE IS INVERTER.TXT

*EXAMPLE: winspice> source c:/spice/INVERTER.txt

*

*THE TRANSISTOR MODELS ARE IN THE FILE NAMED BELOW

.INCLUDE E:\SPICE\WINSPICE\RIT_MICROE_MODELS.TXT

*

*VOLTAGE SOURCES

*

1

2

V10to-5

+-

M1

R=10K

7

+-




*

V1 1 0 DC 5

V2 2 0 DC 1

*

*TRANSISTORS

M1 7 2 0 0 RITSUBN49 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6

+ps=44e-6 nrd=0.025 nrs=0.025

*

*RESISTORS

R1 1 7 10000

*

*REQUESTED ANALYSIS

.OP

.DC V2 0 5 .1

.PLOT DC V(7)

.END

V2=1 -

0

SPICE Examples

CMOS THEORETICAL INVERTER VOUT VS VIN

VIN VOUT

+VIdd

+V

VohImax

VOUT

Slope = Gain




VIN

CMOS

VO

+V0

0

ViL

VoL

Vih

VIN

Idd

∆∆∆∆0 noise margin=ViL-VoL∆∆∆∆1 noise margin=VoH-ViH

Vinv

SPICE Examples

INVERTER LAYOUT WITH PADS




INV/NOR4

W = 40 µmLdrawn = 2.5µmLpoly = 1.5µmLeff = 1.0 µm

SPICE Examples

DC SIMULATION OF INVERTER VOUT & I VS VIN

Homework Assignment




Homework Assignment

SPICE Examples

MEASURED CMOS INVERTER VOUT & I VS VIN




SPICE Examples

RING OSCILLATOR, td, THEORY

td = T / 2 Ntd = gate delayN = number of stagesT = period of oscillation

Vout

Seven stage ring oscillatorwith two output buffers

Buffer




T = period of oscillation

T = period of oscillation

Vout

Buffer

SPICE Examples

MEASURED RING OSCILLATOR OUTPUT

73 Stage Ring at 5V




td = 104.8ns / 2(73) = 0.718 ns

SPICE Examples

SPICE LEVEL-1 MOSFET MODEL

p+ p+

S

G

D

CGDO

COX

CGSO




p+ p+

CBDCBS

RS RDID

CGBO

B

where ID is a dependent current source using simple long channel equations.

SPICE Examples

AC MODEL FOR MOSFETS

The parameters that effect the AC response of a MOSFET are the resistance and capacitance values.

RS,RS Source/Drain Series Resistance, ohmsRSH Sheet Resistance of Drain/Source, ohmsCGSO,CGDO Zero Bias Gate-Source/Drain Capacitance, F/m of widthCGBO Zero Bias Gate-Substrate Capacitance, F/m of lengthCJ DS Bottom Junction Capacitance, F/m2CJSW DS Side Wall Junction Capacitance, F/m of perimeter




CJ DS Bottom Junction Capacitance, F/m2CJSW DS Side Wall Junction Capacitance, F/m of perimeterMJ Junction Grading Coefficient, 0.5MJSW Side Wall Grading Coefficient, 0.5

These are combined with the transistors L, W Length and WidthAS,AD Area of the Source/DrainPS,PD Perimeter of the Source/DrainNRS,NRD Number of squares Contact to Channel

SPICE Examples

RING OSCILLATOR LAYOUTS

17 Stage Un-buffered Output L/W=2/30 Buffered Output




L/W 8/16 4/16 2/16 73 Stage 37 Stage

SPICE Examples

MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR

nmosfet pmosfet




73 Stage Ring Oscillator

SPICE Examples

FIND DIMENSIONS OF THE TRANSISTORS

NMOS PMOS

L 2u 2u

W 12u 30u

AD 12ux12u=144p 12ux30u=360p

AS 12ux12u=144p 12ux30u=360p

73 Stage




AS 12ux12u=144p 12ux30u=360p

PD 2x(12u+12u)=48u 2x(12u+30u)=84u

PS 2x(12u+12u)=48u 2x(12u+30u)=84u

NRS 1 0.2

NRD 1.2 0.3

Use Ctrl Click on all NMOS on OrCad SchematicUse Ctrl Click on all PMOS on OrCad SchematicThen Enter Dimensions

SPICE Examples

LEVEL = 7

*2-15-2009

.MODEL RITSUBN7 NMOS (LEVEL=7



+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7







*

*2-17-2009

.MODEL RITSUBP7 PMOS (LEVEL=7





+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94


SPICE Examples

SIMULATED OUTPUT AT 10 VOLTS




Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring Oscillator and Supply of 10 volts

td = T / 2N = 3.5nsec / 2 / 3

td = 0.583 nsec

SPICE Examples

SIMULATED OUTPUT AT 5 VOLTS




Three Stage Ring Oscillator with Transistor Parameters for 73 Stage Ring Oscillator and Supply of 5 volts

td = T / 2N = 5.5nsec / 2 / 3

td = 0.92 nsecMeasured td = 0.718 nsec @ 5 V

SPICE Examples

CONCLUSION

Since the measured and the simulated gate delays, td are close to correct, then the SPICE model must be close to correct. The inverter gate delay depends on the values of the internal capacitors and resistances of the transistor.

Specifically: RS, RS, RSH




RS, RS, RSHCGSO, CGDO, CGBOCJ, CJSW

These are combined with the transistors L, W Length and WidthAS,AD Area of the Source/DrainPS,PD Perimeter of the Source/DrainNRS,NRD Number of squares Contact to Channel

SPICE Examples

TWO-PHASE CLOCK GENERATORS

CLOCKBAR

CLOCK ΦΦΦΦ1

ΦΦΦΦ2

CLOCK

t3

t2

t1

QS

0 0 Qn-1

0 1 1

1 0 0

1 1 INDETERMINATE

RCB

0 0 1

0 1 0

1 0 0

1 1 0

A

S

R

Q




ΦΦΦΦ1

ΦΦΦΦ2

CLOCK

BAR t1

t3

t1

t2

=

t3

SPICE Examples

TWO PHASE CLOCK VERSION ONE

2V1

5V

+

-

1

V2

CLOCK

+

-

8 9

M11

M13

M15

M17

VOUT1 VOUT210 11



Microelectronic EngineeringSubstrate of all NMOS go to ground, node 0

Substrate of all PMOS go to +5V, node 1

M3 M5

M4 M6

3 4

M1

M2

0

CLOCK-

765

M9

M10

M7

M8

M12M14 M16 M18

SPICE Examples

WINSPICE INPUT FILE

TWO PHASE CLOCK USING RIT SUB-CMOS MOSFETS, Dr. Lynn Fuller, 4-3-2009

*LINE ABOVE IS TITLE

*

*START WIN SPICE AND ENTER> SOURCE "LOCATION AND NAME OF INPUT FILE"

*THIS FILE IS TWOPHASECLOCK1.TXT

*EXAMPLE: winspice> source c:/spice/ID-VD-N.txt

*

*THE TRANSISTOR MODELS ARE IN THE FILE NAMED BELOW

.INCLUDE c:\Documents and




.INCLUDE c:\Documents and

Settings\lffeee\Desktop\SPICE\WINSPICE_Examples\RIT_PSPICE_MODELS.TXT

*

*CIRCUIT DESCRIPTION

*VOLTAGE SOURCES

V1 1 0 DC 5

V2 2 0 PULSE (0 5 0 1NS 1NS 10NS 20NS)

*

*PMOS

M1 1 2 3 1 RITSUBP49 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=1.0 nrs=1.0





SPICE Examples

WINSPICE INPUT FILE





*

*NMOS

M2 3 2 0 0 RITSUBN49 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=1.0 nrs=1.0













*

*REQUESTED ANALYSIS

.OP

.TRAN 1N 100N

.PLOT TRAN V(8) V(9) V(2)

.END

SPICE Examples

WINSPICE SIMULATION

Clock outputs are node 8 and 9




SPICE Examples

TWO PHASE NON OVERLAPPING CLOCK

Clock

Φ1




Φ1

Φ2

SPICE Examples

VERSION 2 OF TWO PHASE NON OVERLAPPING CLOCK

CLOCKBAR

CLOCK ΦΦΦΦ1

ΦΦΦΦ2t3

t2

t1

S

R

18

9

M13 M17

VOUT1 VOUT2




2

V1

5V

+

-

0

V2

CLOCK

+

-

M5

M7

M6 M16

3 4

M3

M4

76

M1

M2

5

M9

M10

M11

M12 M14

M15

M18

M8

VOUT1 VOUT210 11

SPICE Examples

WINSPICE SIMULATION FOR VERSION TWO




SPICE Examples

WINSPICE SIMULATION FOR VERSION TWO + BUFFERS

CLOCKBAR

CLOCK ΦΦΦΦ1

ΦΦΦΦ2t3

t2

t1

S

R




SPICE Examples

BASIC TWO STAGE OPERATIONAL AMPLIFIER




SPICE Examples

SPICE ANALYSIS OF OP AMP VERSION 2

.incl rit_sub_param.txtm1 8 9 7 6 cmosn w=9u l=5u nrd=1 nrs=1 ad=45p pd=28u as=45p ps=28um2 1 10 7 6 cmosn w=9u l=5u nrd=1 nrs=1 ad=45p pd=28u as=45p ps=28um3 8 8 4 4 cmosp w=21u l=5u nrd=1 nrs=1 ad=102p pd=50u as=102p ps=50um4 1 8 4 4 cmosp w=21u l=5u nrd=1 nrs=1 ad=102p pd=50u as=102p ps=50um5 7 5 6 6 cmosn w=40u l=5u nrd=1 nrs=1 ad=205p pd=90u as=205p ps=90um6 2 1 4 4 cmosp w=190u l=5u nrd=1 nrs=1 ad=950p pd=400u as=950p ps=400u m7 2 5 6 6 cmosn w=190u l=5u nrd=1 nrs=1 ad=950p pd=400u as=950p ps=400u m8 5 5 6 6 cmosn w=40u l=5u nrd=1 nrs=1 ad=205p pd=90u as=205p ps=90uvdd 4 0 3vss 6 0 -3cprobe 2 0 30pRprobe 2 0 1meg




cprobe 2 0 30pRprobe 2 0 1megcc 1 2 0.6pmr1 20 20 4 4 cmosp w=6u l=10u nrd=1 nrs=1 ad=200p pd=60u as=200p ps=60umr2 5 5 20 4 cmosp w=6u l=10u nrd=1 nrs=1 ad=200p pd=60u as=200p ps=60u**************************** ***dc open loop

gain*********vi1 9 0 0vi2 10 0 0 *.dc vi2 -0.002 0.002 1u.dc vi2 -1 1 0.1m*****open loop frequency

characteristics******vi1 9 0 0 *vi2 10 0 dc 0 ac 1u*.ac dec 100 10 1g.end

13.5kV/V gain

SPICE Examples

RIT OP AMP WITH OUTPUT STAGE

1

M6

W/L100/2

99

M5

W/L100/2

3

+V +V2

M8 M15

W/L686/2

M19

W/L3800/2

M11

12

M16

M12

9W/L282/2

W/L100/2




20/40

M7

M140/2

1

6

M2

Vin+

40/2

Vin-+V +V

98

2

M490/2

M390/2

45

M14

90/2M10 90/2

13

M13

30/230/2

M17

M20

M181014

M9

W/L

W/L336/2

7

RL

118

W/L2600/2

W/L100/2

W/L645/2

W/L100/2

SPICE Examples

Square Wave, Triangle Wave, Sine Wave Circuit

-

C33

R33+

+V

R2R1 VT

-

C22

R22

Vo1

Rf22Rf33




-

+Vo3-

C

-V

R

-

+ Vo2Vo1

SPICE Examples

Results Square Wave, Triangle Wave, Sine Wave




SPICE Examples

REFERENCES

1. MOSFET Modeling with SPICE, Daniel Foty, 1997, Prentice Hall, ISBN-0-13-227935-5

2. Operation and Modeling of the MOS Transistor, 2nd Edition, Yannis Tsividis, 1999, McGraw-Hill, ISBN-0-07-065523-5

3. UTMOST III Modeling Manual-Vol.1. Ch. 5. From Silvaco International.4. ATHENA USERS Manual, From Silvaco International.5. ATLAS USERS Manual, From Silvaco International.6. Device Electronics for Integrated Circuits, Richard Muller and Theodore




6. Device Electronics for Integrated Circuits, Richard Muller and Theodore Kamins, with Mansun Chan, 3rd Edition, John Wiley, 2003, ISBN 0-471-59398-2

7. ICCAP Manual, Hewlet Packard8. PSpice Users Guide.

SPICE Examples

HOMEWORK - SPICE EXAMPLES

1. Do SPICE for the CMOS inverter using transistor models for RIT’s sub-micron 150 process.


