SPIROC : Silicon PM Readout ASIC - NDIPndip.in2p3.fr/ndip08/Presentations/4Wednesday/... · Dual DAC. 3616 . Analog. memory. 36 . Preamp. Shaper. discri. 362 . Wilkinson. ADC. SRAM

SPIROC : Silicon PM Readout ASIC

Stéphane Callier, Frédéric Dulucq, Julien Fleury, Gisèle Martin-Chassard, Christophe de La Taille,

Ludovic RauxIN2P3/OMEGA-LAL Orsay

18 june 08 C. de La Taille SPIROC : SiPM readout ASIC NDIP08 Aix les Bains 2

CALICE : imaging caorimetry

• After LHC : New imaging calorimetry…at the ILC• Improve jets measurement by Particle flow algorithm• CALICE : 281 phys., 47 labs, 12 countries. Chairperson : JC Brient http://llr.in2p3.fr/activites/physique/flc/calice.htm

TCMTAHCAL

beam

ECAL

SiW ECALW/Sci SiPM ECALSci SiPM AHCAL

RPC DHCAL


CALICE AHCAL testbeam prototype

• Hadronic calorimeter prototype for the ILC : 1 cubic metre, 38 layers, 2cm steel plates

• 8000 tiles with SiPMs fabricated by MePHY group

Mechanics and front end boards: DESYFront end ASICs: LAL

FLC_SiPMASIC Mephy SiPM

Also used withW/Sci SiPM

japanese ECALwith MPPCs


ILC Challenges for electronics

• Requirements for electronics– Large dynamic range (15 bits)– Auto-trigger on ½ MIP – On chip zero suppress– Front-end embedded in detector

– Ultra-low power : («25µW/ch)– 108 channels– Compactness

• « Tracker electronics with calorimetric performance »

• No chip = no detector !!

ATLAS LAr FEB 128ch 400*500mm 1 W/chFLC_PHY3 18ch 10*10mm 5mW/chILC : 25µW/ch

W layer

ASIC

Ultra-low POWER

is the KEY issue

Si wafers


The front-end ASICs : the ROC chips

SPIROCAnalog HCAL(SiPM)36 ch. 32mm²June 07

HARDROCDigital HCAL(RPC, µmegas or GEMs)64 ch. 16mm²Sept 06

SKIROCECAL(Si PIN diode)36 ch. 20mm²Nov 06

• Technological prototypes : full scale modules (~2m)

• EUDET EU funding (06-09)• ECAL, AHCAL, DHCAL• B=5T


Second generation chip for SiPM

• SPIROC : Silicon Photomul. Integrated Readout Chip– 36 channels– Charge measurement – Time measurement – Autotrigger on MIP or spe– Sparsified readout compatible

with EUDET 2nd generation DAQ– Chips daisy-chained– Pulsed power -> 25 µW/ch

• Fabricated in SiGe AMS 0.35 µm– Submitted in june 07– Chip area : 30 mm2


SPIROC main features• Internal input 8-bit DAC (0-5V) for individual SiPM gain

adjustment• Energy measurement : 14 bits

– 2 gains (1-10) + 12 bit ADC 1 pe 2000 pe– Variable shaping time from 50ns to 100ns – pe/noise ratio : 11

• Auto-trigger on 1/3 pe (50fC)– pe/noise ratio on trigger channel : 24– Fast shaper : ~10ns– Auto-Trigger on ½ pe

• Time measurement : – 12-bit Bunch Crossing ID– 12 bit TDC step~100 ps

• Analog memory for time and charge measurement : depth = 16• Low consumption : ~25µW per channel (in power pulsing mode)• Individually addressable calibration injection capacitance• Embedded bandgap for voltage references• Embedded 10 bit DAC for trigger threshold and gain selection• Multiplexed analog output for physics prototype DAQ• 4k internal memory and Daisy chain readout


SPIROC : One channel schematic

IN test

50 -100ns

50-100ns

Gain selection

4-bit threshold adjustment

10-bit DAC

15ns

DAC output

HOLD

Slow Shaper

Slow Shaper

Fast Shaper

Time measurement

Charge measurement

TDC ramp 300ns/5 µs

12-bit Wilkinson

ADC

Trigger

Depth 16

Depth 16

Depth 16

Common to the 36 channels

8-bit DAC

0-5V

Low gain Preamplifier

High gain Preamplifier

Analog memory

15pF

1.5pF

0.1pF-1.5pF

Conversion

80 µs

READ

Variable delay

0.1pF-1.5pF

IN

Discri

Gain

Flag TDC


DAQASIC

Chip ID register 8 bits

gain

Trigger discri Output

Wilkinson ADC Discri output

gain

Trigger discri Output

Wilkinson ADC Discri output

..…

OR36

EndRamp (Discri ADC Wilkinson)

36

36

36

TM (Discri trigger)

ValGain (low gain or high Gain)

ExtSigmaTM (OR36)

Channel 1

Channel 0

ValDimGray 12 bits

…

Acquisition

readoutConversion

ADC

+

Ecriture RAM

RAM

FlagTDC

ValDimGray

12

8

ChipID

Hit channel register 16 x 36 x 1 bits

TDC rampStartRampTDC

BCID 16 x 8 bits

ADC rampStartrampb (wilkinson

ramp)

1616

ValidHoldAnalogbRazRangN

16ReadMesureb

Rstb

Clk40MHz

SlowClockStartAcqt

StartConvDAQb

StartReadOut

NoTrig

RamFull

TransmitOn

OutSerie

EndReadOut

Chipsat


SPIROC layout

36 8bit

5V DAC

Dual DACBandgap

36*16 Analog

memory

36 PreampShaperdiscri

36*2 Wilkinson

ADC

SRAMReadout


Expressions

0 .250 .500 .750 1.0time (us)

2.50

-2.5-5.0-7.5

-10.0

Y0 (m

V)Y0

(mV)

.2500

-.250-.500-.750

-1.0-1.25

Y1 (m

V)Y1

(mV)

150100

50.00

-50.0-100-150

Y2 (m

V)Y2

(mV)

10.07.55.02.5

0-2.5

Y3 (m

V)Y3

(mV)

1.251.0

.750

.500

.2500

-.250

Y4 (m

V)Y4

(mV)

out_pa_hg

out_pa_lg

out_fs

out_ssh_hg

out_ssh_lg

time (us)

User: raux Date: Feb 9, 2007 Time: 2:34:15 PM CET

High gain Preamplifier response

Low gain Preamplifier response

Fast shaper

High gain Slow shaper

Low gain Slow shaper

Tp=15ns

Tp=50ns

Tp=50ns

Noise/pe ratio = 25

Noise/pe ratio = 11

Noise/pe ratio = 31mV/pe

10mV/pe

120mV/pe

Simulation obtained with SiPM gain = 106 _ 1 pe = 160 fC

Simulated waveforms


Input DAC

• 8 bit, 5V range• LSB=20mV• 36 DACs : one per

channel• Ultra low power (1µW) :

no power pulsing• Can sink 10 µA leakage

current• Linearity : ± 2%

DAC linearity

00,5

11,5

22,5

33,5

44,5

5

0 50 100 150 200 250 300

DAC

Volta

ge (V

)

-0,04

-0,03

-0,02

-0,01

0

0,01

0,02

0,03

0 50 100 150 200 250 300


Trigger and gain selection DAC measurement

• Linearity : typ ±0.2%

y = -0,00198623x + 2,32465620R2 = 0,99996616

0

0,5

1

1,5

2

2,5

0 200 400 600 800 1000

-0,01-0,008-0,006-0,004-0,002

00,0020,0040,0060,008

0,01

0 200 400 600 800 1000-0,004

-0,003

-0,002

-0,001

0

0,001

0,002

0,003

0,004

0 200 400 600 800 1000

Linearity

y = -0,0019918454x + 2,3253901509R2 = 0,9999969857

0

0,5

1

1,5

2

2,5

0 200 400 600 800 1000

Trigger DAC Gain selection DAC

Résiduals (V)


Input preamp

• Bi-gain low noise preamp– Reused from SKIROC– Low noise charge preamp

capacitively coupled = voltage preamp

– Gain adjustable with 4 bits common to all preamps : Cf=0.2, 0.4, 0.8, 1.6 pF

– Positive input pulse– 8 mV/pe in HI Gain– Noise : 1.4 nV/sqrt(Hz)– Power : 2 mW (unpulsed)

• Low gain at preamp level – 1.5pF coupling capacitor– 0.8 mV/pe, MAX : 2000 pe

(300pC)

15pF 0.1pF-1.5pF

+HV

Si PM

8-bit DAC

ASICHigh voltage on the cable

shielding


Analog waveforms

680fC ( ~4 pe @SiPM gain=106) in SPIROC

Charge measurement

Auto trigger

High gain channel output

Vout=30mV

Noise=1mV

Gain=45mV/pC

pe/noise~7 (expected ~11)Set up:

Cf=400fF

Tau=50ns


Gain uniformity

• Pedestal uniformity– Avg = 1.16V– Rms = 1.8 mV

• Gain uniformity – Rms 1%– 45 mV/pC (Cf=0.2pF

tau=50ns)

• Noise : ~ 1mV Gain uniformity

43,5

44

44,5

45

45,5

46

46,5

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35Channel

Vout

(mV)

pedestal

1,15

1,155

1,16

1,165

1,17

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35

Channel

DC

vol

tage

(V)

05

1015202530354045

0 0,5 1 1,5

Cf (pF)

outp

ut (m

V/pC

)


S-curves

• Trigger efficiency versus Threshold (1UDAC=2mV)S-curves

0

10

20

30

40

50

60

70

80

90

100

388 390 392 394 396 398 400 402 404 406 408

DAC value

trigg

er e

ffici

ency

Measured Noise ~8mV

(expected ~ 5mV)


Trigger linearity

50% trigger efficiency vs Qinj Cf=200fF; tau=50ns

0

100

200

300

400

500

600

700

800

900

1000

0 200 400 600 800 1000 1200 1400

Qinj (fC)

50%

trig

ger e

ffici

ency

DA

C v

alue


Crosstalk and trigger time walk

• Very low Cross-Talk : 0.3% (long distance cross talk due to slow shaper voltage reference: If this voltage decoupled with 100µF, it becomes negligible ~0.04%)

• Trigger time walk: ~10ns

trigger time walk vs injected charge

0

2

4

6

8

10

12

0 1000 2000 3000 4000 5000

charge (in fC)

time

(in

ns)


12 bit Wilkinson ADC performance

• (stupid) bug in internal ADC : cannot be tested

• Similar to ADC in sister chip SKIROC

• 1 ADC/channel 12 bits 80µs• Fixed in SPIROC2

1046 1047 1048 1049 1050 10510

50

100

150

200

250

300

350

400

450

500

ADC bins (#) mean: 1048.283 std : 0.883

Cou

nt (#

) - to

tal i

s 10

00

SKIROC ADC dispersion - channel 18Noise in low gain shaper

rms = 0.9UADC(330µV)MIP =3 UADC

0 5 10 15 20 25 30 35 401045

1050

1055

1060

1065

1070

1075

1080

1085

AD

C c

ount

(#)

channel number (#)

Skiroc Pedestal Dispersion (Internal ADC)-Gain 1

1050

1080

1055 1060 1065 1070 1075 1080 1085 10900

10

20

30

40

50

60

70

80

90

100

ADC bins (#) mean: 1071.3 std : 4.629

Cou

nt (#

) - to

tal i

s 10

00

SKIROC ADC dispersion - channel 36

Noise in high gain shaper

rms = 4UADC(1.4mV)MIP=30UADC

Pedestal value vs Channel number


Single photoelectron spectrum

• Spiroc1 can already replace FLC_SiPM (multiplexed analog output)

©Beni (DESY)


Conclusion

• SPIROC is a versatile readout chip for SiPM photodetectors

• It provides– Charge measurement from 1 pe to 2000 pe in two linear

scales with a signal to noise ratio of 10– Time measurement to better than 1 ns– Auto-trigger on ½ pe with internal 10 bit DAC– Ultra low power 5V 8bit input DAC for SiPM gain adjustment– 25 µW/ch with 1% ILC Power pulsing– On chip Wilkinson ADC and RAM for daisy chain readout

• It will be produced in large scale in 2009 for the EUDET AHCAL module

• More information on MAROC, HaRDROC, SPIROC, SKIROC, PARISROC on http://omega.in2p3.fr


Backup slides


Barrel HCAL architecture

AHCAL Slab6 HBUs in a row

HBUHCAL Base Unit12 x 12 tiles

SPIROC4 on a HBU

HEBHCAL Endcap BoardHosts mezzanine modules:DIF, CALIB and POWERHLD

HCAL Layer Distributor

1/16 of barrel half

Power: 40 µW / channel

Heat:T grad. 0.3K/2mTime constant: 6 d

P.Goettlicher (DESY)

Front end ASICs embeddedInterfaces accessible


Integrated layer design

Sector wall

Reflector Foil100µm

Polyimide Foil100µm PCB

800µm

Bolt with innerM3 threadwelded to bottom plate

SiPMTile3mm

HBU Interface500µm gap

Bottom Plate600µm

ASICTQFP-1001mm high

Top Plate600µm steel

Component Area:900µm high

HBU height:6.1mm(4.9mm without covers => absorber)

AbsorberPlates(steel)

Spacer1.7mm

Top Plate fixing

DESY

integrated M.Reinecke (DESY)


Slow shaper & SCA

• Slow shaper from HaRDROC– Variable peaking time : 50-150

ns– 3 bits common to all channels– High Gain = 10 mV/pe – Noise = 900 µV– Low gain = 1 mV/pe

• Backup : analog T&H from HaRDROC– Hold capacitor : 2pF -> 0.5 pF– Needs external hold signal– Multiplexed analog output @

5MHz– Allows readout with DAQ0

50 -100ns

Slow Shaper

Depth 16

Analog memory

y = 2,8821x + 13,401R2 = 0,9997

0

50

100

150

200

250

0 10 20 30 40 50 60 70

DTC code

dela

y (n

s)


TDC

• New block– 12 bits– 300 ns full scale– 100 ps LSB (not accuracy !)– « common start » = BC– Time stored in SCA together with

charge– Can also be readout with backup

analog

T

Fast ramp 300ns

Trigger

Depth 16

Discri


Wilkinson ADC

• Taken from MAROC– New : adjustable

resolution : 8 - 10 or 12 bits

– 40 MHz clock– 6-100 µs conversion

time– Power dissipation :

350µW

INL versus Vin

-2,5

-2

-1,5

-1

-0,5

0

0,5

1

1,5

2

1,3 1,6 1,9 2,2 2,5

Vin(V)

INL

(ADC

cou

nt)


Digital part

• Inspired from HaRDROC– Internal or external

Trigger – OR36 output– Discriminator

Validation fast input– 4kbyte RAM– « Open collector »

output signals – LVDS clocks– Start conversion– Start/end readout

Documents

SPIROC : Silicon PM Readout ASIC - NDIPndip.in2p3.fr/ndip08/Presentations/4Wednesday/... · Dual DAC. 36*16 . Analog. memory. 36 . Preamp. Shaper. discri. 36*2 . Wilkinson. ADC. SRAM

SPIROC : Silicon PM Readout ASIC - NDIPndip.in2p3.fr/ndip08/Presentations/4Wednesday/... · Dual DAC. 3616 . Analog. memory. 36 . Preamp. Shaper. discri. 362 . Wilkinson. ADC. SRAM