Spring 2006

Lillevik 437s06-l5 1University of Portland School of Engineering

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Advanced ComputerArchitecture

Lecture 5

Slave bus agentROM example

I/O write port example

Spring 2006

Lillevik 437s06-l5 2University of Portland School of Engineering

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Slave block diagram

Decode

Data Source

Data Sink

Tri State

Tri State

AC

D

AckLS138 LS244

LS244

Device

Spring 2006

Lillevik 437s06-l5 3University of Portland School of Engineering

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Decoding

• Inputs– Address bus– Control bus

• Fully decoded: unique address/function found• Implementation (LS138)

– Two levels: address, control– Use output of first level to enable second

Spring 2006

Lillevik 437s06-l5 4University of Portland School of Engineering

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Decoding block diagram

LS138

LS138

A

C

Correct address

Correct address and function

First and second level may be reversed

Spring 2006

Lillevik 437s06-l5 5University of Portland School of Engineering

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Decoding for I/O write to 0xf

Spring 2006

Lillevik 437s06-l5 6University of Portland School of Engineering

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ROM block diagram

Decode

Data Source

Tri State

Tri State

AC

D

AckLS138 LS244

ROM

Spring 2006

Lillevik 437s06-l5 7University of Portland School of Engineering

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ROM example requirements

• Address range 0x00 – 0x0f, 16 words• CPU executes read memory instructions• Data of ROM (f, e, d, …, 2, 1, 0)• One master: Breq = Bgnt• No interrupts: Int = gnd

Spring 2006

Lillevik 437s06-l5 8University of Portland School of Engineering

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ROM system schematic

Spring 2006

Lillevik 437s06-l5 9University of Portland School of Engineering

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ROM memory schematic ?

Spring 2006

Lillevik 437s06-l5 10University of Portland School of Engineering

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ROM data filesPr

ogra

mR

OM

contents

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Lillevik 437s06-l5 11University of Portland School of Engineering

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ROM timing

CPU driving A, C ROM driving D

Spring 2006

Lillevik 437s06-l5 12University of Portland School of Engineering

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ROM timing, continued.

CPU driving A, C ROM driving D

Spring 2006

Lillevik 437s06-l5 13University of Portland School of Engineering

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Changes for RAM

• Address bus: same• Control bus: same• Decoding: must look for memory read and

memory write• Data bus: connected to both RAM data in and

data out• ACK: same

Spring 2006

Lillevik 437s06-l5 14University of Portland School of Engineering

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I/O write port block diagram

Decode Tri StateAC

D

AckLS138 LS244

Octal D’s

Data SinkV

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Lillevik 437s06-l5 15University of Portland School of Engineering

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I/O write port requirements

• Port address 0x10• CPU executes I/O write instructions• Data: 1, 2, 4, 8, 10, 20, 40, 80• One master: Breq = Bgnt• No interrupts: Int = gnd

Spring 2006

Lillevik 437s06-l5 16University of Portland School of Engineering

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I/O write port system schematic

Spring 2006

Lillevik 437s06-l5 17University of Portland School of Engineering

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Write port schematic ?

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Lillevik 437s06-l5 18University of Portland School of Engineering

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Write port data files

Program

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Lillevik 437s06-l5 19University of Portland School of Engineering

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Write port timing

Write 0x01 to Port 10 Write 0x02 to Port 10

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Lillevik 437s06-l5 20University of Portland School of Engineering

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Changes for I/O read

• Address bus: same• Control bus: same• Decoding: look for I/O read instruction• Data bus: must drive with tri-state devices• ACK: same

Spring 2006

Lillevik 437s06-l5 21University of Portland School of Engineering

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Spring 2006

Lillevik 437s06-l5 22University of Portland School of Engineering

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ROM memory schematic ?

Spring 2006

Lillevik 437s06-l5 23University of Portland School of Engineering

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Write port schematic ?