Spring 2006EE 5324 - VLSI Design II - © Kia Bazargan 1 EE 5324 – VLSI Design II Kia Bazargan University of Minnesota Part I: Introduction

Spring 2006 EE 5324 - VLSI Design II - © Kia Bazargan 1

EE 5324 – VLSI Design IIEE 5324 – VLSI Design II

Kia Bazargan

University of Minnesota

Part I: IntroductionPart I: Introduction


Section Outline

• Administrative Issues

• Semiconductor industry trends

• Chip implementation methodologies

• Design methodologies


Section Outline

•Administrative Issues





Administrative Issues

• Class Time and venue:______________________________ Web page:

http://www.ece.umn.edu/users/kia/Courses/EE5324 Textbook:

J. M. Rabaey, "Digital Integrated Circuits: A Design Perspective", Prentice Hall, 2nd Ed., 2002

CAD software:o Cadence / HSpice / Magic?

• Grades 40% homework and quizzes 25% midterm – open book. Date: ______________ 35% Final exam – open book. Date: ______________


Administrative Issues

• Personnel Instructor: Kia Bazargan

o Email: [email protected] Phone: (612) 625-4588 Office: EE/CSci 4-159o Office hours: __________________________

TA: ______________

o Email: ______________________________

o Phone: ___________ Office: _____________

o Office hours: ___________________


Administrative (cont.)

• Policies Homework must be received before class

o 1min – 24 hours late: 50% of the gradeo > 24 hours late: 0%

Zero tolerance for cheating Collaboration OK, copying NOT OK Include ID on all homework, exams, etc. No extra work for extra credit Check the class web pages regularly, the

students are responsible for checking the discussion threads and announcements regularly


Online Slides

• Slides are posted on the web Handouts as .pdf file Powerpoint files provided too

o NOTE: some slides are animated (like this one)o Click on the slide to see the animationo Click once more.

o Note: some slides have notes! (like this one)

o Some slides contain text that is not printed in the handouts, but animated. These are left for you to fill out in the handouts. An example is shown below (animated: click to see)

This is a sample text, not printed, but animated


References and Copyright

• Textbooks (only [Rab02] required) [WE92] N. H. E. Weste, K. Eshraghian

“Principles of CMOS VLSI Design: A System Perspective”Addison-Wesley, 2nd Ed., 1992.

[Rab02] J. M. Rabaey“Digital Integrated Circuits: A Design Perspective”Prentice Hall, 2nd Ed., 2002.

[Par00] B. Parhami“Computer Arithmetic: Algorithms and Hardware Designs”Oxford University Press, 2000.

[KL99] S. Kang, Y. Levlebici“CMOS Digital Integrated Circuits: Analysis and Design”McGraw-Hill, 2nd Ed., 1999.


References and Copyright (cont.)

• Slides used: [©Hauck] © Scott A. Hauck, 1996-2000;

G. Borriello, C. Ebeling, S. Burns, 1995, University of Washington (Modified by Kia when necessary)

[©Prentice Hall] © Prentice Hall 1995, © UCB 1996 Slides for [Rab96] http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html


What is This Course All About?

• Prerequisite Basic CMOS design Static/dynamic circuit design Layout / Simulation

• What is different from “VLSI Design I”? Higher-level of design (closer to architecture) Emphasis on performance, processor cores,

fault tolerance

• What is covered? Mostly arithmetic circuits Memories Test and testability New issues and design techniques


Course Outline• CMOS Designs

Arithmetic & logic unit (ALU)o Bitwise operationso Datapath layout

Adderso Basic adders: carry propagation, Carry Look-ahead,

Manchester Carry Chaino More complex adders: Carry Save Adder, Brent-Kungo Fast adders: Carry-Select adder, Wallace tree

Multiplierso Shift/Add multiplicationo Booth encodingo Multiplication by constantso Floating point multiplication


Course Outline (cont)

• CMOS Designs (cont) Shift/Rotate operations Memories

o Memory cells: static and dynamico Memory arrays: address decoders, sensors and

amplifiers

• Test and testability Fault models Design techniques: scan design, built-in self-test

• New design techniques/platforms CORDIC algorithms Bit-serial computations [Recent circuit examples]


Section Outline


•Semiconductor industry trends




IC Products• Processors

CPU, DSP, Controllers

• Memory chips RAM, ROM, EEPROM

• Analog Mobile communication,

audio/video processing

• Programmable PLA, FPGA

• Embedded systems Used in cars, factories Network cards

• System-on-chip (SoC)Images: amazon.com


IC Product Market Shares

Source: Electronic Business


Semiconductor Industry Growth Rates

Source: http://www.icinsight.com/ (McClean Report)


More Demand for EDA

Source: http://www.edat.com/edac

CA

E =

Com

pute

r Aid

ed E

ngin

eerin

g


Growth in System Size

Source: http://www.edat.com/edac

CA

GR

= C

om

pou

nd A

nnu

al G

row

th R

ate


Example: Intel Processor Sizes

Source: http://www.intel.com/

Intel386TM DXProcessor

Intel486TM DXProcessor

Pentium® Processor

Pentium® Pro &Pentium® II Processors

1.5 1.0 0.8 0.6 0.35 0.25Silicon ProcessTechnology


Section Outline



•Chip implementation methodologies



Implementation Methodologies

[© Prentice Hall]

Digital Circuit Implementation Approaches

Custom Semi-custom

Cell-Based Array-Based

Standard Cells Macro Cells Pre-diffused Pre-wired(FPGA)Compiled Cells (Gate Arrays)

Semi customCustom

Digital Ckt Implementation Approaches


Custom Design

• Using Magic we can get exactly what we want.

• However: Complex to design Takes weeks to

fabricate High design costs High overhead (non-

recurring – NRE) costs

How do we automate the mapping? [© Hauck]


Standard Cells• Develop predefined implementations of basic gates

with standard form-factor

[© Hauck]


Standard Cells

• Use regular layout• Can automate the mapping process, but

Takes weeks to fabricate No economies of scale PWR

GND

CELL1

CELL2

CELL3

CELL4

CELL5

CELL6

CELL8

CELL7

CELL10

CELL9

CELL16

CELL15

CELL14

CELL11

CELL12

CELL13

ROUTING

CellsROUTING

PWR

GND

PWR

GND

CellsROUTINGCells

ROUTING

CellsROUTING

[© Hauck]


Combined Standard Cell and Full Custom

Use full custom for regular structures & critical paths

Standard cells handle complex logic &non-critical logic

[© Hauck]


Mask-Programmable Gate Array (MPGA)

• Prefabricate all but the metal layers

[© Hauck]


Sea-of-Gates (SOG)

• Prefabricate all but the metal layers and the contacts

[© Hauck]


Discrete Components

• Prefabricate lots of small, simple parts. Wire them together.

D Q

D Q

D Q

DQ

DQ

DQ

[© Hauck]


Programmable Logic Devices

• Categories of prewired arrays (or field-programmable devices): Fuse-based (program-once) Non-volatile EPROM based RAM based

• Recently: VPGA (Via-Programmable Gate Array) Structured ASIC

[© Prentice-Hall]



[© Prentice-Hall]

PLA PROM PAL


Fabrication Process Revisited

• Speed up fabrication & get economies of scale by prefabricating some layers

n-SUBSTRATE

(a) field oxide etching

n-SUBSTRATEp-WELL

(b) p-well diffusion

n-SUBSTRATEp-WELL

(c) field oxide etching

n-SUBSTRATEp-WELL

(d) gate oxidation

n-SUBSTRATEp-WELL

(e) polysilicon definition

n-SUBSTRATEp-WELL

p+ p+

(f) p-plus diffusion

n-SUBSTRATEp-WELL

n+ n+p+ p+

(g) n-plus diffusion

n-SUBSTRATEp-WELL

n+ n+p+ p+

(h) oxide growth

n-SUBSTRATEp-WELL

n+ n+p+ p+

(i) contact cuts (j) metalization

p-WELLn+ n+p+ p+

n-SUBSTRATE

[© Hauck]


Programming Technologies

• Mask-programmed

• Antifuse

• EPROM• EEPROM

• SRAM

n+ drainn+ source

P-Type Silicon

access gate floating gate

PolysiliconField Oxide

N+ diffusionONO

Dielectric

Q

~QWrite

[© Hauck]


RAMs, ROMs

• Given a RAM/ROM with 8k memory locations, in 1k*8bit organization 10 address lines Can implement 8 arbitrary 10-input functions

(but inefficiently)

ROM

000001010011100101110111

I1I2I3

A B C D E F G H

[© Hauck]


Field Programmable Gate Arrays (FPGAs)

• Logic cells embedded in a general routing structure

• Logic cells usually contain: 5-input function

calculator Flip-flops

• All features electronically (re)programmable

RAMRAMRAMRAMRAM

RAMRAMRAMRAMRAM

AMM

[© Hauck]


Multi-Mode SystemsTektronix PhaserCard printer controllers

Different configurations for different printers

Andromeda Systems disk controllerField upgrades performed by modem

Radius pivoting monitorDifferent configurations forlandscape & portrait

Honeywell tape driveDifferent configurations forread & write operations

FPGA

ROM

Config1Config2Config3Config4

[© Hauck]


Microprocessors & Microcontrollers

• Microcontrollers are simple 1-chip computers optimized for embedded control

• Cheap, ubiquitous, can handle complex control flow (relatively slowly)

CPU

RAM ROM

I/O Sensor

Actuator

[© Hauck]


Digital Signal Processors (DSPs)

• Fast multiply-accumulate for signal filtering, etc.

DATARAM

REGISTER

ALU

MUX

MULTIPLIER

ACCUMULATOR

SHIFTER

SHIFTER

REGISTERMUX

REGISTER

MUX

PCPROGRAM

CONTROLLER

I/OCONTROLLER

PROGRAMROM

Data Bus

ProgramBus

Address

Address

[© Hauck]


Digital Logic Implementation Alternatives

o1

i6i5i4i3i2i1

Discrete Components


Gate Arrays

Field-Programmable Gate Arrays (FPGAs)

Full Custom

Standard Cells

PWR

GND

CELL1

CELL2

CELL3

CELL4

CELL5

CELL6

CELL8

CELL7

CELL10

CELL9

PWR

GND


To Probe Further...

• D. G. Chinnery and K. Keutzer,“Closing the Gap Between ASIC and Custom: An ASIC Perspective”, Design Automation Conference (DAC), pp. 637-642, 2000.


Section Outline




•Design methodologies


IC Design Steps (cont.)

SpecificationsSpecifications High-levelDescriptionHigh-level

DescriptionStructural


Description

BehavioralVHDL, C

StructuralVHDL

Figs. [©Sherwani]


Packaging Fabri-cation

PhysicalDesign

TechnologyMapping

Synthesis





Description

Placed& RoutedDesign


X=(AB*CD)+ (A+D)+(A(B+C))Y = (A(B+C)+AC+ D+A(BC+D))

Figs. [©Sherwani]

Gate-levelDesign

Gate-levelDesign

LogicDescription

LogicDescription


Packaging Fabri-cation

PhysicalDesign

TechnologyMapping

Synthesis





Description



Gate-levelDesign

Gate-levelDesign

LogicDescription

LogicDescription


The Big Picture: IC Design Methods

Full Custom

ASIC – StandardCell Design

Standard CellLibrary Design

RTL-Level Design

DesignMethods

Cost /Development

Time

Quality % Companiesinvolved


Optimization: Levels of Abstraction

• Algorithmic Encoding data, computation

scheduling, balancing delays of components, etc.

• Gate-level Reduce fan-out, capacitance Gate duplication, buffer

insertion

• Layout Move transistors driven by

late inputs closer to the output

Eff

ecti

ven

ess

Level of

deta

il


Where Is This Course in the Big Picture?

• VLSI related courses:VLSI CAD VLSI Design Others

EE 4301Digital Design

With Programmable Logic

EE 5329VLSI Digital

Signal Processing Systems

EE 5333Analog

Integrated CircuitDesign

EE 5549Digital

Signal ProcessingStructures for VLSI

EE 5323VLSI Design I

EE 5324VLSI Design II

EE 5301VLSI DesignAutomation I

EE 5302VLSI Design

Automation II


Full Custom Design

Structural/RTL Description

Mem

Ctrl

Comp.Unit

RegFile

...

Layouts [© Prentice Hall]

Component Design

Floorplan [©Sherwani]

Place & Route

A/D

PLA

I/Ocomp

RAM


ASIC DesignStructural/

RTL Description

Mem

Ctrl

Comp.Unit

RegFile

HDL Programming

P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0';

P_Inp: process (Reset, Clock) begin if (Reset = '1') then sum <= ( others => '0' ); input_nums_read <= '0'; sum_ready <= '0';

add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o);Mult_i1 <= sum_o(7 downto 0);

add82 : kadd8 port map ( a => add_i1, b => add_i2, ci => carry, s => sum_o);Mult_i1 <= sum_o(7 downto 0);

Floorplan [©Sherwani]C D

A B

Cell library

D C C B

A C C

D C D B

BCCC


More Issues to Consider

• Area/speed trade-off• Power consumption a new factor

0 10 20

N

0

20

40

60

80

0 10 20N

0

0.2

0.4

look-ahead

select

bypassmanchester

mirrorstatic

manchester

look-ahead

select

static

mirror

bypass

[© Prentice Hall]

t p(s

ec)

Are

a (

mm

2)


More Issues to Consider (cont.)

• Aspect ratio, area budgets, datapath layout• Power and clock grid

Well

Control wires (M1)

Well

Wires (M1)

GND VDDGND

GND

VDD

GND

Approach I —Signal and power lines parallel

Approach II —Signal and power lines perpendicular

Figures: [© Prentice Hall]Si

gnal

wir

es (

M2)

Sign

al w

ires

(M

2)


Datapath Layout Example: Adder

[WE92] p.521

Standard cell layout Bit-slice cell layout


Read/write

Architecture of a CPU

Flags:overflow,zero, etc.

function

Mem

Control

Data pathRegister

File


Arithmetic and Logic Unit (ALU)

• Functions Arithmetic (add, sub, inc, dec) Logic (and, or, not, xor) Comparison (<, >, <=, >=, !=)

• Control signals Function selection Operation mode (signed, unsigned)

• Output Operation result (data) Flags (overflow, zero, negative)


Simple ALU Example

Bit 3

Bit 2

Bit 1

Bit 0

Tile identical processing elements

[© Prentice Hall]

Reg

iste

r

Ad

der

Sh

ifte

r

Mu

ltip

lexer

Data

in

Data

Ou

t

Control


EE 5324 – VLSI Design IIEE 5324 – VLSI Design II

Kia Bazargan

University of Minnesota

Part I, Appendix: FPGA ArchitecturesPart I, Appendix: FPGA Architectures


FPGA Architecture - Layout

• Island FPGAs Array of functional units Horizontal and vertical

routing channels connecting the functional units

Versatile switch boxes Example: Xilinx, Altera

• Row-based FPGAs Like standard cell design Rows of logic blocks Routing channels (fixed

width) between rows of logic Example: Actel FPGAs


FPGA Architecture: Functional Units• Functional units

RAM blocks (Xilinx):implement function truth table

Multiplexers (Actel):build Boolean functions using muxes

Logic gates, flip-flops:Such as carry chains. Used for high-performance computations

Addresslines(input)

output


Programmable Switch Elements

• Used in connecting: The I/O of functional

units to the wires

A horizontal wire to a vertical wire

Two wire segments to form a longer wire segment


Programmable Switch Elements: Implementation

• SRAM connected to the gate of a transistor (Xilinx)

• Fuse / Anti Fuse (Actel)

symbol implementation

symbol implementation

Note: Switches degrade thesignals slow down


Routing Channels• Note: fixed channel widths (tracks)• Should “predict” all possible connectivity

requirements when designing the FPGA chip• Channel -> track -> segment

• Segment length? Long: carry the signal longer,

less “concatenation” switches, but might waste track

Short: local connections, slow for longer connections

channeltrack

segment


Routing Channels (cont.)

• Segment offset?

• Hierarchy?


Switch Boxes

• Ideally, provide switches for all possible connections

• Trade-off: Too many switches:

o Large areao Complex to program

Too few switches:o Cannot route signals

Xilinx 4000

One possiblesolution


Operation Example

• 4-bit ripple-carry adder


- Chain all config bits in a shift register or use pipelining- Partition the elements into subsets, treat each as a memory block

- Consider the problem when designing the FPGA architecture- Carefully schedule the programming

- Yes! If two functional units drive same line- Avoid at architectural design or when prog

Programming• How to access all programmable elements?

Pin limitation

Feasibility of access (Actel example)

• Are there “invalid” configurations?


Programming (cont.)

• Too much detail! (tens of bits for each cell/switch block) Automated placement, routing and

programming Design a simple structure so that tools can

handle

• Partially reconfigurable? Extra control circuitry, more flexibility Runtime reconfigurable? (avoid conflicts with

running components)


Pros and Cons

• General architecture Slower than ASIC Less logic capacity

(solution: reuse silicon area through reconfiguration)

Flexible

• Customization helps Instantiate many small processing elements

parallel processing Some operations faster

(e.g., constant multiplication, bit-wise operations) More operations in parallel

reduce clock speed reduce power consumption


New Challenges

• Balance between elements Data memory Configuration memory Special-purpose functional units Fine- vs. coarse-grain functional units

• Communication bandwidth• Fast automatic tools• Versatile libraries

Documents

Spring 2006EE 5324 - VLSI Design II - © Kia Bazargan 1 EE 5324 – VLSI Design II Kia Bazargan University of Minnesota Part I: Introduction