Upload
elwin-shaw
View
215
Download
0
Embed Size (px)
Citation preview
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 1
ECE 747 ECE 747 Digital Signal Processing Digital Signal Processing
ArchitectureArchitecture
SoC Lecture – Working with SoC Lecture – Working with Analog-to-Digital ConvertersAnalog-to-Digital Converters
April 17, 2007April 17, 2007W. Rhett Davis W. Rhett Davis
NC State UniversityNC State University
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 2
Today’s Lecture
Introduction
Effective Number of Bits (ENOB)
Choosing the right ADC
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 3
Introduction
Thus far, we have focused on finding maximum and mean-square error (MSE) for our architectures.
How does this error relate to the real world (i.e. analog circuits)?
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 4
Signal-to-Noise Ratio Signal-to-Noise Ratio
(SNR) – Ratio of signal power to noise power
Typically, the performance of a system is specified in terms of SNR
How do we translate SNR into bits?
How do we translate MSE into SNR?
Example:BER vs. SNR curves for
a MIMO receiverSource: Ravi Jenkal
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 5
Modeling SNR What is the noise in the SNR?
» Typically band-limited additive white Gaussian noise
How do we model SNR?» Typically use a Gaussian
random variable added to the input of the system
What scaling factor (K) do we use?» K should be equal to the
standard deviation of the random variable, which is the square root of the variance
» Note that the power of a Gaussian random variable is equal to the variance
» For a discrete time systems, assume without loss of generality that T=1
T
NdfNP
T
T
noise0
)2/(1
)2/(1
0
T
NrmsVnoise
0)(
S(f)
f1/(2T)-1/(2T)
N0
e(n)K1*randn()
x(n) H(z) y(n)
01 NK
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 6
Today’s Lecture
Introduction
Effective Number of Bits (ENOB)
Choosing the right ADC
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 7
Noise in ADCs
Analog-to-Digital Converters (ADCs) typically measure their noise performance in Effective Number of Bits (ENOB)
Sources of Noise:» Quantization noise» Analog circuit noise (thermal, shot, 1/f, etc.)» Distortion (not random, but can be modeled
as noise)
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 8
Quantization Noise
Source: Walden, JSAC1999 [1]
1222
1
2
1)(
0
2
N
FST
NFS
noise
Vdt
T
tV
TrmsV
2224
1)/2cos(
2
1)(
2
0
2
FSFST
FSsignal
VTV
TdtTt
V
TrmsV
76.102.62
62log20
122
22log20
)(
)(log20)( 101010
N
V
V
rmsV
rmsVdBSNR
N
FS
NFS
noise
signal
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 9
Example #1
To achieve an SNR of 45 dB, what is the minimum number of bits required?
But what about the analog circuit noise and distortion in the ADC?
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 10
ADC Noise Measurements SNDR – Signal-to-Noise Distortion Ratio
» Ratio of signal power to noise power and harmonic distortion SFDR – Spur-Free Dynamic Range
» Ratio of largest harmonic amplitude to carrier amplitude Example: 50 MS/s ADC with 20 MHz tone
» SNDR = 54.6 dB, SFDR = 69 dB» Source: Ryu, Song, & Bacrania, ISSCC 2006
SFDR
} (integral)SNDR
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 11
Effective Number of Bits (ENOB)
Typically, the largest sinusoid signal possible is used to measure SNDR, and thereforeENOB = [SNDR(dB)-1.76]/6.02
ENOB is a better measure of how many bits you’re actually getting
SFDR is best used when the application is particularly sensitive to distortion
SFDR bits = [SFDR(dB)-1.76]/6.02
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 12
SNDR/SFDR vs. Stated Bits Plots from Walden [1] show that ENOB is
always less than the stated number of bits, but SFDR bits can be more or less than stated number (slightly more, on average)
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 13
Example #2
Design a System with an SNR of 63 dB» Find ENOB
Suppose that the largest input signal is sin(ωt)+cos(ωt)» Find K1
K2
e(n)K1*randn()
x(n)
quantizeround()
H(z) y(n)
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 14
Example #2
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 15
Questions For Vsignal(rms), we used a sinusoid with amplitude equal
to the max value of the input signal, rather than integrate the input signal itself. Why?
Also, this covers noise for the ADC, but what about the rest of the analog front-end?
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 16
Example #3
Suppose the same SNR and input signal from the last example
Suppose also the following:» the number of stated bits is 12» a 3-σ noise margin should be added to the swing
Find K2
K2
e(n)K1*randn()
x(n)
quantizeround()
H(z) y(n)
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 17
Example #3
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 18
Today’s Lecture
Introduction
Effective Number of Bits (ENOB)
Choosing the right ADC
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 19
Why do we care?
We may make any assumption we like when designing a system about how many bits we have and what the SNR is…
…but how do we know if such an ADC even exists? How do we know if it is feasible to build the system we want to build?
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 20
Limits on ADC Performance
Aperture Jitter [2]» Determined by the amount of jitter a in the sample
clock
» Main limitation of ADC performance» Leads to well-know figure of merit P=2ENOB*fsamp
Other contributors» Thermal noise (resistance in amplifier)» Comparator Ambiguity (delay in comparator, limited
by transition frequency fT)» Heisenberg Uncertainty Principle
asampfdBSANR
2
1log20)( 10
945.21
log322.3 10
asamp
aperture fB
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 21
Summary of ADC Performance [1]
Walden showed that P increase from roughly 1x1011 in 1989 to 4x1011 in 1997 [1]
One converter shown in 2006 ISSCC with P of 2.1x1012 Other limits on performance appear to less of a limiting factor [2]
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 22
Selecting an ADC
Different ADC architectures offer different bits/sample rates and power consumption
It’s helpful to review the most common types so that you navigate the papers and know what’s impressive (and what’s not)» Flash» Pipeline» Successive Approximation» Over-sampled
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 23
Flash & Pipeline ADC
Flash ADC» Also called “Direct-
Conversion” ADC» Entire conversion
performed at once in parallel
» Very fast, very large, very power-hungry
Pipeline ADC» Like Flash, but broken into
steps with DAC betweenSource:Maxim
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 24
Successive-Approximation ADC
Successive-Approximation Register (SAR) searches for digital value
Digital-to-Analog Converter DAC produces analog signal
Comparator compares DAC output to input voltage to produce control signal for next approximation
When done, SAR signals end of conversion (EOC) Source:
Wikipedia
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 25
Over-sampled ADC Also called ΔΣ- or ΣΔ-ADC
Signal is over-sampled and converted to a smaller number of bits
A “decimation-filter” is used to achieve a larger number of bits at a lower rate
An Over-sampling ratio (OSR) of ~60 is common
Can be confusing to determine sample-rate (input or output?)
Source:Wikipedia
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 26
Comparison of ADC Performance
Source: Le, Rondeau, & Reed, Signal Processing Magazine 2005 [2]
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 27
Comparison of ADC Power Source: Le, Rondeau, & Reed,
Signal Processing Magazine 2005 [2]
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 28
Power Figure-of-Merit (F) F=(2ENOB*fsamp)/Power=P/Power
Source: Le, Rondeau, & Reed, Signal Processing Magazine 2005 [2]
Spring 2007W. Rhett Davis NC State University ECE 747 Slide 29
References
[1] R. H. Walden, “Analog-to-Digital Converter Survey and Analysis,” IEEE Journal on Selected Areas in Communications, vol. 17, no. 4, April 1999.
[2] B. Le, T. W. Rondeau, J. H. Reed, C. W. Bostian, “Analog-to-Digital Converters: A Review of the Past, Present, and Future,” IEEE Signal Processing Magazine, Nov. 2005.