17Spring 2003 Yield Management Solutions

Breaking Through theCopper/Low-κ BarrierDefect Management in Copper DevicesPart 1: From Barrier/Seed ThroughPost-CMP Clean

Paul Marella, Steve Fanelli, Vikas Sachan, and Dave Coldren, KLA-TencorCorporation

While copper interconnects and low-κ dielectrics represent enabling technologiesfor current and future device performance, their use is accompanied by someunique and difficult challenges. Surface and sub-surface interconnect voids, pluscopper CMP slurry and clean residues are among the most common types of defectsfound in the part of the copper process that begins with barrier and seed deposition,encompasses copper electroplating, annealing, and chemical mechanical polishing(CMP), and ends with post-CMP and backside cleaning. The new defect Paretothey create is founded on the unique material properties of copper and low-κdielectrics and upon the architecture of the damascene process required to utilizethese materials. These yield and reliability challenges are expected to deepen asdevices evolve past the 130 nm node.

IntroductionThe performance enhancements granted by copper and low-κ dielectrics comeat a cost. The materials are relatively new to chip manufacturers, and theirproperties present some challenges, especially in the areas of interconnect yieldand reliability.1 New defect types are arising during photolithography andetch, as well as during deposition, anneal, polish and cleaning.

Despite the difficulties, all of the world’s major chip manufacturers have incor-porated, or are in the process of incorporating, copper/low-κ interconnectsinto their devices. Microprocessors with copper are in production; copperASICs are mostly found in pilot-lines, and copper DRAMs are in the R & Dlabs. In some leading technology devices, copper and low-κ have completelyreplaced aluminum and oxide processes at every level. Copper/low-κ technologynow dominates 130 nm devices, and will be crucial to the successful intro-duction of 90 nm and 65 nm devices. The use of copper and low-κ materials

SSttoorryyCover

18 Spring 2003 Yield Management Solutions

C O V E R S T O R Y

Defect type Process Step Impact Image

Voids Barrier/seed deposition, Risk of opens in vias andECD, anneal trenches—device failure

Protrusions ECD Typically nuisance – CMPmay eliminate

Copper hillocks ECD, anneal Nuisance

Remaining Metal CMP Interconnect shorts

Underpolish of CMP ShortsCopper or barrier

Overpolish CMP Opens or resistive leakage ofcopper into dielectric; thinningof stack accompanied by lowerdevice yield

Scratches CMP Microscratches are usually considerednuisance but larger scratches maylead to opens or shorts

Embedded CMP Electrical shorts; planarity loss Contamination at the dielectric level

Chatter marks CMP May affect subsequentmetallization layer; excessmetal may generate shorts

Dielectric rip-outs CMP Next-level shorts

Peeling (adhesion) CMP Scratching whole wafer – device failure

Corrosion CMP clean Opens or reliability issues

Residual Slurry CMP and CMP Clean Affects subsequent metallizationlayer: blocked etch

Clean residues CMP clean Affects subsequent metallizationlayer: blocked etch

Table I. Common defect types in the copper/low-κ process.

19Spring 2003 Yield Management Solutions

copper into neighboring dielectricsand silicon, potentially poisoningthe devices by causing shorts orleaks. Thus, with copper devices, theintegrity of the metal/dielectricinterface is critical. It is necessary tointroduce a more refractive barriermetal between the dielectric and thecopper layers to encapsulate theinterconnects adequately. Typically atantalum/tantalum nitride (Ta/TaN)bilayer is used, a material that hasshown excellent barrier propertiesup to 550 Celsius. If the barrier cov-erage is incomplete, or adhesionbetween the barrier and the dielec-tric is imperfect, copper may leakinto the dielectric and cause perfor-mance issues, reliability issues orfailure. Copper diffusion may alsoleave behind voids.

After the barrier layer is deposited,typically by physical vapor deposi-tion (PVD), a copper seed layer isdeposited without breaking vacuum.The seed layer is necessary to assureadequate adhesion of the copper tothe barrier, with good continuityand a minimum of voids. However,the seed layer represents an addi-

tional process step compared withaluminum-based devices, and anyadditional step is accompanied bydefects (Figure 1). If the seed layer isnot continuous, the conductive pathfrom the edge of the wafer to thecenter, essential for copper electro-plating, is interrupted. As a result,tiny copper voids may be createdduring ECD. During annealing — orlater, as the device ages — electromi-gration can drive the small voids tocombine. Such voids represent thebiggest yield and reliability issue inthese leading-edge devices.1, 3

A remedy for a discontinuous seedlayer is to deposit a thicker seedlayer. But with the high aspect ratiostructures typically found in 130 nmdevices and expected in futuredevices, a thicker seed layer meansthat the via opening could be nar-rowed or even pinched off from seed-layer overhang effects. A narrowopening to the via complicates copperfill, and large buried voids may result.

Voids are also introduced through themechanism of stress migration. Filmstress, induced by repeated thermal

is also predicted to lead 300 mmwafer production in the near future.Despite the complexity and scalingof this leading-edge technology,expectations are that defect densitiesshould be the same or better than inprevious-generation devices.

One of the keys to successful pro-duction of copper/low-κ devices isappropriate defect management.This paper is the first in a three-partseries that will address defect moni-toring from barrier/seed throughcleaning, defect monitoring in thephoto area, and inline electrical defectmonitoring for copper/low-κ devices.

New materials, newdefect typesWithin the scope of this paper severalcritical process steps are considered:PVD barrier and seed deposition,copper electroplating or electro-chemical deposition (ECD), anneal-ing, CMP, post-CMP cleaning, andfinally a backside clean. Commondefect types associated with theseprocesses are given in Table I.

While some of these defect types arewell known from aluminum/oxideprocesses, many are new. What is itabout copper and/or low-κ thathas introduced these defects?Insight can be gained by examiningsome of the fundamental materialproperties of copper and low-κ insu-lators, and contrasting them withthe better-known materials of aluminum and oxide dielectrics.

Besides its superior conductivity,copper is reputed to offer betterelectromigration (EM) resistancethan aluminum. In reality copperoffers different EM resistance from thatof aluminum. Copper EM processesare dominated by surface and inter-face diffusion, while aluminum EMprocesses are dominated by grain-boundary diffusion. Electromigrationin copper can result in diffusion of

C O V E R S T O R Y

Figure 1. Defect examples associated with barrier deposition or dielectric/barrier interface.

Figure 2. Void examples in interconnect.

20 Spring 2003 Yield Management Solutions

conditions affect the texture of thecopper film during electroplating,which in turn affects the strength ofthe interface. Without adequateadhesion between copper and barriermetal, or between barrier metal andlow-κ layers, or between copper andcap layers, CMP may tear apart thestack, causing local dielectric rip-outor delamination, or fissures at theinterfaces (Figure 5). Exacerbatingthis problem is the low Young’smodulus of the low-κ materials,which causes them to flake easily.

A final and very important differ-ence between copper/low-κ devicesand their aluminum/oxide predeces-sors is that the new devices are fabri-cated using damascene processes,

cycling of the copper films to accom-modate deposition and annealing ofsubsequent layers, can also causesmall voids to coalesce and migrate tothe bottom of the via. Most of thesevoids are confined to the copper inter-connect regions (Figure 2) and relateto the quality of the copper-tantaluminterfaces, but the use of low-κdielectrics, having different coeffi-cients of thermal expansion fromtheir oxide predecessors, can worsenstress management issues.

Film stress gradients can also result inthe formation of copper hillocks. Thisdefect type is particularly of concernwhen the temperature is cycled priorto capping the annealed copper witha SiN or SiC etch stop layer. Whilecopper hillocks are not usually ayield-limiting defect, they add nui-sance defects to the total defect count,lowering the signal-to-noise ratio.

The native oxides of copper are quitedifferent from aluminum oxide, andthis disparity leads to significant dif-ferences in the corrosion propertiesof the two metals. Copper is astronger oxidizing agent than alu-minum and forms a relatively softand porous layer of hydrated oxides.In contrast, aluminum forms a thinand tough protective layer of Al2O3,which is self-limiting in thickness.Plasma treatments must be used toremove the surface oxides of copperbefore the metal is capped; further-more, the time lag between copperCMP and cap layer deposition mustbe kept to a minimum unless thewafers are in protective pods. DuringCMP, corrosion can occur when thechemicals in the slurry or the cleaningsolutions interact with the bare coppersurface. Corrosion and oxidationdefects affect the electrical integrityof the interconnects (Figure 3).

Low-κ materials have a stronger ten-dency to interact with various sur-face functional groups during thenumerous etch, deposition, polish,

and clean steps, resulting in organicresidues unfamiliar from last-gener-ation dielectric processes (Figure 4).Residue removal — of metal, slurryor organic material — is more diffi-cult with low-κ dielectrics becausetheir surface wetting properties aremore demanding, and less aggressivechemistries must be used.1

Adhesion can be challenging incopper/low-κ devices because newmaterials necessitate new under-standing of the physical chemistry ofinteracting neighboring layers.Adhesion is also a more difficultproblem because the number ofinterfaces has been increased by therequirement for a seed layer for eachcopper metallization. Barrier-seed

Figure 3. Copper corrosion and oxidation defects.

Figure 4. Organic residue defects.

Figure 5. Delamination, dielectric rip-out, and

interface fissure defects.

C O V E R S T O R Y

21Spring 2003 Yield Management Solutions

Common practices for copper defect controlThe number and variety of newdefect types arising during copperprocessing is remarkable. Criticalprocessing steps use new materials,processes and equipment. New pro-cessing parameters are required forECD and anneal. The CMP consum-ables set is new — slurry, pad, andclean chemistry — to address newrequirements for polishing copperand low-κ materials.

Defect control in such an environ-ment requires a well-plannedmethodology and precisely the rightset of inspection tools. Because cop-per/low-κ is a relatively immatureprocess, single-wafer excursions

dominate. Furthermore, the ratio ofnuisance defects to yield-limitingdefects is high. In this realm of defectmanagement, extensive samplingis necessary for adequate excursionmonitoring. Also, tracking defectsby type is critical to yield learningand tool monitoring in the presenceof high nuisance counts.

While double-darkfield inspection isgenerally preferred for film levels,such as interlayer diectric and copperECD,8 a study of several of the mostsuccessful foundries and integrateddevice manufacturer fabs in the US,Asia and Europe, has shown that themost common tool set for successfuldefect control at copper CMP is a mixof high resolution imaging and dou-ble-darkfield inspection. During thedevelopment and ramp phases, high-resolution imaging is used for a greaterpercentage of inspections. As yieldlearning progresses and wafer sam-pling demands increase, double-dark-field inspection is increasingly used tomeet the requirement for higherthroughput (Table II).8

Post copper CMP, generally twowafers per lot are inspected in bothlogic and memory areas to measureCMP and ECD defectivity. At thesame time, the substantial wafer-to-wafer variation from under-polish andresidue defects drives the need for highwithin-lot wafer sampling. Here,

while the older devices are fabricatedusing subtractive processes, such asreactive ion etch (RIE) (Figure 6).Because many acids do not react asreadily with copper as they do withaluminum, a suitable copper etchchemistry has not been found. Thus,the industry has turned to single ordual damascene processes, based onprevious experience with tungstenlift-off of larger-geometry devices.

With single damascene, or the morecost-effective (but more difficult)dual-damascene process, the chal-lenge lies in filling a high-aspect-ratio cavity. The difference in archi-tecture between a damascene processand a subtractive process contributesto a change in the dominant defecttypes for each process. With RIE,particles that are left behind as con-taminants of the etch process orincompletely etched material, mayresult in shorts (Figure 7) — or theymay not cause a problem at all. Incontrast, particles left behind duringdielectric removal for the damasceneprocess will ultimately result invoids, especially harmful after thermalcycling or device aging causes thevoids to coalesce and migrate to thebottoms of the vias. Voids typically endup as opens. Complete opens will causedevice failure, while partial openswill have an impact on reliability.

C O V E R S T O R Y

50%

40%

30%

20%

10%

0%

Cu Dual-damascene(0.22µm, 5M)

YIELD DETERRENTS

OPEN

S

Void

s (Op

en)

Shor

ts

Misc

.

70%

60%

50%

40%

30%

20%

10%

0%

YIELD DETERRENTS

AI Subtractive(0.35µm-0.25µm, 3-4M)

OPEN

S

Shor

ts

Misc

.

Typical Yield Deterrents in Copper versus Aluminum Interconnects

Figure 6. Void formation is a major yield deterrent in copper devices.

Interconnect Solutions Defect Type Fault Mechanism

AI - subtractiveStatic,

on-surface

Dynamic,Sub-surface

Cu - damascene

OXIDE

OXIDECu

AI AI

Defect

Defect(can grow & migrate)

Particles SHORTS

Particles VOIDS

(opens)

Technology Changes Redefine Fault Mechanisms

Figure 7. The change from aluminum to copper technology has redefined defect mechanisms for

interconnects, requiring new yield management solutions.

22

double darkfield inspection is oftenchosen for its high throughput capa-bilities (Table III).8

Inline electrical testing using voltage-contrast mode on an e-beam inspec-tion system is essential for detectingburied voids — perhaps the most crit-ical defect type generated within thecopper process. This key technologywill be explored in a later article inthis series. The use of automatedmacro inspection, replacing manualinspection in the detection of grosspolish defects, will also be explored ina later article, as will the use of unpat-terned wafer inspection for tool quali-fication within the copper module.

Case studies Short-loop experiments of various kindstake place during the copper process,to work toward resolving defectproblems unique to copper/ low-κdevices. Once the common defect types

have been identified and sourced,mostly by the yield engineers, defectmanagement typically becomes the

Spring 2003 Yield Management Solutions

responsibility of the process engineers.The process engineers take ownershipof statistical process control (SPC)charts and control limits, and managethe defect excursions within theirmodule. By taking over the toolmonitoring, the process engineersfree the yield engineers to focus onprocess and inline monitoring.

Effective tool monitoring during thecopper process necessitates closelymonitoring each deposition, polishingand cleaning system. The inspectionsystem needs to be situated close to theprocess tools, not only for convenienceand to reduce response time to excur-sions, but also to minimize exposuretime for the copper layers before capping. Finally, contamination con-siderations often dictate that theinspection system be dedicated to thecopper area.

Texas Instruments in Dallas, Texas,described the detection of surface andsub-surface voids using optical and e-beam voltage contrast inspection,respectively, in a recent article. TI’sKilby Development Center (KFAB)used double-darkfield inspection to

C O V E R S T O R Y

Inspection e-beam High Double- Recommended TechnologyTechnology Resolution Darkfield

Imaging

Barrier Seed 0 1 4 Double-darkfield

Copper ECD 0 1 1 Double-darkfield

Copper CMP, M1-M2 3 7 3 High resolution imaging/e-beam

Copper CMP, M3+ 3 5 5 High resolution imaging/Double-darkfield/e-beam

4 Foundry and 4 Logic Fabs, 130 nm

Table II. Summary of technologies used by eight fabs to control defects in the copper process.

These fabs are at various points between yield ramp and production. Adapted from Reference 8.

RecommendedTechnology % Lots # Wafers/Lot % Wafer Area

Barrier/Seed Double-Darkfield 25-50 3-5 100

Copper ECD Double-Darkfield 50 3-5 100

Copper CMP, High Resolution 25-50 2 100M1-M2 Imaging

Copper CMP, M3+ Double-Darkfield 100 5-15 100

Typical Sample Plan

Table III. Summary of typical sampling plan recommended to control defects in the copper process

during ramp and production. Adapted from Reference 8.

Figure 8. KLA-Tencor’s AIT darkfield inspection was implemented post-ECD and post-CMP, and

utilized to partition the source of patterning and underlying defects.

Post

-CM

P Pa

reto

Void

Long

Pit

Part

icle

Scra

tch

Othe

r

Mis

sing

Mat

eria

l

70%60%50%40%30%20%10%

0

Post-ECD Post-CMPDarkfield Inspection Post-ECD and Post-CMP

ECD Void

ECD Void ECD Void

Void Long Pit

uncover a characteristic spatial patternof surface voids in the defect wafermaps after ECD, after CMP, and afterthe CMP clean, for a 130-nm copperdual-damascene device. This studyrevealed that the root cause of thevoids was in the ECD; the voids weresubsequently enlarged and uncoveredby CMP and the post-CMP clean(Figure 8). TI developed an out-of-control protocol, and transferred theprocess to production.3

A second experiment by the samegroup used an inline e-beam inspec-tion system in voltage contrast modeto detect sub-surface voids that were

23Spring 2003 Yield Management Solutions

causing yield problems.Screening the pre-ECDseed conditioning, thepre-ECD rinse condi-tioning, and the post-ECD anneal, they dis-covered that the annealwas the problematic area(Figure 9). By changingthe anneal conditionsthey reduced the sub-surface void formation toacceptable levels.3

Infineon Technologies inDresden, Germany, useddouble-darkfield inspec-tion to systematicallyinvestigate the effective-ness of various post oxide

CMP cleaning process parameters onmemory products, and their potentialimpact on final device yield (Figure10). As the post-CMP rinse procedurewas varied, electrical characterizationshowed post-CMP defects primarilyaffected the wafer’s subsequent met-allization layer. Slurry agglomera-tion defects had the greatest impacton yield, causing shorts betweenmetal lines. Because nuisance defectsshowed the greatest variation innumber as the rinse parameters werevaried, tracking by total defectcount would not have been useful.Instead, tracking by defect type

was critical, and theinspector’s Real TimeClassification option(RTC) was able to distin-guish “killer” slurryagglomeration defectsfrom nuisance defects(flat, chopstick-shapedsilicon oxide, and micro-scratches) with noimpact on throughput(Figure 11). Infineondetermined the optimumcleaning rinse solutionand process time — andthe result proved to be acompromise between

maximizing device yield and mini-mizing both the process time and costof consumables.6

TI DMOS 6, TI’s first 300 mm fab, wasinterested in ramping their 130 nmcopper devices on 300 mm wafersquickly. They faced some challenges,particularly because they werebringing up new tools (Figure 12).In phase I (process qualification andintegration) they used the KLA-Tencor2350, high resolution imaginginspector to determine that morethan 30% of the die on the waferwere affected by copper seamdefects, post CMP. The defect pro-vided problems for vias landing onthe leads, and for line resistivity(Figure 13). DMOS6 was able tooptimize their CMP process andeliminate the galvanic corrosion thatwas responsible for the copper seamdefects.

In phase II (yield ramp) a missing-metal defect, detected post CMP byhigh resolution imaging, was affect-ing 3-5% of the die, with excursionsaffecting up to 20%. The source wasfound to be TaN barrier particlesinterfering with the subsequent cop-per plating. After improvements to

C O V E R S T O R Y

Total Defect Count

eS20XP Defect Scan Summary

Anneal "A"

Anneal "B"

Wafer Map

eS20XP Via Void Evaluation

Figure 9. This summarizes the results of the second experiment,

which compared the effect of ECD pre-conditioning anneal,

pre-ECD rinse, and post-ECD anneal on copper voids. The

vast majority of defects found by the KLA-Tencor eS20XP were

sub-surface defects as opposed to surface or particle defects.

Figure 11. Images by optical microscope and

SEM of typical defect types: Flat, chopstick

shaped particles (top), which are regarded as

nuisance defects, and spherelike slurry agglom-

eration (bottom), which affect device yield.

Bin 72 Bin 82 Bin 92

Bin 91Bin 81Bin 71

Slurry conglomerates

Flat geometrical particles

MultiChannelDetection

SingleChannelDetection

AnomalousPixel Area

0 100 800

Scratches

Figure 10. Defect binning scheme set up using the AIT’s RTC

option. The numbers 7, 8, and 9 represent size characterization;

the second digits, 1 and 2, represent single-and multichannel

detection, respectively.

24

the barrier metal process, the TaNparticles were brought under control.

High resolution imaging was alsothe technology of choice for copperCMP monitoring during phase III(yield entitlement). A new defectsignature was detected on a set ofwafer maps, and was traced to particlescoming from degraded CMP brushes.After the brush was replaced, thedefect source was eliminated.

During each of these phases, e-beaminspection with the KLA-TencoreS20XP was used to complementthe high resolution imaging, withsuccess at each phase. TI DMOS 6plans to use a similar high resolutionimaging and e-beam inspectionstrategy to bring up their 100 nmprocess.9

AMD Fab 30, described an effectivetool monitoring strategy for theircopper CMP module, in which bothsingle-wafer excursions and highnuisance rates — especially in the formof microscratches — were present.They used KLA-Tencor’s AIT, a highthroughput, double-darkfield inspec-tion system equipped with RTC andHigh Resolution Defect Classifica-tion (HRDC) to monitor all copperlayers for their most critical defecttypes: residual copper, copper precipitates, copper corrosion andslurry residue, and separate thesefrom defect types of less importance:

microscratches, previous-layer defects,particles and pattern defects. RTCwas able to accomplish this discrim-ination with no discernible impacton throughput. A new feature called“trigger sampling” directed samplesof defect images from wafers flaggedby RTC, to undergo HRDC. HRDCexamined a number of defects on thewafer to identify defects of interest(Figure 14). Whenever the popula-tion of any of these defect typesexceeded its (layer-dependent)threshold, HRDC declared the toolout of control, and appropriate cor-rective measures were taken.5

AMD feels this is a practical solutionfor their “high volume high inspec-

Spring 2003 Yield Management Solutions

tion sample production facility.”They reported a cycle time improve-ment of 30% within the copperCMP module, a reduction in falseexcursions, faster time to results, anda higher capture rate of criticaldefect types. With this new method-ology, AMD Fab 30 has been run-ning in production since November2001, and considers the methodolo-gy part of their process of record.5

TI KFAB was using the AIT double-darkfield inspection system to moni-tor full lots of a 130 nm copper sin-gle-damascene test-chip device, postCMP, when they discovered anexcursion. Further analysis showedthat most defects were coming fromslot 24, the first wafer going into theCMP polisher, and they were able toaddress the problem (Figure 15). Inthis case, it was essential that theywere monitoring the whole lot, or theywould have had much more difficultyuncovering this first-wafer effect.7

TI’s general tool monitoring strategy isto dedicate the AIT double-darkfieldinspection system to the copper CMParea in the copper “wet room,” andset up simple, speedy (40 wph) scansafter via and trench CMP. They userecipes optimized for CMP surface

C O V E R S T O R Y

Inspection Strategy for New Technology/Ramp

Finger printing,

Max sensitivity -- Look for unknowns

(Qualifications / Integration issues)

EffectivenessPhase 1/Transfer

YsYr - Integration

Defect reduction - DSA

Inspection plan - Sample Planner

RationalizationPhase 2/Ramp Excursion Control - Yr

EfficiencyPhase 3/Production

Yiel

d or

Out

put

Figure 12. The key for DMOS6 in the yield ramp were to minimize risk to qualification delays

and to get up the yield curve as fast as possible.

Typical wafer map showing the defect distribution.

Typical SEM image of the seam defect.

Phase I Example: Copper Seam Defect

Figure 13. Phase I, Copper Seam defect. This systematic defect was detected on the 2350, post

copper CMP1.

inspection as wafer samplingdemands increase (requiring higherthroughput inspection) has been asuccessful tool utilization strategy inmany fabs.

What’s ahead?Copper and low-κ dielectrics areenabling technologies for futureproduct scaling. Yet, as criticaldimensions are pushed down to

100 nm and beyond, some of the cur-rent challenges in electromigrationand reliability are likely to becomeincreasingly difficult. And newissues will arise. Karen Maex, strate-gic research coordinator for intercon-nect technologies at IMEC, recentlydiscussed concerns about the specificresistivity, porosity of the low-κdielectrics, and the lack of an effec-tive test for electromigration.2

1

defects, which together with RTC,minimize the effects of nuisancecounts. They inspect full lots, corre-late in-line defects to electrical data,reduce outliers, and work to under-stand the process variation. The maindefect type at via CMP has been slur-ry residue, while CMP scratches havedominated at trench CMP. Whenexcursions are understood andbrought into control, TI reduces thesampling rate. This methodology hasdriven a dramatic yield improvementat trench, and a more modestimprovement at via. The methodolo-gy has also been implemented in TI’s300 mm fab.7

TI demonstrated the value of utilizingthe 23xx high resolution imaginginspector as a reference system,ensuring the capture of all defecttypes of interest for that module,then using the resulting Pareto chartand defect map to set up appropriaterecipes on the higher throughput,double-darkfield system.3, 7 Theyfound that the double-darkfield sys-tem was able to capture all CMPdefect types that the high resolutionimaging system could capture. Theyalso found that the high-resolutionimaging technology was especiallysensitive and uniquely effective incapturing ECD and integrationdefects (seam/edge voids, patterndefects, etc.).

While specific methodologies andtool sets throughout the copperprocess are determined by many fac-tors, such as product type, layer, anddominant defect species, a few generalobservations can be made. Extensivesampling is recommended for ade-quate monitoring of single-waferexcursions. Tracking defects by typeis critical for yield learning and toolmonitoring in the presence of highnuisance counts. Finally, utilizing amix of high-resolution imaging anddouble-darkfield inspection, migratingto predominantly double-darkfield

Spring 2003 Yield Management Solutions 25

C O V E R S T O R Y

Figure 14. SPC charts to catch defects of interest with IMPACT High Resolution Defect Classification.

Average Defect Count

Average Defect Count (after)

Percent OOC

Percent OOC (after)

100%

90%

80%

70%

60%

50%

40%

30%

20%

19%

0%

Per

cen

t W

afer

s O

OC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Avg

. D

efec

t Co

un

t

Slot

CMP Trench Defect Per Slot

Identification/Reduction of Excursion Wafers

Figure 15. CMP trench defect per slot.

The effective resistivity specificationof the International TechnologyRoadmap for Semiconductors for 90 nm to 32 nm may not be possibleto meet, primarily because specificresistivity rises as line widths shrink.At linewidths of 100 nm the specificresistivity is twice that of a 200 nmline, and at 60 nm the specific resis-tivity triples. This effect may berelated to the fact that the linewidths are becoming comparable tothe length of the mean free path ofelectrons in copper, promotinginelastic scattering at the copper-barrier sidewalls.2

Some companies are currently exper-imenting with mesoporous materialsas low-κ dielectrics. These materialscontain interconnected pores 2 nmin diameter or greater, a means ofachieving even lower κ values. Theproblem with high porosity materi-als is that they are vulnerable to pen-etration by any stray molecules ofgas or vapor. Such contaminationwould raise the effective κ value,and diminish the value of the pre-sumed low-κ dielectric. To mitigatethis potential problem, the sealbetween the dielectric and the barriermetal layer would have to be nearlyperfect.2 Chemical vapor deposition(CVD) of the barrier-seed layershould be more successful than PVDfor coating the irregular sidewallspresented by the porous low-κdielectric — but CVD of Ta/TaN hasits own set of problems such as con-tamination. The more likely candi-date for managing deposition on theporous sidewalls is a relatively newtechnique called atomic layer depo-sition (ALD).10 However, perhaps amore serious problem than coverageof irregular sidewalls is having resid-ual polymer left in the pores afteretch — this may be a difficult inte-gration problem.11

Another probable upcoming chal-lenge as the industry reaches the

High throughput, high sensitivity double-darkfield UVinspectionAs the semiconductor industry pushes the technology from 130 nm to 90 nmand beyond, increasing process complexity has given rise to new types ofdefects that are harder to find and identify. Rapid detection of single-waferexcursions, and tracking by defect type will continue to be key to successfulproduction of leading-edge devices. The AITFUSION UV™, the latest evolutionof the production-proven AIT family of high throughput, high sensitivitydouble darkfield inspection systems, was developed to address the specialneeds of 300 mm inspection and excursion monitoring at 100 nm design rulesand below. The combination of double-darkfield optics, Adaptive Mode™technology, increased data rate, and UV wavelength illumination deliverdramatic cost of ownership improvements. High defect capture, even onrough, grainy surfaces and in the presence of color variation, make it an idealtool for cost-effective copper CMP, deposited films, and patterned-layerinspection. By increasing the amount of light scattered from small defects,this tool’s UV wavelength illumination supports critical sensitivity require-ments for sub-100 nm design rule production. Spot migration — enabledby the AITFUSION UV’s increased sensitivity and advanced detection algo-rithms — contributes to significant throughput enhancements. Three independent collectors offer selectable polarizers and programmable spatialfilters for superior noise suppression and complete capture of all criticaldefect types. Inline automatic defect classification (IMPACT™ iADC)technology extracts information in real time during inspection to classify alldefects on a wafer. This allows better nuisance filtering for improved defectcapture, trending by killer-defect type for faster, more reliable recognitionof excursions, and defect review sample shaping.

70.000

60.000

50.000

40.000

30.000

20.000

10.000

Def

ect

Den

sity

CM

-2)

<

Lot-Wafer ID

Lot

01

Lot

02

Lot

03

Lot

04

Lot

05

Lot

06

Lot

07

Lot

08

Lot

09

Lot

10

Lot

11

Lot

12

Lot

13

Lot

14

Lot

15

Lot

16

iADCManual classification

Visible versus UV graphics

Tput

AITFusionUV3.5 µm

Std Algo HLAT/ChFus

18.3 - 20 wph

AITFusionUV5 µm

31.1 wph

AIT XP 5 µm

12 - 14 wph

Counts = 3583 Counts = 4174

Counts = 2368

Counts = 456

C O V E R S T O R Y

Spot Migration: Sensitivity andThroughput Advantages

Trending by Defect Type

90 nm and 65 nm nodes is copper fill.With a barrier/seed layer of 1100 Å(field thickness), thick enough toensure adequate continuity on the viasidewalls, the opening to a 65 nm viawould be shrunk to 150 Å, makingcopper fill very challenging.11 Voidswill likely continue to be a dominantdefect mechanism as design rulesshrink and high-aspect ratios remain.

Finally, a new method for testing forelectromigration will likely be nec-essary. Currently these tests requirehigh temperatures, which can causefilm stress, especially in low-κ mate-rials. Furthermore, grain growth canoccur during a high temperaturetest, and subsequent relaxation offilm stress may be accomplished byvoid formation.12 Without an effec-tive test for electromigration, thereliability of the low-κ device willbe uncertain.2

In the face of these challenges, accu-rate and timely defect detectionbecomes even more critical. As theindustry moves forward, with solu-tions driven by new materials, newarchitecture and new processes,defect inspection must stay one stepahead. Shorter-wavelength lightsources, reaching into the UV, willenable greater sensitivity (see side-bars). At the same time, new algo-rithms in data processing and datamanagement will prove critical tosuccess. Hardware and softwareimprovements must work to keepthroughput high and manage costs.

SummaryCopper interconnects and low-κdielectrics are enabling technologiesfor device performance; at the sametime they are accompanied by somenew and difficult challenges. Thesechallenges may deepen as devicesevolve past the 130 nm node.Surface and sub-surface voids, slurryand clean residues are among the

Corrosion defect detected at copper CMP1.

Total Defect Count Defect of Interest

0.13µm Spacer EtchThis recipe bins the defect of interest, enabling smarter SEM review

iADC turned on

High resolution imaging inspectionIn-house characterization studies, substantiated by similar real-world studiesin fabs, have demonstrated that high-resolution imaging is the preferredtechnology for detection of the smallest defects in all circuit geometries,but particularly in dense logic areas and where linewidths are smallest. The23xx family of high resolution imaging inspection systems builds on aproduction-proven platform and is ideally suited for line monitoring of awide range of layers that require the highest sensitivity. These include FEOLetch, photo (ADI, PCM, and PWQ applications), critical metal-etch, andcritical copper CMP. Flexible UV illumination modes combine with highNA to enable inspection of all process layers with full sensitivity to theentire range of defects. Broadband offers high resolution and color “noise”suppression for capture of critical defects, while narrowband complementsbroadband inspection by providing enhanced resolution and contrast forcapturing defects in the absence of color noise. Improved defect capturein dense geometry and in the presence of color variation is made possiblewith proprietary optical edge contrast noise-suppression technology.Sensitivity-enhancement and nuisance-rejection algorithms enable robust,high sensitivity with low nuisance rates. Mature autofocus subsystemsand die-to-die run-time alignment algorithms deliver high sensitivity andlow nuisance rates with the stability required for production usage. Inlineautomatic defect classification (IMPACT iADC) technology providesimmediate feedback on defect types, and enables inline nuisance filtering,trending by defect type, and sample shaping for offline SEM review.

C O V E R S T O R Y

Detection of Unique Defect Types

iADC for Faster Time to Results

28

most common kinds of defects foundin the parts of the copper processthat begin with barrier/seed and endwith cleaning. The new defectPareto they create is founded on thematerial properties of copper andlow-κ dielectrics. The architectureof the damascene process also con-tributes strongly in determining thedefect Pareto charts for the newdevices.

Several successful fabs have shownthat defect control in the copperprocess can be optimized by: (1)dense sampling to quickly managesingle-wafer excursions, (2) trackingby defect type to mitigate the influ-ence of nuisance defects such asmicroscratches, and (3) selecting amix of inspection systems thatenables capture of all relevant defecttypes while maintaining adequatethroughput to meet cost of owner-ship targets.

AcknowledgementsThe authors would like to thankArun Chatterjee for critical readingof this manuscript.

References1. Laura Peters, “Exploring Advanced

Interconnect Reliability,” Semicon-ductor International.

2. Peter Clarke, “Challenges mountingover low-κ, copper interconnect, saysresearcher,” Semiconductor BusinessNews, October 9, 2002.

3. Judy B. Shaw, Richard L. Guldi, Jef-frey Ritchison, Steve Oestreich, KaraDavis, Robert Fiordalice, “Voids, Pitsand Copper,” Yield ManagementSolutions, Winter 2002.

4. Arun Chatterjee, “Copper Intercon-nect: Process Control Solutions,” pre-sentation January, 2000.

5. Peter Stoeckl, Barry Saville, Jim Ka-vanagh, Thilo Dellwig, “AdvancedCu CMP Defect Excursion Controlfor Leading Edge Micro-ProcessorManufacturing,” Yield ManagementSolutions, Winter 2002.

6. Kerstin Kaemmer, Grit Bonsdorf, Mar-tin Tuckermann, and Jim Kavanagh,“Using real-time defect classificationto investigate post-CMP cleaningprocesses,” Micro, October 2002.

7.Richard Guldi, Vince Korthuis, MonaElssa, Frank Cataldi, Jeffrey Ritchi-son, Judy Shaw, Vikas Sachan, SteveFanel l i , Michael Vunguyen, BobFiordalice, “Process and Tool Moni-toring in Copper/Low-κ CMP,” pre-sented at the Yield ManagementSeminar, SEMICON West, 2002.

Spring 2003 Yield Management Solutions

8. Raleigh Estrada, “Common Practicesin Defect Control within the CopperModule.”

9. Jus t in Anderson, Jason Heine,Matthew Soucek, Kwame Boahenand Jon Button, “Fast Ramp of a130nm/300mm Copper Processwith a Phased Yield EnhancementMethodology.” Yield managementSeminar, SEMICON West, 2002.

10. John Forster, “Copper Barrier/Seed,” presented at the November20, 2002 meeting of the Thin FilmUser Group of the American VacuumSociety.

11. Imran Hashim, “Challenges forNextgen Copper Barrier/Seed,” pre-sented at the November 20, 2002meeting of the Thin Film User Groupof the American Vacuum Society.

12. Paul Besser, “Microstructure of InlaidCopper Interconnect Lines: Charac-terization and Implications for Relia-bility,” presented at the November20, 2002 meeting of the Thin FilmUser Group of the American VacuumSociety.

C O V E R S T O R Y

There used to be a time when high-yield copper interconnects only existed in your

imagination. But now, they can be a reality. KLA-Tencor has the tools and strategies

to help you find, analyze, and fix the defects that most greatly impact device yield –

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The result? A copper interconnect yield so high, you’ll want to shout it to the world.

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For solutions and strategies to accelerate copper yield, visit our Cu Xpress

website at www.kla-tencor.com/CuXpress

©2002 KLA-Tencor Corporation

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