Spring08 yms08 issue1

yms yieldmanagementsolutions

www.kla-tencor.com/ymsmagazine2008 | Issue 1

Welcome to the Spring 2008 issue of KLA-Tencor’s YMS Magazine, available on CD-ROM and online atwww.kla-tencor.com/ymsmagazine

Contents page 2

ArtiCle topiCs:Defect Management page 3

Fab Economics page 25

Inspection page 29

Metrology page 33

Product News page 38

http://www.kla-tencor.com/ymsmagazine

Yield Management Solutions is published by KLA-Tencor Corporation. To receive Yield Management Solutions: www.kla-tencor.com/ymsmagazineFor literature requests, visit: www.kla-tencor.com/products

©2008 KLA-Tencor Corporation. All rights reserved. Material may not be reproduced without permission from KLA-Tencor Corporation. Products in this document are identified by trademarks of their respective companies or organizations.

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Advances in SEM Review for Efficient Generation of Meaningful Paretos Crolles 2 Alliance and KLA-Tencor Corporation page 3

Using Design Based Binning to Improve Defect Excursion Control for 45nm Production United Microelectronic Corporation and KLA-Tencor Corporation page 7

Defect Criticality Index (DCI): A New Methodology to Significantly Improve DOI Sampling Rate in a 45nm Production Environment Toshiba Corporation and KLA-Tencor Corporation page 11

A Novel Method of Characterizing Post-Laser Anneal Surface Conditions for the 45nm Process Technology Node United Microelectronics Corporation and KLA-Tencor Corporation page 15

Automatic Optimization of MEEF-driven Defect Disposition for Contamination Inspection Challenges United Microelectronic Corporation and KLA-Tencor Corporation page 18

fAb eConoMiCs

A New Decision Paradigm for Comparing Patterned Wafer InspectorsMicron Technology, Inc. and KLA-Tencor Corporation page 25

inspeCtion

Influence of Immersion Lithography on Wafer Edge DefectivityIMEC and KLA-Tencor Corporation page 29

Metrology

Predicting Electrical Measurements by Applying Scatterometry to Complex Spacer StructuresIBM Microelectronics and KLA-Tencor Corporation page 33

proDuCt news

Aleris 8500, 8350 and 8310 page 38

SensArray Etch Measurement Suite page 39

WaferSight 2 page 40 Terafab Family of Systems page 41

Editor-in-Chief Charles Lewis

Contributing WritersBecky PintoReeti PunjaLisa Garcia

Art Director and Production Editor Inga Talmantiene

Production ConsultantJovita Rinkunaite

Circulation EditorCathy Silva

Contents


http://www.kla-tencor.com/products

2008 | Issue 1 Yield Management Solutions | www.kla-tencor.com/ymsmagazine

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Advances in SEM Review for Efficient Generation of Meaningful ParetosL. Tétar, B. Hinschberger, D. Pepper – Crolles 2 AllianceM.K. Raghunathan, O. Moreau, D. Randall – KLA-Tencor Corporation

Figure 1 shows an increase in the percentage of SEM Non-Visual defects on three different layers for 90 and 65nm technologies at Crolles. The SNV category in the defect Pareto interferes with the ability of the defect or yield engineers to monitor the key defects of interest, effectively reducing the meaning, or information content, of the Pareto. This has a direct impact on the corrective actions taken during an excur-sion or process ramp; insufficient information delays decisive action, or in the worst cases an incorrect decision could be made. As a result, the time to volume production, which is the largest determinant of manufacturers’ profit, is affected.

Experiment and Results

We investigated several factors that affect the ability to generate meaningful Paretos:

Resolution of the SEM•

Defect detection •

- Stage accuracy of the SEM - Effectiveness of the defect re-detection algorithm

Defect classification •

- Prevalence of previous-layer & color-variation defects - Accuracy and purity of automatic defect classification

Quality of the inspection recipe•

Measuring approximately 800 wafers over a period of six months at three technology nodes (90, 65, and 45nm) at Crolles, we tested the ability of a new e-beam review and clas-sification system (KLA-Tencor eDR-5200) to work together with our existing inspection tools to improve each of these factors and enable us to generate better defect Paretos.

Starting at the 45nm generation, conventional SEM review tools have limited ability to generate high-quality defect

Paretos. Extensive testing of the new eDR-5200 has demonstrated improved inspection-SEM review and classification

performance at the 90, 65, and 45nm nodes. With enhanced connectivity between the eDR-5200 and the inspector, users

created better inspection recipes in less time, leading to quicker yield-related decisions.

Introduction

Defect inspection, review, and classification are each critical steps in generating defect Pareto charts that are fundamental to the defect control cycle. With shrinking killer defect sizes and increasing integration complexity, defect and yield engi-neers are becoming more concerned about the quality of defect Paretos generated by SEM review tools. In many circumstan-ces, semiconductor manufacturers find that one of the largest categories in their defect Pareto is “SEM Non-Visual” (SNV) defects. Using the new eDR-5200 system, we studied the challenges for generation of meaningful Paretos and developed solutions to address these challenges to assist yield engineers in making correct decisions during process development or in high-volume production.

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27 303637 40

82

FEOL 1 FEOL 2 BEOL 1

Layer

% S

NV

90nm65nm

Figure 1: Increasing % SNV with design rule advances for three layers at Crolles.



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Resolution of the SEMAs leading-edge fabs bring 65nm devices into production and investigate the 45nm and 32nm nodes, very high SEM resolution (on the order of 2–3nm) is essential for imaging very tiny defects. The eDR-5200’s high resolution was demonstrated in the images of tiny killer defects on 65 and 45nm technologies, as shown in Figure 2.

Defect Detection Stage Accuracy of the SEM A high-precision stage and advanced de-skewing algorithm are absolutely essential as design rules go beyond 65nm, in order to be able to locate critical defects at smaller design rules (Figure 3). We studied the positioning performance using inspection results from industry-standard brightfield inspectors in our fab. We found that, on the eDR-5200 equipped with a high-precision stage, the defect always lay within a 2–3µm field of view.

The high stage accuracy of the system enables it to operate in Direct Defect Location (DDL) mode, where, following global deskew, it automatically drives and grabs an image at the location of the defect. With no defect re-detection involved, DDL review recipes can be set up by a broad range of fab users due to their simplicity of creation.

We used DDL to automatically run review jobs for two differ-ent deposition layers. These DDL mode review jobs ran at a 3µm FOV with >90% success rate. Moreover, this was accomplished at a speed ~2x faster than typical review jobs.

Defect Re-detection AlgorithmLow-contrast or very tiny defects (Figure 4) can be completely overlooked or categorized as SNV by traditional defect re-detec-tion approaches.

Using the eDR-5200, we found the average defect re-detection rate to be >90% across 29 process steps for more than 600 wafers at three different technology nodes: 90, 65 and 45nm (Figure 5).

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0.5µm 0.5µm 0.5µm

Figure 2: Sample of high-resolution images having 0.5μm field of view (FOV) from eDR-5200.

6µm 3.5µm

Figure 3: Need for stage accuracy.

3.5µm 1.5µm

Figure 4: Low-contrast defect re-detection using advanced algorithms.

Average Defect Re-detection Rate across 29 layers - 90, 65 & 45nm

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Figure 5: Average defect re-detection rate on the eDR-5200.



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Defect Classification

Prevalence of Previous-Layer/Color-Variation Defects Because an electron beam interacts only with the surface of a layer, deeply embedded or previous-layer defects are not visible in a SEM image and hence are classified as SNV.

A new approach is used on the eDR-5200 by accessing optical information from compatible inspection tools using an applica-tion called “Data on Demand” (DOD) to assist in classification of previous-layer defects. With this capability, there is access to optical patch images for all defects in the KLARF (KLA Re-sults File), which assists in understanding the nuisance defects better — whether it’s a previous-layer defect, color-variation defect, or noise from the inspector.

Figure 6 illustrates that there were some defects in the layer below the one being inspected, besides some color-variation defects. These could be seen optically but not by the SEM.

Traditionally, they would be classified as SNV, but with the new approach they could be directed to the “previous-layer/optically visible” defect bin.

Automatic Defect Classification We implemented automatic defect classification on three layers at the 90nm technology node. The classifiers for each of these three layers had seven to eight different class codes. The basis of these classifiers was to efficiently separate killer defects from nonkiller defects.

Figure 7 shows an illustration of the classifier’s performance on one of the FEOL layers where the automatic and manual defect classifications match closely. This shows promise for use in production.

Quality of the Inspection Recipe

Using the connection capability between the eDR-5200 and compatible optical inspection systems, we investigated the inspection recipe optimization process and found it to be faster and more precise. This was mostly due to the elimination of multiple iterations between inspector and SEM.

The inspection recipe tuning is interactive on the new SEM system, so the user receives instantaneous feedback with each recipe threshold adjustment in the form of SEM images and defect class assignments. This process can be used by a broad range of fab personnel for both advanced technologies and for high-volume production, thanks to a common interface with the inspection tool. This approach has become our standard process for brightfield inspector recipe optimization. Further, this frees the inspection tool for additional production inspec-tion.

We optimized ten recipes for 90, 65, and 45nm technologies using this technique. We found that we could obtain the final recipe with only one iteration of the process. The improvement in the inspection recipe relative to the existing recipe setup technique is shown in Figure 8. In this case the SNV rate was reduced while the killer defect counts were maintained, merely by adjusting regional thresholds.

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0 01

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Nuisance Previous-Layer Defect Color Variation

w/o DODw/ DOD

OM Ref

SEM

OM

SEM

OM Def

Figure 6: Classification of previous-layer/color-variation defects on the eDR-5200 using DOD.

FEOL #1: 90nm Defect Pareto

Nuisance NK DOI #1 NK DOI #2 NK DOI #3 K DOI #1 K DOI #2 K DOI #3 K DOI #4

eADC Classification

Manual Classification

Figure 7: Performance of automatic defect classification on the eDR-5200.

Actionable Pareto: Before Inspector Recipe Optimization vs After

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SNV Killer DOI 1 Killer DOI 2 Killer DOI 3

Def

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Defect Count using traditional Inspector Recipe Optimization

Defect Count after using new technique Inspector Recipe Optimization

Figure 8: SNV reduction after inspection recipe optimization on SEM.



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In some cases, this technique helped identify the best optical mode on the inspection tool to maximize (SEM-visible) killer DOIs in the Pareto. Figure 9 shows an example of a Pareto resulting from testing three different optical modes on contact after-development inspection at 45nm. Based on the results, Optical Mode 3 was the optimum mode for this recipe because the resulting Pareto had (1) low SNV count, (2) low previous-layer defect count, and (3) best sensitivity to killer DOIs.

Figure 10 shows that it took ~5 hours to optimize the 45nm inspection recipe for optical mode. We estimate that without this capability it would have taken at least two shifts.

The Paretos resulting from an inspection recipe optimized using this method were verified across several lots. Figure 11 shows the percentage of SNVs and DOIs to be stable and consistent in performance.

Conclusion

We have shown that, with all the above features, the eDR-5200 has improved our inspection-SEM review and clas-sification performance on multiple use cases at the 90, 65, and 45nm nodes. We are now able to make better wafer inspection recipes in a shorter period of time with minimal training for fab personnel using the connectivity between the eDR-5200 and the inspector. This has helped us make quicker yield-relat-ed decisions about our process.

The review use case and methodology using the eDR-5200 has now become an integral part of our defectivity control plan deployment in Crolles’ mixed R&D/production environ-ment. This has been possible because of the improvements in time to results, utilization of fab resources and tools, and a step-by-step methodology that guarantees quality results. This methodology helps Crolles to improve both development time and, ultimately, time to market, which are critical in today’s competitive semiconductor market.

This paper was originally published as "Advances in SEM non-visual defect reduction: rapid generation of meaningful paretos", L. Tétar, B. Hinschberger, D. Pepper, O. Moreau, D. Randall, M.K. Raghunathan, The 10th Technical and Scientific Meeting of ARCSIS, December 6 - 7, 2007.A version of the paper was also published in Future Fab International, Issue 24, January 2008, pages 94 - 100.

Biographies L. Tétar gained his defectivity experience as applications engineer for a SEM review tool vendor, then as an inspection tool owner for Intel Ireland. He joined ST Microelectronics in 2006 and is now in charge of advanced R&D FEOL defectivity reduction.

M. K. Raghunathan has a M.E. in Microelectronics Engineering from RMIT University in Melbourne. He has been an applications engineer in the eBeam Review and Classification Division at KLA-Tencor for two and a half years, developing applications and use cases working in several state-of-the-art semi-conductor fabs in Asia and Europe.

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45nm: PHOTO LAYER: Defect Pareto w/ 3 Different Optical Modes on 2xxx

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Optical Mode 1 High nuisance rate, sensitive to previous-layer defects

Optical Mode 3 Low nuisance rate, highly sensitive to previous-layer defects

Optical Mode 2 Low nuisance rate, not sensitive to previous-layer defects, and demonstrating high count of all killer DOIs

Figure 9: Advanced inspection recipe optimization on SEM.

Quick review on 2xxx

Color variations?yes

Create eDR-5200 recipe

Sampling + auto review of each test using DDL

Classification

RICO optimization

Finalize & upload to 2xxx

DOI capture?

Create basic recipe

Create 3 tests with different optical combos

Run hot scans

30min

1hr 45min

15min

25min / Test

15min / Test

10min / Test

Adjust Thresholds

Figure 10: Process flow for inspection recipe optimization on SEM.

45nm: FEOL: DOI % SNV % after 1 Iteration of Inspection Recipe Optimization on SEM

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After Inspection Recipe Optimization

Before Inspection Recipe Optimization

Figure 11: Consistency in performance of inspection recipes optimized on SEM.



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Using Design Based Binning to Improve Defect Excursion Control for 45nm Production Crockett Huang, Hermes Liu, S.F. Tzou – United Microelectronic Corporation Chris Young, David Tsui, Alex Tsai, Ellis Chang, – KLA-Tencor Corporation

Design Based Binning (DBB), a method that integrates design information and defect inspection results, can be used to

identify design locations where defects frequently occur, allowing advanced fabs to correct systematic problems through

design or OPC modifications. DBB techniques can also be extended to enable better monitoring for systematic and ran-

dom defect excursions in production.

Introduction

For the 45nm node, immersion lithography has been a ma-jor enabling technology for pattern shrinkage. Litho R&D engineers have applied OPC and tighter process windows to mitigate the impact of decreasing pitch and complex pattern design. However, pattern-related systematic yield loss is still listed as a major barrier for 45nm advancement to production. Certain pattern designs are sensitive to process variation from film deposition, photo and etch steps. A combination of film over-deposition and under-etching at these steps can lead to film residue in the form of line bridging defects (Figure 1).

This problem will get worse in the production stage, with process variation arising from multiple tools and modules. With sensitive inspection tools and small-pixel inspection recipes, pattern excursions can be identified. However, if the failed pattern count is low (in tens) and the total defect count is high (in thousands), current random sampling methods for SEM review, sampling 50 to 100 defects per wafer, can easily miss this excursion. Consequences can be significant, affecting yield, time to market and profit.

To address this issue, we employed a new methodology called Design Based Binning (DBB) that bins defects of interest according to their background pattern information. This infor-mation can be used to identify certain design locations where defects frequently occur. While these known, systematic pat-tern problems might be addressed with design/OPC modifica-tions, they can still show up in production as excursions, and thus need to be constantly monitored. We can bin and track for such excursions with DBC (Design Based Classification, shown conceptually in Figure 2).

overunderEtch

overunderPhoto

overunderDep

Line bridging (28xx)

Line broken (28xx)

Aft

er E

tch

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/ To

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Figure 1: Marginal design and process variation can lead to systematic excursion events.



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We can also use design and pattern information to monitor for random excursions. For each defect, a proprietary model merges its background pattern information with the size information assigned by the inspection tool, and generates a value to indicate the defect’s likely yield impact. This Defect Criticality Index (DCI) ranges in value from 0 to 1.

By applying DBC and DCI to inspection results, we can build SPC charts to monitor systematic (DBC) and random (DCI) excursions. During the R&D stage, we can identify marginal pattern sites from either the design library or PWQ/FEM data. These risky pattern features will be built into a hot spot lib-rary and passed to production for monitoring. When a defect excursion happens during a pilot/production stage, the SPC chart will flag the problem. This will trigger additional defect sampling and review specific to the problematic pattern

location. This methodology will enable us to take prompt cor-rective action at an early stage of the excursion, before many wafers are lost.

Experimental Data and Results

Wafer inspection and defect binning We selected four SRAM wafers from the same lot, processed through the gate etch layer. We inspected these wafers using a brightfield inspection tool (KLA-Tencor 28xx), and reviewed around 50 randomly chosen defects on each wafer with the review SEM. We classified the defects manually, and normal-ized the data by defect type to check for excursions. The results, shown in Figure 3, indicated potential random excursions on wafers 3 and 4, as well as a systematic problem (type B) on wafer 4. However, due to the high total defect count on the

Class-1 Class-2 Class-3 Class-4

1. Extract design clips 3. Assign Pattern Class code

2. Compare against Pattern Library

Define “patterns of interest” in Pattern Library

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Figure 2: Pattern failure monitoring by supervised Design Based Classification.

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Particle Type S NV Type B Residue Previouslayer

wafer 1: 666 defects




Figure 3: Defect Pareto resulting from traditional method for review sampling and normalization.

380360340320300280260240220200180160140120100806040200

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Figure 4: Unsupervised Design Based Binning results on Wafer 4. Top bin represents defects on dummy pattern.



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DCI results for random excursion monitoring For each defect, DCI was calculated automatically. A lower index indicates that a defect is less critical. The DCI results can help prioritize defects for inclusion in the SEM review sample. An example of DCI values with their corresponding defect im-ages is given in Figure 6. To protect customer IP, all GDS clips were hand drawn and do not reflect their original design.

Based on SEM review and DCI number, we set a threshold of 0.1 for non-critical random defects (small defects on spare pat-tern). A plot of the percentage of non-critical defects (Figure 7) indicates that wafer #3 had the highest percentage of critical random defects among the four wafers. This result motivated us to review a sample of defects from the higher DCI group on the SEM. We identified a polymer excursion defect which was missed by the traditional sampling method.

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wafers, and the limited SEM review sample (average=42), the excursion signal did not clearly indicate the extent of the problem.

DBC binning results for systematic excursion monitoring Next, results from these four wafers were binned using DBB. An example of DBB results from wafer #4 is shown in Figure 4. The top bin in the chart represents defects on dummy pat-tern regions, which are regarded as “don’t care” regions. These defects can be filtered out with no impact on yield. By running DBC analysis on the four wafers, we found that one pattern type from the hot spot library had a high defect count on wafer 4 (Figure 5). This wafer was sent for further SEM review, and the outcome was confirmed as a systematic excursion.

DCI = 0.01

Type B defect count

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Figure 5: DBC results indicate Wafer #4 had a systematic excursion: the “line broken” defect type shown in the SEM images.

DCI =0.06

DCI = 0.65

DCI =0

DCI =0.33 DCI = 0.01

Dummy: No DCI value

Figure 6: DCI samples show defect size (blue rectangle) and pattern background information (red line drawings, disguised to protect customer IP).



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Summary

We summarized the comparison between the new DBB method-ology and the current UMC practice in Table 1.

From many use cases in UMC, DBB has shown benefits in finding pattern-related defects on 45nm device wafers. DBB is a novel method for finding systematic defects, and has the potential to serve as an in-line monitor for systematic and random excursions.

Item Current Practice New DBB Methodology

Defect on dummy Many defects on dummy pattern

0 %

Nuisance (poly grain/cap, small particle/field)

Vary/high defect count Use DCI < 0.1 to screen out random non-DOI

Systematic defect (pattern failure) identification

Repeater analysis Review same type > 2

Control chart on “known pattern of interest (POI)”

Excursion trigger By total defect counts-Bad die%

By count and DCI % (e.g. for DCI < 0.1)

SEM review sampling, 50 defects

Random selection Systematic defect with DBC and random review with high DCI

© 2007 IEEE. Reprinted, with permission, from the International Symposium on Semiconductor Manufacturing (ISSM) 2007 conference, October 2007: ISSM Paper: DM-P-240

AcknowledgmentsThe authors will like to thank Dr. Tzou from UMC CRD for his full support in publishing this paper. We also thank Allen Park from KLA-Tencor for his thoughts and input to our paper.

ReferencesK. Monahan and B. Trafas, “Design and Process Limited Yield at the 65nm Node and Beyond” Proceedings, SPIE, 2005.

J. Yeh, A. Park, “Novel technique to separate systematic and random defect during 65-nm and 45-nm process R&D stage,” Proceedings, SPIE 6521-40, 2007.

MaryJane Brodsky et al., “Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era,” Design and Process Integration for Microelectronic Manufacturing III, SPIE 5756, 2005.

Table 1: UMC current practice compared with DBB method

Percentage defects with DCI < 0.1

50%

60%

70%

80%

90%

Wafer 1 Wafer 2 Wafer 3 Wafer 4

Perc

enta

ge

Potential random excursion

Potential systematic /nuisance excursion

DCI = 0.37

Figure 7: DCI chart showing Wafer # 3 having highest potential for yield-impacting random excursion.



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Defect Criticality Index (DCI): A New Methodology to Significantly Improve DOI Sampling Rate in a 45nm Production EnvironmentYoshiyuki Sato, Yasuyuki Yamada, Yasuhiro Kaga, Yuuichiro Yamazaki – Toshiba Corporation Masami Aoki, David Tsui, Chris Young, Ellis Chang – KLA-Tencor Corporation

To reduce the percentage of non-DOI or nuisance defect types populating the defect Pareto, a new methodology

associates GDS clip (design layout) information with every defect detected by the inspection system. This information,

together with traditional inspector-assigned attributes such as size and brightness, is used to assign a Defect Criticality

Index (DCI) to each defect. When only high-DCI defects are included in the SEM review sample, resulting defect Paretos

are more actionable. For a gate process on a 45nm logic device, the DOI extraction rate improved from 12% to 68%.

Introduction

Because smaller defects become yield relevant as minimum design features shrink, manufacturers have had to increase wafer inspection sensitivity in order to capture all defects of interest (DOI). This has resulted in an increased number of detected defects and a higher percentage of non-DOI or nui-sance defect types during in-line monitoring. When a SEM review tool is used to observe and classify these defects in order to determine root cause, a problem arises. Time constraints in the fab usually limit review sampling to a relatively small, fixed defect sample per wafer—typically 50 to 100 defects. If 100 defects were sampled from a population of several thou-sand defects on a wafer, the sampling rate would be only a few percent. Under such conditions, it is difficult to identify DOI types that should be monitored in production. A new sam-pling method is required for effective DOI capture under very low sampling-rate conditions (Figure 1).

In this paper, we verify the effectiveness of utilizing design data for the separation of DOI from non-DOI. We also propose a new review sampling method that assigns a “criticality” index based on design data. This index is used together with traditional defect information for improved DOI sampling.

Technology Node

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Figure 1: Increased risk with technology node of missing critical defects, from low review sampling rate.



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System Overview

Design Based BinningThe principles of Design Based Binning are shown in Figure 2. After in-line defect inspection, the following actions occur:

Each defect is mapped to its GDS coordinate, and the 1. corresponding pattern background data is extracted (GDS clip). Any GDS layer can be chosen for mapping.

The GDS clips are compared. 2.

Defects are binned based on pattern matching, patch 3. image and design attributes such as line width and line space.

The binning results are utilized for DOI/non-DOI separation and systematic/non-systematic separa-tion analysis.

System verificationTo verify this system we used a TEG (Test Element Group: includes all test elements from a single transistor to small-scale SRAM circuits, etc.) pattern as shown in Figure 3, line-and-space patterns, with design rule and line directions different in each TEG block. A broadband bright-field system (KLA-Tencor 28xx) was used to inspect the wafer after metal 1 trench formation.

After wafer inspection, we obtained the GDS clip of the metal 1 layer and performed Design Based Binning as described above. Auto classification created four groups representing the four background patterns. The resulting Pareto chart by pat-tern group is shown in Figure 4.

The defect count in each group exhibited wide variation. Group 1, representing the horizontal pattern with the smaller line spacing, showed the highest defect count. It is possible to determine pattern-specific defects by restricting SEM review sampling to each pattern group in turn.

Figure 5 shows part of a defect wafer map color coded by pat-tern group. Each TEG block clearly shows a single color, which suggests good accuracy and purity of the auto classification by background pattern.

Figure 6 shows the Design Based Binning results for defect data from a 45nm SRAM gate process. After wafer inspection, the GDS clip of the gate layer was extracted and the patterns were automatically classified. The pattern type showing the most defects was found to be “blank clip” (no gate-layer pat-tern); thus, defects on blank areas were dominant in the inspec-tion data. These defects are non-DOI.

Defect Criticality Index (DCI)

Each defect detected by an inspection tool has attributes such as defect size and brightness, in addition to coordinate data that indicate its location on the wafer. These defect attributes are traditionally utilized for automatic defect classification.

Figure 7 shows the new concept of the Defect Criticality Index (DCI). Generally, the criticality (yield relevance) of a defect is determined by the background pattern associated with the neighborhood of the defect, along with traditional defect attri-butes. For example, a small defect on a sparse background (low pattern complexity) would be considered less yield relevant. On the other hand, a large defect on a complex background pattern tends to have relatively higher impact on yield.

Group 1 Group 2 Group 3 Group 4

1. Extract design clips

3. Create Pattern based Pareto

2. Compare clips against themselves

Figure 2: Overview of Design Based Binning.

Pattern-1: Pitch-A, Horizontal Pattern-2: Pitch-A, Vertical

Pattern-3: Pitch-B, Horizontal Pattern-4: Pitch-B, Vertical

Figure 3: TEG pattern used for system verification.

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As with Design Based Binning, the design attribute for each defect is extracted from the GDS clip. Then the DCI is calcu-lated by combining the design attribute with traditional defect attributes. DCI values range in value from 0 to 1 and are used to assess priority for inclusion in the SEM review sample.

Sampling experimentIn order to verify the DCI sampling method, we planned and executed the following experiment. First we inspected the wafer, which had a 45nm design rule TEG pattern, after salicide formation. We reviewed and manually classified all detected defects (total 1315 count) on the SEM. We identified five pattern defect and particle types as DOI. Non-DOI types included "defect on dummy pattern" and "cone" (Si spike). The DOI percentage in the full defect population was about 11% (Figure 8).

We then tested three methods for determining a 100-defect SEM review sample. The first was random selection, the method most commonly employed in fabs today. The Pareto generated by our random sample was considered the baseline. The second used the inspector’s assigned defect size informa-tion to choose the 100 biggest defects for SEM review. The third used the new DCI method described above, selecting the 100 defects with the highest DCI values for the SEM review sample. For the calculation of the DCI, both defect size and design attributes were used.

Results and Discussion

Results of the sampling experiment are summarized in Figure 9. In the randomly sampled defect group (the baseline), 70% of defects were found on the dummy pattern. The total DOI percentage was 12% in the baseline Pareto (similar to the true DOI population found by 100% review), but only two of the five DOI types were represented in this Pareto.

In the sampling group ordered by defect size, the total DOI percentage improved to 33% and all five DOI types were represented. The best results were observed in the DCI-driven sampling group, which showed 68% DOI. The DCI Pareto also delivered the highest number of pattern defect AA, the pattern defect considered the most critical defect type.

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Figure 5: Defect map by pattern group.

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Figure 6: Pareto chart resulting from Design Based Binning for 45nm SRAM gate layer. Top defect type is non-DOI ‘blank clip.’

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Figure 7: Defect Criticality Index concept.

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Figure 8: Complete defect data set for sampling experiment, based on 100% SEM review. Results show 11% DOI in the total population of detected defects, and five distinct DOI types. (45nm SRAM device, gate layer, inspected by KLA-Tencor 2800).

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Figure 9: Comparison of DOI capture rate and DOI type for three different sampling scenarios.



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One of the reasons the DOI ratio in the DCI sampling group was so high is that it totally eliminated the prevalent defect-on-dummy type from the sampling group. Since a specific GDS layer code is usually assigned to the dummy pattern, GDS clips that only include dummy pattern can be perfectly separated.

We also compared SEM images of particle defects from the random sample with those of the DCI-driven sample. In the random sampling group, the majority were particles in the field oxide region, while in the DCI sampling group, more particles on transistor structures (active region and gate poly structure) were represented. This observation shows that DCI-ordered sampling can improve the quality of the review sample in addition to boosting its DOI ratio.

Gate process–related defects can also affect subsequent contact formation. As shown in Figure 10, particles that have fallen on gate structures may cause incomplete contacts. By overlaying contact layer GDS data (a future layer), another DCI set can be calculated. The new set of DCI values could help estimate yield-relevant defectivity for the upcoming contact layer.

To validate this idea, we designed another sampling experi-ment. We used the defect data from the gate layer together with GDS data from both gate and contact. Using the DCI methodology, we compared the results, shown in Figure 11. The DOI percentage based on the contact-layer GDS was 62%, nearly equivalent to the 68% value based on the gate-layer GDS. However, in the contact-layer GDS case, more particle-type defects (large particle and small particle) were included in the Pareto. Clearly some of these defects were less critical (lower DCI) at gate than at contact, where they could cause contact failure. This result suggests that DCI can use a combination of current-layer defect data and future-layer GDS data to predict yield for subsequent processes.

Conclusion

A new sampling method assigns a Defect Criticality Index (DCI) to all defects detected by an inspection tool and uses this information to select a SEM review sample skewed toward a higher percentage of DOI. The DCI is calculated for each defect by using a combination of traditional defect attributes assigned by the inspection system and design information associated with the location of the defect.

We verified the value of this methodology on a 45nm logic de-vice. At the gate process, the DOI extraction rate was improved from 12% to 68%. Furthermore, by overlaying defect data from the gate layer with design data from the contact layer (a future layer), the DCI method was able to predict defect criti-cality for the contact process.

We achieved our purpose of creating defect Paretos with higher yield relevance, by using the DCI method to bias the SEM review sample toward more yield-critical defects. Further inves-tigation is needed to correlate our results with yield data and optimize DCI application to line monitoring.

This paper originally appeared as “Defect Criticality Index (DCI): A new methodology to significantly improve DOI sampling rate in a 45nm production environment,” Yoshiyuki Sato et al., in Metrology, Inspection, and Process Control for Microlithography XXII, Proc. of SPIE, Vol. 6922, 6922-37 (2008).

ReferencesK. Monahan and B. Trafas, “Design and Process Limited Yield at the 65nm Node and Beyond” SPIE 2005 Proceedings 5756_23

J. H. Yeh and A. Park, “Novel Technique to Separate Systematic and Random Defects During 65nm and 45nm Process Development” SPIE 2007 Proceedings 6521_40

Metal-2

Metal-1

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Incomplete contact

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Defect

Figure 10: Particles at the gate layer could cause an incomplete contact.

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Figure 11: Comparison of DCI-generated defect Paretos for gate and contact layers, based on gate defect data, and both gate and contact GDS information.



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A Novel Method of Characterizing Post-laser Anneal Surface Conditions for the 45nm Process Technology NodeW-Y Teng and J-H Yeh – United Microelectronics Corporation P. Chen, S. Radovanovic, D.K. Chen, H. Cheng, and U. Mahajan – KLA-Tencor Corporation

The Laser Spike Anneal process can cause slip line defects and other surface damage, disqualifying substrates for

use at the 45nm node and beyond. Recent advances in UV laser scattering technology have allowed us to use

high-resolution haze to capture whole-wafer surface information with sub-nm vertical resolution, and correlate the

results to LSA processing conditions.

Introduction

With continuous scaling of device dimensions in advanced technology nodes, ultra-shallow and low-resistivity junctions are needed to suppress short-channel effects and improve device performance1. Controlling across-wafer anneal tempera-ture uniformity and minimizing pattern density effects are critical in enabling these Ultra-Shallow Junctions (USJ) for the 45nm node and beyond. One promising method is picosecond Laser Spike Anneal (LSA)1, 2, 3, 4. This process enables highly localized elevated temperatures for rapid annealing of implant layers without impacting the process thermal budget. Howev-er, slip line defects and other surface damage are often induced by rapid heating of the substrate during the LSA process5. Consequently, understanding and characterizing the surface condition of post-anneal wafers are critical in order to develop a robust LSA process. Traditional defect detection techniques either cannot detect slip line defects efficiently (brightfield/darkfield patterned wafer inspectors) or provide information from only a small portion of the wafer (optical microscopes), as seen in Figure 1. A similar situation exists with regard to understanding post-anneal wafer surface morphology. Atomic Force Microscopy (AFM) can provide accurate and quantitative surface information, but its speed is unsuitable for full-wafer characterization and production monitoring.

Laser scattering technology has long been used for monitor-ing slip lines and other defects on unpatterned substrates. In addition, scattering from the substrate surface (traditionally known as haze) is highly sensitive to changes in substrate mor-phology and surface roughness. Haze can capture significant

sub-threshold information that is not detected in the defect channel. Full-wafer haze information allows characteriza-tion and monitoring of surface quality at production-worthy throughput6.

In this study, we applied advanced UV laser scattering tech-nology to characterize the surface condition of laser-annealed wafers. In addition to slip line defects, we were able to capture whole-wafer surface information at sub-nm vertical resolution using high-resolution haze. This surface condition has been shown to correlate well to LSA processing conditions. The results were further confirmed by SEM review, illustrating the potential of using haze data for process development, charac-terization, and monitoring.

Figure 1: Post laser anneal slip defects located and reviewed by optical microscope.



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Experimental Details

Bare silicon wafers were used as the starting substrate in this study. The wafers were processed through the laser anneal tool prior to inspection. For the first part of the study, and to mini-mize the effects of incoming wafer quality on the final surface morphology, one wafer was annealed at six different tem-peratures at and around the process center line, T°C (T-75°, T-50°, T-25°, T, T+25°, and T+50°). A schematic illustration of the anneal splits is shown in Figure 2. Subsequent LSA experiments were run on one wafer with one or two process conditions to verify the repeatability of the characterization technique and to understand within-wafer variations in the anneal process.

Laser scattering measurements were conducted using KLA-Tencor’s Surfscan SP2 unpatterned wafer inspection system. The scans were run under normal incidence in high-throughput mode, which is the optimum scan condition for detecting slip lines and other shallow defects because of their defect scattering characteristics. Surface morphology informa-tion was obtained from the haze scattering detected on the SP2 by analysis of the SURFimages. The SURFimage haze maps provided local surface information at pixel-level lateral resolution and sub-nm vertical resolution. The data is present-ed in 192-bit grayscale to provide clear visualization of surface variation. Haze data from each anneal zone was obtained through a newly developed capability7 that enables local data extraction, analysis, and defect binning of local surface scatter-ing signals using user-defined parameters. The results of this analysis were then correlated to LSA process conditions. SEM review was also conducted to understand the surface condition of each zone and to validate the SURFimage results.


Figure 3 shows a Light Point Defect (LPD) map for the first wafer used in the study. The edge defect signature at the top of the wafer is typical of what is seen for slip line defects. How-ever, the LPD map does not show noticeable differences among the various anneal process conditions (zones). This implies that any modification to the wafer surface that might have occurred during the laser anneal is below the detection threshold of the defect channel.

On the other hand, the SURFimage wafer map (Figure 4) shows distinct visual differences among the different process zones on the wafer. The average haze from each process zone (extracted through offline analysis of the raw scan data) was plotted against the LSA temperature. Figure 5 shows wide channel haze versus process temperature. Strong correlation can be seen, showing that the surface scattering signal increases with anneal temperature.

T -75ºC

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TºC

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Figure 2: Schematic illustration of wafer map with different laser anneal process zones.

Figure 3: Light Point Defect map of post-LSA wafer showing edge signature. No correlation can be seen to the different LSA zones.

T -75ºC − 7ppm

T -50ºC − 15ppm

T -25ºC − 26ppm

TºC − 34ppm

T +25ºC − 37ppm

T +50ºC − 40ppm

HTN-W

Figure 4: SURFimage map of wafer with zones annealed at different temperatures, showing change in surface scattering signal for different process zones. Low haze regions are darker, and high haze regions are brighter. The dark bands are the unprocessed regions between the different anneal zones.

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Figure 5: Good correlation observed between measured SURFimage haze and LSA process temperature. This indicates increased surface roughening at higher anneal temperatures, resulting in higher haze scattering signal.

A SURFimage wafer map shows surface-quality zones which correlate with anneal

temperature.



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Previous studies8 have shown a good correlation between surface scattering Power Spectral Density (PSD) and surface roughness as measured by laser scattering. Based upon these and other characterization work9 the haze results from this study indicate that the wafer surface is modified and rough-ened as a result of the LSA process. This surface roughening increases with LSA temperature (laser energy density).

SEM review of the different zones was also conducted to obtain an understanding of the surface features on the annealed wafer. The results (Figure 6) clearly show increased surface topography and modification for the zones annealed at higher temperatures, thus validating the haze results and trend.

Additional annealed wafers (Figure 7) show similar correlation between LSA temperature and SP2 haze, validating the repeat-ability of this technique. The raster pattern of the laser can also be clearly seen on each wafer.

This technique is also effective at capturing within-wafer variations in surface morphology. A wafer that was annealed at T-75°C was scanned in high-sensitivity mode on the Surfscan SP2 (to capture maximum surface information). The SURFimage map (Figure 8) is able to effectively detect within-wafer annealing variations by changes in local haze. The second map shows the wafer binned into low, medium, and high haze regions for ease of view. These results show the ability of SURF-image to provide full-wafer surface information at production-capable throughputs.

The next step in this study includes AFM analysis of the differ-ent LSA zones in order to obtain a direct quantitative correla-tion between measured surface roughness and haze. In addition, the unpatterned wafer defectivity and surface morphology will be correlated to inline product wafer inspection results. With tighter surface morphology control requirements for the 45nm node, these results can be used to establish SPC limits for pro-duction monitoring of the LSA process.

Conclusions

As IC technology advances result in progressively smaller device dimensions, understanding and characterizing the impact of process variations on wafer surface conditions and identifying potential surface damage become critical. UV laser scattering technology enables full-wafer surface monitoring with sub-nm vertical resolution and high throughput. This technique has been shown to be sensitive to small variations in LSA process temperature that are not detectable by standard defect-monitoring techniques, thus providing a powerful tool for process development and monitoring in a fab production environment.

References1. A. Shima, Y. Wang, S. Talwar, and A. Hiraiwa., Symp. VLSI Tech. Dig., (2004), 174

2. A. Matsuno, K. Kagawa, and Y. Niwatsukino, Proc. of the 2nd Int. Semiconductor Technology Conf. ISTC2002, Tokyo, V.2002-17, (2002) 148

3. J. Venturini, Advanced Thermal Processing of Semiconductors, RTP 2005, IEEE, (2005), 7

4. K. Adachi, K. Ohuchi, N. Aoki, H. Tsujii, T. Ito, H. Itokawa, K. Matsuo, K. Suguro, Y. Honguh, N. Tamaoki, K. Ishimaru, and H. Ishiuchi, Symp. VLSI Tech. Dig., (2004), 142

5. K. Goto, T. Yamamoto, T. Kubo, M. Kase, Y. Wang, T. Lin, S. Talwar, and T. Sugii, IEDM-99, IEEE, (1999), 931

6. F. Holsteyns, L. Cheung, D. Van Den Heuvel, G. Marcuccilli, G. Simpson, R. Brun, A. Steinbach, W. Fyen, D. Vangoidsenhoven, P. Mertens, and M. Maenhoudt, Proc. SPIE V. 6152, (2006)

7. KLA-Tencor, Internal Communication, (2006)

8. A. Belyaev, A. Steinbach, H. Yeh, and B. Pinto, Nikkei Microde-vices, (July, 2006)

9. KLA-Tencor, Internal Communication, (2006)

Zone 1 (T -75°C) = 7ppm Zone 2 (T -50°C) = 15ppm Zone 3 (T -25°C) = 26ppm

Zone 4 (T°C) = 34ppm Zone 5 (T +25°C) = 37ppm Zone 6 (T+50°C) = 40ppm

Figure 6: SEM review of laser anneal zones, showing increase in surface topography with LSA temperature.

TºC − 34.8ppmT -75ºC − 14.6ppm

T +25ºC − 33.8ppm

Figure 7: Two SURFimage maps showing regions of different LSA process condition, and distinct raster signature of the laser.

HSN: 1200°C anneal

Figure 8: High-sensitivity SURFimage of wafer annealed at T-75°C (T is the process center line). Dark (7-8ppm haze) and bright regions (18-20ppm haze) indicate local variations in LSA process conditions, resulting in differences in surface morphology. Wafer map on the right shows regions binned into high (green), medium (orange) and low (pink) haze categories.



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Automatic Optimization of MEEF-Driven Defect Disposition for Contamination Inspection Yung-Feng Cheng, Shih-Ming Yen, James Cheng, Peter Peng – United Microelectronics CorporationTracy Huang, Aditya Dayal, Kaustuve Bhattacharyya, Joe Huang – KLA-Tencor Corporation

Mask ‘haze’ defects can progress quickly in wafer fabs, and even trace amount of airborne contaminates can cause defect

growth. The new STARlight2 ‘Litho3’ algorithm calculates the local Mask Error Enhancement Factor (MEEF) values, then

categorizes defect criticality and bins critical defects. Litho3 captured all critical defects, including those that ultimately

print on the wafer and impact production yield. The number of defects to be reviewed prior to cleaning and disposition

was significantly reduced compared to not implementing Litho3.

Introduction

Device scaling has been a key element in the adoption of 193nm lithography in wafer fabs. The intensified photon energy associated with 193nm lithography has accelerated the development of crystal and haze defects. This particularly affects increasingly complex OPC designs and low k1 photo-masks. High-resolution inspection systems provide excellent capability for detection of small defects of all types. However, the main defects of concern in lithography are those that actu-ally print on the wafer, and these may constitute only a small portion of the total defects detected by the inspection system. Reviewing a very broad range of defects can significantly delay cleaning and disposition decision making and can impede production considerably.

KLA-Tencor’s new STARlight2 Litho3 algorithm is designed to calculate the local Mask Error Enhancement Factor (MEEF) values in the lithography context, thereby categorizing defect criticality on the local geometry and the MEEF. The new algorithm allows binning of the critical defects aggregated at high-MEEF geometries.1-5

Commonly encountered reticle defects can progress rather quickly in wafer fabs, in both lithographically exposed and nonexposed states. Contamination sources are quite prevalent and multifaceted; trace amount of airborne contaminates such as ammonia, sulfur, carbon dioxide or moisture can cause de-fect growth, even at ambient conditions. These crystal defects

can begin to form on all types of surfaces, including those pref-erentially initiated on an EPSM surface; they are followed by a much faster second development stage, called crystal growth. Figure 1 gives an example of defect migration on a 90nm pro-duction mask. The mask passed incoming inspection. However, after one week it developed defects that were extremely detri-mental to production yield.2-6

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1 week

1 week

Figure 1: Illustration of crystal defect progression on a production mask in a wafer fab.



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Litho3 Effectiveness in Defect Identification

A MEEF-driven lithographic detector named Litho3 was designed for run-time use during mask inspection, with the ability to group critical defects into a single bin based on their criticality. The coordinates of these critical defects can be transferred from reticle to wafer domain in KLARF format via XLINK functionality on a KLA-Tencor 9xxx. The KLARF file is then sent to a KLA-Tencor Defect Review System for wafer-level defect analysis.

In this work, four tritone reticles designed to pattern a poly-silicon layer were simulated using the STARlight2 algorithm equipped with the Litho3 detector. Pixel sizes of 90nm and 125nm were used to inspect these reticles. Defects of the high-est criticality were captured by Litho3 and subsequently sub-jected to printability validation. Litho3 consistently captured all the printable defects among the reticles investigated.

The effectiveness of Litho3 in capturing critical defects was demonstrated and detailed in previous communications6. An example is given in Figure 2, which shows that the total num-ber of reticle defects was reported to be 568, among which five evolved into wafer defects verified by SEM review. All five of these defects were captured by Litho3. Due to the complexity of the design features and the type of contamination involved, other users may find the implementation of Litho3 iterative and time-consuming. In the following sections, we discuss the main defect categories in relation to design features; this is fol-lowed by the introduction of an automatic program that gives much faster Litho3 optimization.

Contamination Overview

Contamination defects are frequently seen on photomasks during their fab use. The contamination sources can be traced back to the stepper and fab environment, DUV exposure in a stepper through which contamination reactions are notably accelerated, and various chemicals used during mask cleaning and fabrication. Recent papers have concluded that ammonium sulfate and cyanic acid are the dominant contamination spe-cies observed on the reticle surface. The formation and growth mechanisms of ammonium sulfate and cyanic acid depend upon a range of parameters, such as atmospheric temperature and pressure, moisture level and, quite importantly, the surface on which they reside and its associated properties. It is widely ac-cepted that haze defects are a consequence of multiple photo-chemical reactions activated by deep UV exposure (Figure 3). Among multiple reactions yielding sulfates, carbonates and ox-alates, the ammonium sulfate exothermic reaction (1) is central to haze formation. Crystals form by sublimation of ammonium salts. FTIR and Raman spectroscopy measurements have shown that ammonium sulfate makes up the highest content in the defect blend.11, 12

In the following sections, we discuss categories of commonly seen contamination defects to better understand the defect-formation mechanism and the evolution into printable defects depending upon the chemical and physical properties of the residing surface, as well as how the defects behave with regard to Litho3. For the purposes of this work, we categorize defects based on their location with respect to the design features. Since more defects are grown on EPSM than on COG masks, our main focus here is on EPSM reticles, in which “clear” refers to quartz and “opaque” refers to MoSi.

A. Contamination initiated on clear

Case A1 – Contamination in high-MEEF areasThe first category concerns defects formed on quartz. When found in dense features or high-MEEF areas, contaminants on clear have a higher probability of printing on the wafer than do those on MoSi or chrome, causing CD variation to go out of spec. On a quartz surface, any residual silanols appear as a result of surface hydrolysis, which could create nucleation sites for subsequent crystal growth. In the realm of crystallization kinet-ics, nucleation usually occurs with a higher-rate constant than that of crystal growth, whereas the latter is the rate-limiting step. In the case of sulfate crystals, due to the low surface en-ergy, the rate of crystal growth is higher than that of crystalline or semicrystalline polymers or oligomers. On this note, there is a greater quantity of sulfate crystals than cyanic acid crystals.8,

10, 24

From the surface energy standpoint, MoSi and chrome sur-faces have a higher surface energy than quartz does. Similar to quartz, the surfaces of MoSi and chrome are enriched with fine MoSi and chrome crystals that have a greater tendency to attract and retain moisture. Such moisture entrapment is es-sential to sulfate and cyanic crystal growth.7, 8

For defects nucleated on clear in high-MEEF areas, detection is crucial, as bridging may result. Figure 4 gives an example of

NH4+ + SO4

2- → (NH4 )2SO4 (1)

+

CaCO3 → (NH4 )2CO3

+

NH3 → NH4OOCCOONH4

CO2 + H2O → HOOCCOOH NH4 + CO2 → + H2O

+

NH3 → NH4OOCCOONH4

OH

OH

NN

N

Ammonium sulfate Cyanuric acid

Figure 3: Common defects of ammonium sulfate and cyanuric acid.

Litho3

Total Defects = 568

Printable Defects = 5

(a) (b) (c)

Litho3 Defects = 115

Figure 2: . Graphical representation of Litho3 detector successfully capturing printable defects. a) Defect map showing total defects detected. b) Examples of critical defects captured by Litho3, including the five printed defects as schematically shown in c).



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how such defects can be captured by Litho3. The high-MEEF area shown increases defect sensitivity, whereas the Litho3 pa-rameters are determined mainly by the assist and dark features in the reticles under inspection.

It has been reported that contamination is more severe in low k1 reticles where dense geometries are present. This is in accordance with the fact that defects are prone to develop in high-MEEF areas. One possible defect-formation mechanism is described in Figure 5. The quartz surface, originally formed through flame hydrolysis, is subject to slow hydrolysis, gen-erating labile silanols. Further hydrolysis may lead to Si-O-Si and more silanol formation. Silanols can react with ammo-nium in ambient conditions. Oxygen ions on a quartz surface attract ammonium ions to form ammonium sulfate. Similarly, cyanuric acid reacts with surface silanols, followed by further crystallization.7, 10

Case A2 – Contamination initiated on clear in low-to-medium-MEEF areasComparatively, contaminants grown on clear in low-MEEF areas have less impact than those accumulated in high-MEEF areas. Nevertheless, depending upon a number of factors, such contaminants can grow substantially, as shown in Figure 6. The transmission loss, however, is significantly smaller than it is in the high-MEEF area. The defect image on the left is almost invisible to the naked eye. A possible reason is that defects can easily form on a quartz surface, then immediately spread laterally in all directions, as opposed to stacking in a direction normal to the quartz surface. This single-layer, low-aspect-ratio crystal defect has such low modulation that it can be detected only at standard sensitivity. The associated MEEF is quite low, thus the defect is detected only by the standard HiRes detector and not by Litho3.

Such preferential crystal growth has been widely observed in clear, open areas on photomasks. Change in environmental and kinetic factors could favor continuous crystal growth into multiple layers or lamellar structures, if the temperature and humidity are at low levels or if the crystal growth has under-gone its nascent state and new nuclei fall upon the first-layer crystal.22-24

B. Contamination initiated on MoSi

Case B1 – Contamination in high-MEEF areasDue to the high surface energy of opaque features on reticles, it is possible that contaminants initiate on MoSi or chrome in addition to quartz. Moreover, deposited MoSi surfaces with Mo-Si structures have dangling silanols that potentially act as nuclei leading to crystal growth. Though the size of nuclei formed on the MoSi surface is comparable to the size of those formed on quartz, the instances of crystal growth on MoSi and chrome are significant. At the same moisture level, MoSi and chrome retain water for a longer time, leaving nucleation sites even after evaporation.

Upon nucleation, contaminants initiated on dark in high-MEEF areas undergo rapid crystal growth due to associated low interfacial surface energy. Moreover, once sulfate crystals are formed at the first layer, more sulfate crystals are devel-oped at a faster rate than that of the first layer, at the expense of sulfur ions, ammonia and carbon dioxide in the ambient. Therefore, any surface that provides the greatest surface energy and stable silanols through which nuclei reside is subject to crystal contamination. Sulfate crystal growth, or the second stage of crystallization, plays a role second in importance to

Figure 4: IDefects grown on clear in high-MEEF area captured by Litho3.

(SiO2 )x + 2H2O ↔ (SiO2 )x-1 + Si(OH)4

=–Si-O-Si =– + H2O + 2=–Si-OH

=–Si-O- + =– Si-OH ↔ =–Si-O-Si =– + OH-

Si Si Si Si Si Si Si

O O O O O O

OH O- OH OH OH O- OH

H+ H H+H H+ H H

N

H

N

H

NH2

H

O

S

N

H

N

H

N

H

N

H

NH2

H

O

S

Quartz surface

Figure 5: Ammonium sulfate formation on quartz.

Figure 6: Defects grown on clear in low MEEF not captured by Litho3. The localized detection sensitivity is the same as the full sensitivity of the standard detector (no sensitivity enhancement).

Figure 7: Litho3 detection of defects grown on dark in a high-MEEF area. The localized detection sensitivity is 150% higher than the sensitivity in the low-MEEF area.



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nucleation in sulfate crystallization. Figure 7 gives an example where the crystals aggregated on a MoSi surface.7, 10, 24

Case B2 – Contamination initiated on MoSi in low-MEEF areasContaminates initiated on dark in low-MEEF areas, in most cases, have little impact on printability as validated by Litho3/XLINK connectivity. The MEEF calculation is determined by the design feature as well as the presence of contamination; de-fects are given slightly higher-than-standard sensitivity, hence are captured by Litho3. The Litho3 parameters as determined from cases A1 (contamination on clear in high MEEF) and A2 (contamination on clear in low MEEF) can be applied directly to B2 (contamination on dark in low MEEF) features (Figure 8). Nevertheless, large-size contamination may be possible as a result of severe contamination, similar to case B2 (contamina-tion initiated on clear in low MEEF). When crystals grow fur-ther into the quartz area, the contamination migrates to case C3 (contamination initiated from clear/dark in low MEEF).

C. Contamination initiated on Qz/MoSi edge

Case C1 – High MEEF contamination In contrast to case B (contamination initiated on dark), more contamination is observed at the edge of clear/dark. One possi-ble cause is that the deposited MoSi provides nucleation sites, yet the border of quartz/MoSi, i.e., the etched MoSi surface, is more reactive in nature and enriched with labile, unprotected Mo-Si bonds that are more susceptible to moisture attack.17-19 A schematic of EPSM is shown in Figure 9 to better illustrate this effect. A similar rationale can be applied to the border of quartz/chrome, where the etched chrome surface tends to at-tract more moisture than does the bulk chrome. This suscep-tibility to moisture attack is more pronounced and is dramati-cally magnified in dense geometries or high-density device patterns, particularly in the presence of assist features.

Upon nucleation at the border of the Qz/MoSi edge, sulfate contaminates grow tangentially to the border, where the inter-facial surface energy is at its minimum. It is not uncommon for the crystals to grow more preferentially into the quartz side than into the MoSi side, due to the difference in the interfacial surface energy involved. Similarly, in the case of COG, the sulfate crystals grow further into the quartz side than into the chrome side. The crystal growth of this type of defect occurs at a faster rate than on either bulk quartz or MoSi or chrome; this has a deleterious effect on defect printability, as severe bridging could result.24

It is noteworthy that assist features, including dark and clear, can lead to a greater quantity of printing defects as a result of this type of contamination. Depending upon the defect disposi-tion and the cleaning strategy, contaminates that originate from the edge of the primary clear/dark feature can eventually develop preferentially in a tangential direction, thus connect-ing the neighboring assist features to the main features. Once it reaches the neighboring assist features, the contamination has a high probability of growing in a direction normal to the reticle surface rather than continuously outgrowing tangentially beyond the assist feature itself. These 3-D defects, in effect, entrap the growth in the confined space between primary and assist features; hence they accumulate next to the primary ge-ometry. Thus formed, crystals of significant dimension in both height and width could potentially alter the defect printability of assist features. In the Litho3 optimization, both the upper and lower limits in the Litho3 parameters need to be prudently selected to include the defect in the assist feature, such that the NILS (Normalized Image Log Slope) contains a large enough sample size. After Litho3 implementation, the defects should have high MEEF and high sensitivity. Defects in this category also possess high modulation that differentiates them from the noncritical defects.

SRAFs are intuitively classified as low-MEEF (low-sensitivity) regions. However, a better understanding of the defect-forma-tion mechanism as described above suggests that SRAFs have a strong tendency to develop sulfate contamination and therefore need to be treated as higher-sensitivity regions. In the MEEF map, one would need to extrapolate the NILS from the main feature to the assist features, such that the defects are given the same high sensitivity as would have been observed in the primary features. Therefore, these assist features are treated as identical to the primary features in Litho3 optimization.

Case C2 – Low MEEF contaminationContaminates initiated on clear/dark in low-MEEF areas (Fig-ure 10) have less significant printability impact than defects initiated on clear/dark in high-MEEF areas (Figure 11). When the defects become large in size, the crystal growth pattern folds into case A2 (contamination initiated on clear in low MEEF). As discussed above, defects can easily form on the clear/dark edge surface and be immediately followed by outgrowth laterally in all directions, as opposed to stacking in a direction normal to the quartz surface. However, due to the defect’s close-ness to the clear/dark edge, its corresponding MEEF values are higher than those in case B (contamination initiated on clear in low MEEF). Therefore, despite the relatively low modulation

Figure 8: Litho3 detection of defects grown on dark in low MEEF. The localized detection sensitivity is the same as the full sensitivity of the low-MEEF area.

Quartz

EPSM

Figure 9: Schematics of EPSM on quartz, where the etched sidewall could potentially provide additional nuclei for crystal growth.



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in the clear/dark border, these single-layer crystal defects are given slightly higher-than-standard sensitivity and are thus detected by Litho3.

Litho3 Integrated Automatic Defect Optimization

The aforementioned surface contamination, in particular the bridging defects, is significant regarding printability. The bridging locations may vary depending upon the device design, e.g., primary line to primary line, primary line to assisted line, or primary line ends (LE/LE). Among those de-signs, regions with the highest MEEF correspond to the high-est criticality, hence are ranked as having the highest defect printability based on which Litho3 parameters are computed.

To understand the correlation between MEEF and Litho3 parameters, MEEF was calculated on several representative device features where corresponding Litho3 parameters were optimized. Figure 12 gives an example of how Litho3 param-eters can be computed. The top figure shows a processed or remapped gray-scale image in which upper and lower limits were applied before remapping. Zones I-V denote the regions with the different MEEF values, with the dense region IV having the highest MEEF. The bottom figure shows sensitiv-ity versus MEEF, illustrating how Litho3 was applied to the processed gray-scale image. Litho3’s full sensitivity was higher than HiRes or standard sensitivity (solid blue line), in which the MEEF factor was not accounted for. Zones I-V are located in the sensitivity versus MEEF chart, in which Zone IV was the highest MEEF area and Zone I the lowest. L3C was the adjusting parameter to determine which MEEF value defects were given the full Litho3 sensitivity.

Upon Litho3 optimization, a total of 568 defects were captured, whereas 115 defects were binned into Litho3 (as previously illustrated in Figure 2). These L3itho defects were then sorted based on their corresponding MEEF values; the re-sulting histogram is shown in Figure 13. As discussed earlier, this reticle was subject to lithography processing, in which five printed defects were detected (Figure 11) with effective MEEF values that were among the highest of the Llitho3 defects. Re-sults from other reticles also suggest that printed defects were found in geometries of the highest MEEF values. If one were to draw a 20% line on the MEEF histogram to separate the high-MEEF defects from all Litho3 defects, the number of the defects to be reviewed would be significantly lower than that of the original Llitho3 bin; in fact, printed defects are conve-niently included in this top 20% MEEF group.

Figure 10: Litho3 detection of defects grown on clear/dark in a low-MEEF region. The localized detection sensitivity is the same as the full sensitivity of the MEEF region.

Figure 11: Litho3 detection of defects grown on clear/dark in a high-MEEF area. The localized detection sensitivity is higher than the full sensitivity at the low-MEEF region.

I

I

Sensitivity

Lo MEEF

HiR FullSense

L3 FullSense

Hi MEEF

II

II

III

III

IV

IV

V

V

I=255

I =128

L3C = 50

I = 0

Figure 12: An example of Litho3 optimization of a device geometry representing the reticle under inspection. Top: Processed gray-scale trace of mask inspection. Bottom: Illustration of how L3C is defined.

Effective MEEF MapDefect GS Image

Effective MEEF

00

2 4 6 8 10

10

20

30

10

50

60

12 14 16 18 20

Def

ect

Co

un

t

Figure 13: Histogram of Litho3 defects of corresponding effective MEEF values. Printable defects are among the top 20% of the high-est MEEF group, which includes the printed defects.



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Applying this 20% MEEF guideline can potentially enhance wafer fab productivity by enabling quick and sane decisions as to whether the reticles need to be cleaned or quarantined.

Naturally, one could debate that some defects found in low-MEEF regions could potentially print on wafers. This argument may be valid, yet it can be addressed in two ways. First, defects of similar size generally have greater printabil-ity in high-MEEF than in low-MEEF regions. In cases where the contamination is so severe that defects in the low-MEEF region impact reticle quality, the same is expected of defects in the high-MEEF region. According to our 20% MEEF line, such highly suspected defects in the high-MEEF area would then be immediately reviewed, leading to the determination that the reticle is heavily contaminated. Second, defects tend to aggregate and stack up in dense or high-MEEF regions, whereas in the sparse or low-MEEF regions, crystals have the tendency to spread across quartz, resulting in less printability impact.

Take another, closer look at the 20% MEEF check rule. Defects found in the same device geometry (Figure 14) are initiated in different locations. The defect on the left (Figure 14a) originated from almost the end of the primary feature and

developed tangentially onto the next primary feature, bypassing the neighboring assist line. The defect on the right (Figure 14b) originated from the midsection of the primary feature, devel-oped tangentially onto the assist line, then stopped. Such crystal growth patterns agree with our earlier discussion that crystals are more likely to propagate on quartz than on EPSM. Moreover, the defect in Figure 14b has greater transmission loss than that in Figure 14a, mainly due to the stacking of the crystals in a direction normal to the surface, which is subject to UV degrada-tion under lithography. Due to the defect impact, the defect in Figure 14b has a higher MEEF than it would without a defect. In the same way, the defect in Fig-ure 14a has higher MEEF than it would without a defect; however, its effective MEEF (= 9) is lower than that in Figure 14a (effec-tive MEEF = 11). Both defects were included in the top 20% MEEF category to be reviewed by the fab user. Therefore, the 20% MEEF check rule enables users to quickly detect crystal growth in order to make timely decisions.

As MEEF value maps are available in the current KLA-Tencor TeraScan system, automatic Litho3 detection with the 20% MEEF rule implemented can be activated where users, upon completion of defect inspection, need only review a small por-tion of the total defects to determine whether the reticle needs cleaning. Since the number of Litho3 defects is smaller than the total defect count, applying the 20% top MEEF rule allows us-ers to review less than 20% of the total defects to make sensible decisions. Therefore, productivity can be substantially enhanced. Adopting this MEEF-enabled Litho3 detection scheme would also benefit reticle requalification for contamination detection. For the same reticle, MEEF values can be calculated automati-cally, with the associated defects immediately flagged for users to review, enabling them to make decisions even before completing the full reticle inspection.

ProlithTM was implemented to help verify defect printabil-ity (Figure 15). Defects from cases A and F were chosen for simulation and wafer print comparison, such that defect A had a MEEF higher than the 20% MEEF line, and defect F had a MEEF below the 20% line. Both simulation and wafer print results were quite consistent, demonstrating that the defect initiating from clear in high MEEF (top) caused a greater than 10% CD variation and printed on the wafer. The defect from

(a) (b)

Figure 14: Defect grown at similar device geometry included in the 20% top MEEF defects.

Figure 15: Simulation and wafer validation result of printable defects at 193nm lithography at varying exposure conditions, NA 0.9. Left: Defect inspection image. Middle: Wafer print results. Right: Simulation results.



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clear/dark in a relatively low-MEEF area (bottom), though grown adjacent to the assist line, remained undetected at the wafer plane.

Conclusions

As validated by lithography exposure via XLINK, Litho3 captured all critical defects, including the ones that could ulti-mately print on the wafer and substantially impact production yield. The number of defects to be reviewed prior to cleaning and disposition was significantly reduced compared to when Litho3 was not implemented.

Contamination was found to be most severe in low k1 reticles, particularly in high-MEEF regions. Such defect behavior was associated with high retention of ammonium ions at the quartz surface, followed by confined crystal growth in the dense region, leading to considerable optical transmission loss.

Detailed MEEF and defect formation analyses were carried out for Litho3 defects, through which we found that defects with high MEEF tended to have greater printability. Therefore, the criticality of Litho3 defects could be ranked based on their corresponding MEEF values. Only defects with the highest MEEF needed to be reviewed by users to quickly identify crystal growth. The highest-MEEF group from our printabil-ity study was composed of the top 20% MEEF. Such improved MEEF-driven automatic defect inspection can improve pro-ductivity by >80%. Moreover, such capability could further improve productivity in reticle requalification, where high-MEEF defects can be immediately flagged before completion of inspection.

This paper was originally published in the Proceedings of the 18th Annual IEEE/SEMI Advanced Semiconductors Manufacturing Conference (ASMC 2007), 11-12 June 2007, Stresa, Italy.

Acknowledgements

The authors would like to express appreciation to the following individuals for their valuable discussions and contributions: Yalin Xiong, Lih-Huah Yiin and Zhian Guo of KLA-Tencor Corp.

References

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2. H. Ishii, A. Tobita, Y. Shoji, H. Tanaka, A. Naito, H. Miyashita. Root cause analysis for crystal growth at ArF excimer laser lithography, Photomask and Next-Generation Lithography Mask Technology XI. Proceedings of SPIE, Vol. 5446, pp. 218-224, 2004.

3. P. Marmillion, W. Trybula, B. Grenon. Advanced photomask cleaning, 24th Annual BACUS Symposium on Photomask Technology, Weed. Proceed-ings of SPIE, Vol. 5567, pp. 506-510, 2004.

4. E.V. Johnstone, L. Dieu, C. Chovino, J. Reye, D. Hong, P. Krishnan, D. Coburn, C. Capella. 193nm haze contamination: A close relationship between mask and its environment, 23rd Annual BACUS Symposium on Photomask Technology. Proceedings of SPIE, Vol. 5256, pp. 440-448, 2003.

5. J. Choi, H.S. Lee, J.S. Jung, B.C. Cha, S.G. Woo, H.C. Cho. Substrate effects on the characteristics of haze defect formation on the photomask surface under exposure condition. Proceedings of SPIE, Vol. 6607, p. 4590.

6. W. Chou, Y.F. Cheng, S.M. Yen, J. Cheng, P. Peng, J. Huang, T. Huang, D. Wang, E. Chen, C.Y. Hsiang, K. Bhattacharyya, A. Dayal. A novel run-time MEEF-driven defect disposition extending high-resolution contamination inspection to next-generation photomask. Proceedings of SPIE, Vol. 6607, p. 2390.

7. Sb. Nauch, Tr., Investigation of ammonium sulfate crystallization in a pseudo-liquefied layer. Kuzbas Politekh Int., No. 26, 1970.

8. S. Banerjee, C.C. Lin, S. Su, C. Bowers, H.F. Chung, W. Brandt, K. Tang. Characterization of photomask surface cleaning with cryogenic aerosol tech-nique

9. J. Huang, L.H. Peng, C.W. Chu, K. Bhattacharyya, B. Eynon, F. Mirzaagha, T. Dibiase, K. Son, J. Cheng, E. Chen, D. Wang. Process window impact of progressive mask defects, its inspection and disposition techniques (go/no-go criteria) via a lithographic detector, SPIE 2005

10. A. Pant, M.T. Parsons, A.K. Bertram. Crystallization of aqueous ammo-nium sulfate particles internally mixed with soot and kaolinite: crystalliza-tion relative humidities and nucleation rates, J. Phys. Chem. A, 110(28), pp. 8701-8709.

11. B. Grenon, W. Volk, K. Bhattacharyya, A. Poock. The Crystal Growth and Reticle Degradation Expose

12. B. Grenon, C. Peters, K. Bhattacharyya, W. Volk. Formation and detection of sub-pellicle defects by exposure to DUV system illumination, 19th BACUS Symposium on Photomask Technology. Proceedings of SPIE, Vol. 3873, p. 162, 1999.

13. K. Bhattacharyya, W. Volk, D. Brown, J. Ayala, B. Grenon. Investigation of reticle defect formation at DUV lithography, 22nd BACUS Symposium on Photomask Technology. Proceedings of SPIE, Vol. 4889, p. 478, 2002.

14. K. Bhattacharyya, K. Son, B. Eynon, D. Gudmundsson, C. Jaehnert, D. Uhlig. A reticle quality management strategy in wafer fabs addressing progressive defect growth problem at low k1 lithography. Proceedings of SPIE, Vol. 5853, p. 525, 2005.

15. B. Grenon, K. Bhattacharyya, W. Volk, K. Phan, A. Poock. Reticle surface contaminants and their relationship to sub-pellicle defect formation. Proceed-ings of SPIE, Vol. 5375, p. 355, 2004.

16. K. Bhattacharyya, M. Eickhoff, B. Grenon, M. Ma, S. Pas. An investigation of a new generation of progressive mask defects on the pattern side of advanced photomasks. Proceedings of SPIE, Vol. 5752, p. 1257, 2005.

17. D.W. Lee, H.Y. Jung, M.S. Kim, J.S. Lee, Y.K. Choi. Effect of UV/O3 treatment on mask surface to reduce sulfuric residue ions, 24th Annual BACUS Symposium on Photomask Technology. Proceedings of SPIE, Vol. 5567, 2004.

18. R. Schmid, A. Zibold, K. Bhattacharyya, X. Chen, B. Grenon. Evaluation of printability of crystal growth defect in a 193 nm lithography environment using AIMS. Proceedings of SPIE, Vol. 5567, p. 1035, 2004.

19. S. Osborne, M. Nanninga, H. Takahashi, E. Woster. Mask cleaning strate-gies: haze elimination. Proceedings of SPIE, Vol. 5992, p. 1013, 2005.

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22. H. Ishii, A. Tobita, Y. Shoji, H. Tanaka, A. Naito, H. Miyashita. Root cause analysis for crystal growth at ArF excimer laser lithography. Proceedings of SPIE, Vol. 5446, p. 218, 2004.

23. F. Eschbach, D. Selassie, P. Sanchez, D. Tanzil, V. Tolani, M. Toofan, H. Liu, B. Greenebaum, M. Murray, R. Villacorta. ArF lithography reticle crys-tal growth contributing factors. Proceedings of SPIE, Vol. 5567, p. 497, 2004.

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Inspection Tool Evaluation Methodologies

Many parameters are considered when evaluating optical patterned wafer inspection tools for a fab’s particular yield-monitoring strategy. Some are economic factors, such as capital cost, cost of ownership, and platform extendibility. Others are implementation factors, such as ease of recipe setup and automated defect-binning capability. However, the most criti-cal factor to consider is an inspector’s effectiveness at detecting defects of interest for a range of inspection points, at the high-est possible speed.

Most inspection tool manufacturers publish graphs of sensitiv-ity (represented by pixel size) versus throughput (Figure 1). In general, higher-sensitivity modes run at lower throughputs. However, the ability of an inspection system to capture defects of interest on layers of interest is determined by more than just pixel size. Rather, inspector sensitivity is a complex entity affected by tool parameters such as peak wavelength, wave-length spectrum, numerical aperture, optical aperture, and detection algorithms. Inspector sensitivity also varies with layer, device, and design rule.

We have found through experimentation that published sensi-tivity and throughput specifications are not a reliable predictor of real-world performance when comparing different types of inspectors or inspectors from different suppliers. Sensitivity specifications are often based on pixel sizes, but pixel size alone is not a direct determinant of ultimate sensitivity. Further-

more, published throughput specifications are often based on a specific measurement methodology that can vary among inspector suppliers. These published throughputs also depend on factors such as inspected area, and may not represent the actual throughputs observed in the fab on production wafers. Hence, the use of published specifications for tool comparisons is often an inaccurate representation of actual tool performance.

A better tool comparison methodology uses data on actual production wafers from a supplier demonstration or an on-site evaluation. This allows for a more accurate determination of

fAb eConoMiCs

A New Decision Paradigm for Comparing Patterned Wafer InspectorsJustin Arrington, Paul Johnson – Micron Technology, Inc., Ali Salehpour, Andy Phillips, Gangadharan Sivaraman, Anthony Moore, Ray Campbell, Wade Jensen – KLA-Tencor Corporation

Today’s optical patterned wafer inspectors cover a range of configurations, including brightfield, darkfield, and

brightfield/darkfield combination tools. With so many choices, selecting a tool that meets a fab’s yield-monitoring require-

ments can be a complex endeavor. How should fab management efficiently decide which tool provides the best overall return

on investment in terms of cost, defect capture, and yield acceleration? A new decision methodology has been developed that

creates a metric for this evaluation process: weighted average throughput in production (WATIP).

Thro

ug

hp

ut

Pixel A Pixel B Pixel C Pixel D Pixel E Pixel F Pixel G Pixel H

Sensitivity

Figure 1: Data demonstrating the inverse relationship between sensitivity—represented as a pixel size—and throughput for an optical patterned wafer inspector. Higher-sensitivity pixels have a lower throughput.



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the pixel sizes necessary to meet specific yield-monitoring requirements. This also allows the chipmaker to measure ac-tual inspector throughput on production wafers. Further, this methodology allows a chipmaker to accurately determine the relative throughputs of inspectors at the sensitivity required for a specific subset of process layers. Based on the monitor-ing requirements of a production environment, some of these process layers may be inspected more frequently than others, affecting the overall inspector capacity. Thus, the downside of this comparison methodology is that it does not take into con-sideration how these process layers fit into the overall desired production usage of the inspection tool.

A new, more complete evaluation methodology involves the use of a parameter called the weighted average throughput in production (WATIP). WATIP breaks down the expected production utilization of an inspection tool by layer, or by in-spection segment. For each layer, the sensitivity requirements determine the optical mode, pixel size, and algorithm utilized. The pixel size determines the inspector’s throughput at a given layer. Additionally, the expected average capacity for each layer is used as a weighting factor for each layer’s throughput. The overall WATIP of the inspector is the sum of each individual layer’s weighted throughput. WATIP takes into account the sensitivity, throughput, and capacity requirements of each layer projected to run on the inspector. Moreover, it recognizes that different tools meet a particular sensitivity requirement at different throughputs, and that evaluating these differences is a critical factor in tool comparisons. The following section presents an overview of how WATIP is calculated.

Calculating Weighted Average Throughput in Production (WATIP)

WATIP is a new decision methodology for comparing the performance of different inspection tools. WATIP provides an accurate assessment of the overall production throughput of an inspector by taking into account sensitivity, throughput, and layer capacity. It determines the production throughput

of each tool once a particular sensitivity requirement has been met. WATIP is calculated using the following

In this equation, TPT is the measured throughput. Average capacity is a weighting factor comprised of the percentage of inspection capacity used for each layer or inspection segment. Table 1 shows how WATIP is calculated and compared for two different inspectors.

In Table 1, the operating points where the inspector will be used are shown in the green shaded boxes. These can either rep-resent specific process layers or more general layer categories. The inspection points in Table 1 are typical layer categories for production utilization of a high-end brightfield inspector. In section A of the table, the average capacity is entered as a percentage. This can be based on benchmark data or actual pro-duction usage of the tool. In section B, the pixel sizes needed to meet the sensitivity requirements of each layer are listed. These pixel sizes are based on benchmark data or evaluation data from the different inspection tools. The throughput for each pixel size is entered in section C of the table. These throughputs can be acquired from the supplier’s standard specification sheet for the tool or, for better accuracy and measurement consistency, determined from timing data collected on the different inspec-tors using the chipmaker’s wafers. Finally, the WATIP for each layer or layer category is calculated in section D by multiplying the average capacities given in section A by the throughputs in section C. The overall WATIP for the tool is obtained by summing the WATIP calculation for the individual layers. In this example, Inspector B has a WATIP that is 1.6x higher than Inspector A. This comparison is meaningful because it utilizes throughputs for each inspection segment that meet the sensitivity requirements, and takes into account the capacity utilization for each segment.The higher WATIP provided by Inspector B would translate into improved lot sampling and contribute to a lower inspector cost of ownership.

fAb eConoMiCs

A Etch CMP Litho

Etch: Critical Etch: Non-Critical CMP: Line Monitor Litho: ADI

Average Capacity (weighting) 24% 24% 10% 42% 100%

B Etch CMP Litho

Pixel Size Based on Benchmark Data Etch: Critical Etch: Non-Critical CMP: Line Monitor Litho: ADI

Inspector A Pixel 0.16μm 0.16μm 0.26μm 0.12μm

Inspector B Pixel 0.16μm 0.28μm 0.20μm 0.16μm

C Etch CMP Litho

Throughput Based on Pixel Size Etch: Critical Etch: Non-Critical CMP: Line Monitor Litho: ADI

Inspector A TPT (wph) 2 2 4 1

Inspector B TPT (wph) 2 5 3 2

D Etch CMP Litho

Weighted Average TPT in Production Etch: Critical Etch: Non-Critical CMP: Line Monitor Litho: ADI WATIP

Inspector A WATIP (wph) 0.48 0.48 0.40 0.42 1.78

Inspector B WATIP (wph) 0.48 1.20 0.30 0.84 2.82

Table 1: Hypothetical calculation of WATIP for two inspectors. For each inspection segment, the average capacity utilization (A), pixel size needed to meet the sensitivity requirements (B), and throughput (C) are determined, and WATIP (D) is calculated. Individual layer WATIPs are summed to obtain the overall inspector WATIP. The WATIP for Inspector B is 1.6x higher than the WATIP for Inspector A. This higher WATIP translates into increased inspection capacity and contributes to lower inspector cost of ownership.



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WATIP: DRAM Use Case

A recent DRAM evaluation focused on two high-end brightfield inspec-tion tools for inline defect monitoring. This evaluation involved assessing the sensitivity-at-throughput of the inspectors on ten process layers. One of these inspectors was KLA-Tencor’s 2800 broadband brightfield patterned wafer inspector. For each process layer, one “Production” (high throughput) inspection recipe and one “Engineering” (lower throughput, higher sensitivity) inspection recipe were developed on each tool. The resulting inspections were compared based on sensitivity to critical defects, suppression of SEM Non-Visuals (events detected by the optical inspection system that are not re-detected during SEM review), and throughput. For each process layer, the inspection recipe that best met the sensitivity requirements at the highest throughput was determined for each tool. Then, based on expected capacity utilization of each inspection point, the WATIP for each inspector was calcu-lated. Complete data are presented for one process layer.

Inspector performance was compared for a poly CMP process layer. Initially, two inspection recipes were created for each tool on this layer—a high-sensitivity (lower throughput) recipe and a high- throughput (lower sensitivity) recipe. It was found that the high-throughput recipe provided sufficient sensitivity to the defects of interest, and therefore further analysis was limited to only this throughput mode. Figure 2 shows a defect Pareto comparing the inspec-tion results from the high-throughput recipes of the two different inspectors. Although the SEM Non-Visual rate for Inspector B (4.2%) was lower than that for Inspector A (8.8%), the rate for both tools was below the prescribed limit of 10%. The defect Pareto shows that Inspector B provided higher capture of defects of interest than Inspector A, although both tools met the minimum defect detection requirements for the layer. Based on the expected capacity utilization of this inspection in produc-tion, Inspector A had a WATIP of 3wph, while Inspector B had a WATIP of 4wph. Overall, the high-throughput recipe of Inspector B provided

fAb eConoMiCs

SurfaceParticle

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Figure 2: Pareto comparing defect capture on a poly CMP DRAM wafer. Inspector B is KLA-Tencor’s 2800 broadband brightfield patterned wafer inspector (2800). The high-throughput recipe of the 2800, with a WATIP of 4wph, provided the highest sensitivity-at-throughput and was therefore the better inspection to use for yield monitoring on this layer.

Small EmbeddedParticle

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Defect count 15-150x higherthan maximum chart value

Inspector C, SlowInspector C, MediumInspector D (9150), MediumInspector D (9150), Fast

Figure 3: Pareto comparing defect capture on a nitride deposition NAND flash wafer. Inspector D is KLA-Tencor’s Puma 9150 darkfield patterned wafer inspector. For each tool, two inspection recipes covering different throughputs were compared. The high-throughput (fast) recipe of the Puma 9150, with a WATIP of 21wph, provided the highest sensitivity-at-throughput and was therefore the better inspection system to use for yield monitoring on this layer.



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better capture of defects of interest at a lower SEM Non-Visual rate and a higher throughput. Thus, for this particular process layer, the best sensitivity-at-throughput was provided by Inspector B.

Using similar analyses on data from ten process layers, it was determined that the overall WATIP for Inspector B was appro-ximately 30% higher than the WATIP for Inspector A. Thus, Inspector B best met the yield-monitoring requirements for this DRAM technology node.

WATIP: NAND Flash Use Case

In addition to brightfield DRAM comparisons, NAND flash devices were used to evaluate two darkfield inspection tools for inline defect monitoring. One of these inspectors was KLA-Tencor’s Puma 9150 darkfield patterned wafer inspector. Several different inspection recipes covering different through-puts were developed on each tool for each process layer. The resulting inspections were compared based on detection of critical defects and suppression of SEM Non-Visuals. For each process layer, the inspection that provided the best sensitivity at the highest throughput was determined for each tool. Then, based on expected capacity utilization of each inspection point, the WATIP for each inspector was calculated. Complete data are presented for one process layer.

Inspector performance was compared for a nitride film deposi-tion process layer. For each tool, two inspection recipes utiliz-ing different throughputs were developed with the goal of achieving the best possible sensitivity. The recipes for Inspec-tor C covered a slow-throughput mode and a medium-through-put mode. The recipes for Inspector D covered medium- and fast-throughput modes. A defect Pareto comparing the inspec-tion results from the two different darkfield tools is shown in Figure 3. These results show that the slow recipe of Inspector C had a SEM Non-Visual rate of 33%, well above the limit of 10%, and thus was removed from further consideration. The SEM Non-Visual rates for the medium recipe of Inspector C (6.6%) and for both recipes of Inspector D (0%) were below the limit of 10%. These results further show that Inspector D provided much higher capture of defects of interest, including unique capture of residue defects, compared to Inspector C. The inspection recipes that provided the best sensitivity-at-throughput for each tool were the medium recipe of Inspector C and the fast recipe of Inspector D. Based on the expected capacity utilization of this inspection in production, the medium recipe of Inspector C had a WATIP of 13wph and the

fast recipe of Inspector D had a WATIP of 21wph. Overall, the fast recipe of Inspector D provided better defect capture at a higher WATIP, and thus was the better tool for yield monitor-ing on this particular process layer.

Similar data were collected from thirteen different process layers. For each layer, two inspection modes were evaluated—high sensitivity (lower throughput) and high throughput. Based on these analyses, it was determined that the overall WATIP for Inspector D was approximately 4x higher than the WATIP for Inspector C for the high-sensitivity inspec-tions, and approximately 2x higher for the high-throughput inspections. Thus, Inspector D best met the yield-monitoring requirements for this NAND flash technology node.

Conclusion

With today’s optical patterned wafer inspectors covering a range of configurations, it is important to utilize a tool selec-tion paradigm that effectively evaluates production perfor-mance. Current decision paradigms that rely on a supplier’s published specifications based on pixel size can be a poor predicator of real-world sensitivity-at-throughput, as sensitiv-ity depends on multiple tool parameters and throughput can vary depending on measurement methodologies and factors such as area inspected. Furthermore, the utilization of the inspector for each inspection point can significantly affect the measure of an inspection system’s overall performance.

This paper introduced a new decision paradigm that utilizes a parameter called the weighted average throughput in produc-tion (WATIP). For each inspection point, WATIP takes into account the throughput of an inspector at required sensitivity and the expected capacity utilization of that inspection. The WATIP methodology efficiently and effectively determines which inspector provides better performance with lower capi-tal costs. The details of calculating WATIP and a hypothetical example of how to use WATIP to compare two inspectors were presented. Finally, two use cases involving the comparison of different inspectors for memory defect monitoring were discussed. These use cases demonstrated how a comparison methodology using WATIP can help to effectively determine which tool is best for a fab’s particular yield-monitoring requirements.

Acknowledgements

The authors would like to thank Shawn Lyonsmith, Ryan Spear, David Daycock, and Jon Morgan of Micron Technology; and Adrian Wil-son, Matthew McLaren, Cathy Perry-Sullivan, Becky Pinto, and Mark Dishner of KLA-Tencor for their assistance with this paper.

WATIP compares the overall production throughput of different

inspection tools by evaluating sensitivity, throughput, and

layer capacity.

fAb eConoMiCs



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inspeCtion

Influence of Immersion Lithography on Wafer Edge Defectivity I. Pollentier – IMECA. Somanchi, F. Burkeen, S. Vedula – KLA-Tencor Corporation

During immersion exposure, particles can be transported from the wafer edge area to the printed area or scanner’s

wafer stage. In this study, an automated wafer edge inspection system that provides full-wafer edge imaging and

defect classification demonstrated the impact of immersion lithography on wafer edge defectivity. The work revealed

key challenges to controlling wafer edge-related defectivity, including choice of resist and optimization of EBR recipes.

Introduction

In semiconductor manufacturing, the control of defects at the edge of the wafer is a key factor in keeping the number of yielding die on a wafer as high as possible. The removal of photoresist from the wafer backside and edges is especially important in order to avoid contact between the resist and the scanner stage or wafer-handling hardware. Typically, a solvent edge bead removal (EBR) step is the last step in the coating recipe: the combination of a solvent stream from a static nozzle towards the wafer back side and a dynamic nozzle towards the wafer front side dissolves the resist up to a few millimeters from the wafer's outer edge. The desired position of the EBR material edge at top side (the so-called EBR-width) can depend on the coated material (e.g., antireflective topcoat versus photoresist material) and/or on the layer within the device (e.g., a contact hole lithography process might use

a slightly different EBR width than the gate process). In order to increase die yield, it’s desirable to have EBR widths that are as small as possible.

Immersion lithography1–4 changed the defectivity issues at the wafer edge significantly. During the immersion exposure sequence the wafer edge is in contact with the water from the immersion hood (IH), introducing additional concerns beyond direct contact of resist with the scanner. First, when the IH is scanning in the EBR region, its movement can damage mate-rial edges (Figure 1a). IMEC’s program on immersion lithogra-phy found that, for example, photoresist material can partially peel off during the IH pass (Figure 1b).

A second concern involves the cleanliness of the wafer edge outside the EBR edges. The IH pass wets not only the near-edge top surface, but also the curved wafer edge and even part of the bottom surface. Defects can be released from this area and redeposited either on the wafer or on the wafer stage. In the first case, there will be a direct impact on the wafer defec-tivity. In the latter case, defects present on the wafer stage can still be transported onto wafers in subsequent wafer process-ing. IMEC’s program on immersion lithography found that resist residues left on the curved wafer part by an incomplete EBR step can be damaged by the IH pass, releasing fragments into the system (Figure 1c).

Traditional defect inspection techniques have serious limi-tations when monitoring these new issues. Conventional darkfield or brightfield inspection tools cannot access the wafer edge, since these systems typically have an edge exclusion of ~3mm. While microscopy tools can inspect the edge area, they can only give qualitative information, and give typically limited sampling information for the wafer edge.

wafer stagewafer

Damage/adhesion failure of material EBR edge (a)

(b) (c)

Transport of wafer edge contamination towards stage or wafer die region

coated materials

immersion hood

TCX007

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Figure 1: (a) Schematic representation of possible defect issues with immersion lithography; (b) example of damaged photoresist material inspected with topdown optical microscope; (c) example of damaged residues at the wafer edge, inspected by tilted SEM (45°).



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This study used a new automated edge-inspection system, called VisEdge® CV300 (from KLA-Tencor), that provides full wafer edge imaging (top near edge, top bevel, apex, bot-tom bevel, and bottom near edge) using laser-based optics and multisensor detection. The system then uses automated defect classification (ADC) software to classify the defects of interest (DOI).

VisEdge Technology for Wafer Edge Defect Inspection

The VisEdge technology for wafer edge defect inspection (Figure 2) is based on a laser source directed to the wafer edge surface. Four detectors simultaneously collect the scattered light, the specular or reflected light, the phase shift in differ-ent polarizations, and topography information. As the laser scans the wafer edge surface, each signal can be converted into an image. Each type of defect produces a specific combination of signals, making ADC possible.

Imaging of the WaferEdge

Imaging covers the entire edge region, including the following areas: ~5mm bottom near edge, bottom bevel, apex, top bevel, and ~5mm top near edge. Scanning generates a continuous high-resolution image for the entire wafer edge, which can be interpreted as a Mercator projection or an unfolding of the wafer edge surface into a flat plane.

Since the full wafer edge is scanned during the measurement, it is possible to represent the whole circumferential edge as an image. Excursions in eccentricity and/or in EBR width, which might result in a layer’s edge ending on the wrong underlying substrate, can be easily monitored and corrected using this kind of inspection.

For immersion-related work on wafer edge cleanliness, a high-resolution view of the wafer edge is typically more use-ful. Here, the images view only a few millimeters of the edge. Figure 3 uses this representation to show resist flakes observed along the apex-bevel regions in the specular channel.

Immersion Defect Process Characterization and Optimization

Immersion-related defects at the wafer edge can be due to damage of the coated material edge in the EBR area, when the IH is passing over this region. On the other hand, defects can be caused by transport of particles present on the bevel. These might be released by forces of the immersion hood, transport-ed by the water in the hood, and redeposited on the wafer and/or stage. This work focuses on the latter, and in particular on the flake defects observed in past work 5.

Edge-region Flake Defects

Flake defects are related to material residues that are present on the wafer edge after coating. Typically, these residues are only present on the apex part of the bevel, and therefore are difficult to detect by conventional top-down inspection meth-ods. The residues result from a nonoptimized EBR process: since the coated material on the wafer edge can be significant-ly thicker than on the flat top region, an insufficient solvent supply can leave edge residues while the top surface is clean. This phenomenon is more commonly observed with photore-sist materials, rather than with BARC and topcoat materials.

The morphology of edge residues can depend on the resist. For some resists, the residue can be quite uniform along the apex. For other resists, large areas of thick residues are combined with areas of thin residues.

Once detected, the problem can be solved fairly easily by ad-justing the EBR recipe. Because making the EBR recipe lon-ger limits the throughput of the immersion cluster, however, fabs try to avoid this adjustment if possible. Since convention-al inspection tools like tilted SEM can only measure a limited area of the wafer edge, there is a clear risk of handing wafers with resist residues over to the immersion scanner.

When wafers with resist residues are exposed on an immersion scanner, it is difficult to predict if the IH pass over the edge of the wafer will damage the resist residue, and if (part of) the residues will redeposit on the wafer top side or on the scanner wafer stage. Tilted SEM inspections suggested qualitatively that such damage can happen with certain resists.

Phase shift

Laser beam

Specular intensity TopographyScatter

Figure 2: Schematic representation of VisEdge measurement principle.

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Figure 4: IH exposure sequence for edge flake characterization.

bottom bevel

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Figure 3: Example of a VisEdge specular image showing part of the bevel/apex region. This kind of representation is important for the evaluation of wafer edge quality.



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Experimental Conditions of Edge Flake Characterization

We experimented with three resists with different chemistries. Sensitivity to edge damage was expected to vary across the three resist types. A dedicated exposure job spatially sepa-rated the areas where flakes are expected and where they are not expected. One section, consisting of two rows of eleven fields, was exposed close to the wafer edge at the opposite side of the notch. A similar area of two rows of eleven fields was exposed in the region of the notch. During the exposure of these two-by-eleven sections at both locations near the wafer edge (Region II), the IH makes continuous up-and-down scans over the wafer edge area, increasing the probability of defect generation (Figure 4). The exposure job was also designed so that on another part of the wafer (Region I, on the right hand side), the immersion hood did not pass over the wafer edge. In Region I, no flake-like defects should be detected.

VisEdge Qualification for Edge Flake Defects

The specular image of regions with resist residues clearly showed a difference in reflected intensity: dark areas in the resist residues refer to thick layers, while light areas indicate much thinner layers. The results obtained from Resist A are detailed below.

We compared the SideScan images of areas where the IH did and did not pass. Figure 5a is a typical SideScan specular im-age for Region I (i.e., where the IH did not pass). Differences in thick and thin resist residues are visible, but no fragments of the resist residues are released. In contrast, in Figure 5b, taken from Region II, parts from the thick residue at the bottom of the apex are released. The close-up in the image indicates that some, but not all, of these edge flakes are rede-posited on the apex closer to the top area of the apex.

To determine whether any of these edge flakes end up on the top region (where it may be possible for edge dies to be

damaged), we analyzed the TopScan image of the correspond-ing areas of Fig 5a and 5b using the scatter signal, shown in Figure 5c and 5d. In Region II, a lot of particles were detected, while in Region I no particles were observed in the images. This observation was encouraging for further ADC work.

In specifying a classification algorithm to detect the edge-region flakes, redeposited edge flakes on the apex side were de-tected by setting the threshold levels for the reflectivity in the specular channel of the SideScan image. For redeposited defects in the top near-edge region, a combination of signals in the specular and scatter channels yielded more accurate detection. Once all the measurement parameters for both areas are fixed, all can be combined in a single measurement recipe. A single measurement sequence on a wafer provides defect classification and mapping for all the wafer edge areas of interest. (Figure 6.)

Immersion Process Characterization and Optimization towards Edge Flake Defects

Having qualified the inspection to classify and map edge flake defects, we used our results in a design of experiment (DOE) to improve our understanding of this kind of defect source and its key impact parameters.

Resist and Process Optimization

As indicated above, Resist A tends to generate flakes when the IH is passing over its edge. The nonoptimized coating process left residues for two other resists, B and C; however, the resi-due morphology was different.

When the same immersion exposure job was used, significantly fewer edge flakes were detected in the near top region for Resists B and C than for Resist A (Figure 7). Moreover, the re-sidual defects were less confined to the exposure zone, so some of these defects might not be related to flaking, but caused by coating and wafer handling. In the TopScan images, no clear sign of damage was seen. Clearly the choice of resist chemistry can be important to prevent this kind of defects.

As indicated earlier, resist residues can be optimized by chang-ing the EBR recipe on the coat track. Resist A showed several

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Figure 5: Specular and scatter images from Region I (a and c) and Region II (b and d) of a test wafer. As explained in the text, IH damage is more likely in Region II.

Top nearedge

Figure 6: Immersion characterization (quantification of edge flakes at wafer edge): Flakes on apex and top near edge can be quantified by composite analysis of SideScan and TopScan signals.



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hundred defect flakes with the regular (short) EBR sequence. After optimization, this resist achieved defect values similar to the background values obtained with the nonflaking Resists B and C.

Further Wafer Edge Challenges in Immersion Lithography

More kinds of defects besides the edge region flakes can be important in immersion lithography. This section discusses a few other possible defect sources.

Wafer Handling Marks and Resist Rework Process

A variety of artifacts were seen even in fresh Si wafers, pri-marily on the bevel and apex region. These wafers had very limited processing and handling. Even on a fresh Si wafer with minimal wafer handling, damage was visible in the form of particles in the apex/bevel region. This introduces an addi-tional concern with transport-related artifacts, and illustrates the need for an assessment of wafer edge quality and handling before introduction to the immersion process.

Resist Rework Processes

At IMEC, resist work is typically done by a combination of a dry ashing step, followed by a wet clean. In some cases rework is used to redo a lithography step, for instance after an out-of-spec condition. In other cases, such as on monitoring wafers for (daily) focus/dose/CD or overlay, rework can be done more frequently. Limited rework typically results in an increased presence of scratches (typically at the lower bottom bevel) and an overall increase in reflectivity variation. Where wafers are reworked more often (estimated to be approximately ten times or more), the bevel/apex area is much more affected. These defects could pose a risk when the immersion hood is passing over the wafer.

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Figure 6: Edge flake defects as a function of resist chemistry and EBR recipe.

Conclusion

In this paper, we have investigated the impact of immersion lithography on wafer edge defectivity. In the past, such work has been limited to inspection of the flat top part of the wa-fer edge due to the inspection challenges at the curved wafer edge and lack of a comprehensive defect inspection solution. This made it very difficult to detect and control defects on the nonflat part of the wafer edge. Our study used a new automated edge-inspection system that provides full-wafer edge imaging (top, side, bottom) using laser-based optics and multisensor detection, and then classifies the defects of interest with ADC software.

This technology demonstrated the impact from the immer-sion hood on wafer edge defectivity. Moreover, the work revealed several key challenges to keep wafer edge-related defectivity under control, including choice of resist, optimi-zation of EBR recipes, wafer handling, and so forth.

Acknowledgements

Diziana Vangoidsenhoven, Christie Delvaux, Bart Baudemprez, and Tom Vandeweyer for help in processing and wafer selection.Thomas Hoffmann for help in the area of immersion soak time simulations.

Philippe Foubert, Dieter Van Den Heuvel, Shinichi Hatakeyama (TEL), Kathleen Nafus (TEL), Sean O’Brien (TI), Mireille Maen-houdt, and Richard Bruls (ASML) for helpful discussions on immersion tools and related defectivity.

A version of this article was published in SPIE 2007 Metrology, Inspection, and Process Control for Microlithography XXI Confer-ence, Vol. 6518 and in Solid State Technology magazine, February 2007.

References

1. B. Smith, H. Kang, A. Bourov, F. Cropanese, Y. Fan, “Water immersion optical lithography for the 45nm node,” Proc. SPIE, Vol. 5040, p. 679-689, 2003.

2. M. Kocsis et al., “Immersion specific defect mechanisms: Findings and recommendations for their control,” Proc. SPIE, 6154 (2006), 6154-180.

3. M. Maenhoudt et al., Journal of Photopolymer Science and Technology, 19 (2006), 585.

4. M. Ercken et al., Journal of Photopolymer Science and Technol-ogy, 19 (2006), 539.

5. I. Pollentier et al., Proc. SPIE, 5754 (2005), 129.



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Metrology

Predicting Electrical Measurements by Applying Scatterometry to Complex Spacer StructuresMatthew Sendelbach, Javier Ayala – IBM MicroelectronicsPedro Herrera – KLA-Tencor Corporation

Wafers, Structures, and Models

Wafer samples

Engineering wafers spread across three lots were used in this work. The devices built on these wafers were intentionally nonstandard due to various engineering splits meant to push the process window beyond the edge of normal device func-tionality. Thus, these wafers had sufficient process variation to explore the correlations between structural variations and electrical performance.

StructuresBoth NFET and PFET 90nm node structures were measured in this work. By scatterometry standards, these two structures are quite complex and vary significantly from each other. The most significant features of these structures include a silicon-on-insulator (SOI) substrate with an implanted region, a gate poly that has been implanted at the top, and a nitride spacer on top of an oxide spacer. The PFET also contains a second oxide shape that is nestled on top of the L-shaped nitride spacer. This shape and the different implants to which each FET is subjected make these structures significantly different from each other. Sample XSEM images of the FETs are shown in Figure 1.

2.3 Scatterometry modelsThe scatterometry measurements were collected on a KLA-Tencor SpectraCD100 system. Correct modeling of the many different films comprising the structures was critical in obtaining good fits to measured spectra and “realistic” profiles.

Prediction analysis methodology was used with scatterometry to model complex NFET and PFET spacer structures.

Electrical measurements of gate resistance, Lpoly, and transistor current (Ion) correlated to inline scatterometry

measurements of the nitride spacer pulldown and the gate poly critical dimension, enabling the scatterometry

measurement to predict the electrical measurement with 3 sigma confidence limits.

Introduction

Scatterometry has long demonstrated its ability to accurately measure simpler structures, such as those found in the Shallow Trench Isolation (STI) and gate modules. However, IC manu-facturers now require the monitoring and control of increas-ingly sophisticated structures.

Spacers make up one category of complex structures that scatterometry is now addressing. They are important because of the influence they have on multiple device characteris-tics. Thus, measuring spacer structures inline can enable the prediction of device performance, which can lead to improved performance and yield. The work described in this paper dem-onstrates scatterometry’s ability to measure complex spacer structures, and use such measurements to predict electrical measurements. A methodology, called prediction analysis, is used to determine how well scatterometry measurements of certain parameters correlate to electrical measurements of gate resistance, gate Lpoly, and transistor current Ion. (Detailed information about prediction analysis can be found in the original SPIE publication of the same title in the Proceedings of SPIE 2007 Metrology, Inspection, and Process Control for Microlithography XXI Conference, Vol. 6518).

Because of its tight correlations, the scatterometry measure-ments can be used as a predictor of electrical performance sig-nificantly before the electrical test occurs. Thus, scatterometry can be a reliable measurement technique for improving spacer controls and reducing the mean time to detect (MTTD) some profile abnormalities.



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In particular, the effects from multiple implants and other processing had to be accounted for properly to ensure the ex-traction of accurate optical properties. Initial test models had more than 10 varied parameters, or degrees of freedom (DOF), for both the NFET and PFET structures. In the end, seven DOF for the NFET and eight DOF for the PFET were settled upon. The DOF common to both structures were the nitride pulldown from the top of the gate, the implanted gate poly height, the undoped gate poly height, the gate poly middle critical dimension (MCD), the nitride spacer width at the bot-tom, the implanted SOI thickness, and the SOI height. The PFET also had the same nitride spacer thickness as a DOF; this parameter did not apply to the NFET. Model schematics of the FETs, along with their DOF, are shown in Figure 2.

In order to alleviate concerns that complex models are unsta-ble, and therefore produce large precision values, short-term, dynamic precision data were collected. The sampling for the NFET consisted of five chips on one wafer, three dynamic cycles per chip, while the sampling for the PFET consisted of nine chips on one wafer, five dynamic cycles per chip. One of the nine chips from the PFET sampling produced “flyer” re-sults, meaning its measurements contained an unusually high amount of variation. Although this sampling was limited, it was adequate for this proof-of-concept experiment. A summary of the 3σ precision results for the critical DOF is presented in table 1. The PFET data are shown both with and without the flyer chip removed. Most of the 3σ precision values were less than 1nm; these results were quite good for such complex models, and indicated that the models were stable.

3σ Precision

NitridePulldown (nm)

NitrideWidth (nm)

NitrideThickness (nm)

Poly MCD(nm)

NFET 1.26 0.79 0.09

PFET (no flyers removed)

0.79 2.93 1.18 0.12

PFET (1 flyers removed)

0.35 0.23 0.44 0.10


Electrical measurements were collected at two points in the process. The first was called PS test, and was taken right after gate silicide formation. The second was called M1 test, and was taken right after the metallization of the first back-end line layer. All graphs showed wafer median data, and for each graph, the chips measured electrically and the chips measured with scatterometry were the same set of chips. No “flyers” from either set of measurements were removed from the analysis.

The electrical measurement error (Vy) was calculated using FMP analysis, but not TMU analysis, because the system consisted of multiple tools that were assumed to be a good ref-erence measurement system. The scatterometry measurement error (Vx) was calculated using the precision data presented in Table 1 (the PFET data containing the flyer was used).

Precision data were used because only one tool was used and because TMU analysis was not performed on the scatterometry data. Although it could have been estimated, the accuracy component was unknown and therefore rolled into Vother. Whether the accuracy component is estimated or rolled into Vother makes little difference on the primary metrics of TPE, CPE, and CPQ, because this difference is a second-order effect on these metrics. Since both system measurement errors were calculated using chip-level data, the errors had to be transformed into wafer-level data in order to be used for the prediction analysis because wafer medians were used. This transformation was approximated by dividing the variance form of the chip-level data by the number of measured chips per wafer.

PS test: gate resistanceAt PS test, gate resistance was found to correlate to the nitride spacer pulldown. Gate resistance was measured by the gate resistance parameters PCN_Rs for NFETs and PCP_Rs for PFETs. Note that the electrical measurements of gate resistance were performed on two different physical structures, so only the NFET pulldown was compared to the NFET gate resistance (PCN_Rs), and only the PFET pulldown was compared to the PFET gate resistance (PCP_Rs). This separation of NFET and PFET measure-ments was also true for the other comparisons in

Chrome (for decoration)

Implanted Poly

Oxide Spacer

Oxide

Gate Poly

Implanted SOI

SOI

Buried Oxide not shownx/y scale intentionally altered

x/y scale intentionally altered

NFET PFET

Nitride Spacer

Figure 1: XSEM images of the NFET and PFET spacer structures used in this work. The most significant features are labeled. Note that the chrome was added as part of the XSEM sample preparation, and was not present during the scatterometry or electrical measure-ments. The x/y scale was intentionally altered in these images.

Nitride Pulldown

Implanted Poly Height

Gate Poly Height

Gate Poly MCD

Nitride Spacer Width

Implanted SOI Thickness

SOI Height

x/y scale intentionally altered x/y scale intentionally altered

NFET PFET

Nitride Spacer Thickness

Figure 2: Schematics of the NFET and PFET scatterometry models used in this work. The varying parameters are shown (7 for the NFET, 8 for the PFET). The x/y scale was inten-tionally altered in these images.

Table 1: Short-term, dynamic 3σ precision data of NFET and PFET scatterometry models. Only the precision data from the critical varying parameters are shown. PFET data are shown both with and without the flyer that was observed.



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Metrology

the results section of this paper. The results are shown in Figure 3. Because nitride pulldown was defined as a negative number in the scatterometry model, note that the left side of each graph indicates more pulldown.

Both the x and y forms of TPE, CPE, and CPQ are shown below each graph, as well as the percent-age metrics, the number of data pairs, and the R2. Data show that the TPE { CPE; this means that the electrical measurement error is negligible. The TPE and CPE also indicate that the nitride pulldown can predict the gate resistance to within 0.68 ohm/square for the NFET, or 1.4 ohm/square for the PFET. The CPQ for the graphs ranged from about 3 to about 4; this corresponded to a data range that was sufficient to show a good correlation. Vother dominated the sources of error; this would probably still be true even if the accuracy component of Vx were determined and put back into Vx. The domination of Vother occurred in all of the correlations of this paper, so this observation will not be noted any more.

A physical explanation explains the experimental data: As the pulldown increases, more of the gate is exposed to future silicide formation (the oxide spacer is re-moved before silicide formation). When more silicide is formed, the gate resistance decreases because of the high conductivity of silicide.

M1 test: gate resistance

Gate resistance was also measured at M1 test and found to correlate to the nitride spacer pulldown, as shown in Figure 4. The electrical measurement error was negligible because TPE { CPE. The TPE and CPE indicated that the nitride pulldown could predict the gate resistance to within 0.73 ohm/square for the NFET, or 0.82 ohm/square for the PFET. The CPQ ranged from about 3 to about 4, again corresponding to a

more pulldown more pulldownPCP_

Rs (0

.5 o

hm/s

quar

ein

crem

ents

)

NFET Nitride PD vs. PSPCN_Rs (median of 15 chips)

nitride pulldown (10nm increments) nitride pulldown (5nm increments)

PFET Nitride PD vs. PSPCP_Rs (median of 15 chips)

TPEx5.3

CPEx5.3

CPQx3.2

TPEy1.4

CPEy1.4

CPQy2.9

%Vx0.15

%Vy0.06

%Vother99.80

data pairs13

R^20.64

PCN

_Rs

(0.5

ohm

/squ

are

incr

emen

ts)

%Vx0.04

%Vy0.25

%Vother99.71

data pairs13

R^20.76

TPEx16.5

CPEx16.5

CPQx3.5

TPEy0.68

CPEy0.68

CPQy3.9

Figure 3: Nitride pulldown vs. gate resistance (PCN_Rs and PCP_Rs) at PS test for the NFET (left) and PFET (right). Nitride pulldown is defined in the scatterometry model as a negative number, so more pulldown is indicated by a shift to the left.

more pulldown more pulldownPCP_

Rs (0

.5 o

hm/s

quar

ein

crem

ents

)

NFET Nitride PD vs. M1PCN_Rs (median of 23 chips)

nitride pulldown (10nm increments) nitride pulldown (5nm increments)

PFET Nitride PD vs. M1PCP_Rs (median of 23 chips)

TPEx3.6

CPEx3.6

CPQx4.2

TPEy0.82

CPEy0.82

CPQy4.0

%Vx0.21

%Vy0.11

%Vother99.68

data pairs16

R^20.79

PCN

_Rs

(0.5

ohm

/squ

are

incr

emen

ts)

%Vx0.01

%Vy0.14

%Vother99.85

data pairs16

R^20.64

TPEx22.2

CPEx22.2

CPQx2.7

TPEy0.73

CPEy0.73

CPQy3.2

Figure 4: Nitride pulldown vs. gate resistance (PCN_Rs and PCP_Rs) at M1 test for the NFET (left) and PFET (right). Nitride pulldown is defined in the scatterometry model as a negative number, so more pulldown is indicated by a shift to the left.

PCP_

Rs (0

.5 o

hm/s

quar

ein

crem

ents

)

NFET Poly MCD vs. M1PCN_Rs (median of 23 chips)

Poly MCD (1nm increments) Poly MCD (1nm increments)

PFET Poly MCD vs. M1PCP_Rs (median of 23 chips)

TPEx2.6

CPEx2.6

CPQx1.9

TPEy1.3

CPEy1.3

CPQy2.4

%Vx0.01

%Vy0.04

%Vother99.95

data pairs16

R^20.40

PCN

_Rs

(0.5

ohm

/squ

are

incr

emen

ts)

%Vx0.01

%Vy0.10

%Vother99.90

data pairs16

R^20.49

TPEx2.0

CPEx2.0

CPQx2.0

TPEy0.88

CPEy0.88

CPQy2.7

Figure 5: Gate poly Middle CD vs. gate resistance (PCN_Rs and PCP_Rs) at M1 test for the NFET (left) and PFET (right).



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Metrology

data range that was sufficient to show a good, but not excell-ent, correlation. The physical explanation for this correlation was identical to the one where the gate resistance was mea-sured at PS test.

Figure 5 compares the gate resistance measured at M1 test to the poly MCD. Once again, TPE { CPE, and both metrics indicated that the poly MCD could predict the gate resis-tance to within 0.88 ohm/square for the NFET, or 1.3 ohm/square for the PFET. The CPQ (~2–3) was a bit lower than for the nitride pulldown comparisons, indicating that the data range was sufficient to show only some level of correlation. A physical explanation explains these correlations well: a larger gate CD exposes more surface area on top of the gate to future silicide formation, which results in a lower gate resistance.

M1 test: Lpoly

Lpoly is a capacitance-based electrical measurement of gate length at M1 test, and was found to correlate to the gate poly MCD scatterometry measurement (Fig-ure 6). The CPE was found to be slightly smaller than the TPE, so the electrical measurement error was small but had a noticeable effect on the total error. The poly MCD measurement was capable of predicting the Lpoly measure-ment to within ~1.5nm for both the NFET and the PFET. The CPQ for the NFET was ~2–3, meaning that the data range was sufficient to show some amount of correlation, while the CPQ for the PFET was ~5, meaning that that data range was sufficient to

show a good correlation. Knowledge of the Lpoly measurement2 reveals that it is a good measure of the physical gate length, and therefore should (and in fact does) correlate to the scat-terometry poly MCD measurement.

M1 test: transistor current

Figure 7 shows that the transistor current through the NFET (nIon) at M1 test correlated to the nitride pulldown measure-ment. Once again, the CPE was found to be only slightly smaller than the TPE. The nitride pulldown measurement predicted the NFET transistor current to within ~40 µA/µm, while the CPQ values of ~2–3 indicated that the data range was sufficient to show some correlation. As in the previous cases, the experimental data can be explained physically: more nitride pulldown is due to more spacer overetch, which also results in more oxide loss on top of the implanted SOI layer. Since this oxide layer reduces outdiffusion of the source-drain dopant, a thinner oxide results in more outdiffusion of the dopant. Less dopant in the source-drain reduces its conduc-tivity, causing less current flow (nIon) through the NFET source-drain. Due to dopant differences in the PFET, a similar correlation was not seen between pIon and the PFET nitride pulldown.

Conclusions

Prediction analysis methodology was used to predict one measurement (called the dependent variable) based upon other measurements (called the independent variable) such that the error of the predicted measurement is bounded.

Scatterometry was successfully used to model complex NFET and PFET spacer structures. The scatterometry measurements were collected from nonstandard engineering wafers that were purposefully altered to expand the device performance beyond the normal process window in order to explore the relations between structural variations and electrical parameters. Elec-trical measurements of gate resistance, Lpoly, and transistor

more pulldown

NFET Nitride PD vs. M1 nlon(median of 8 chips)

nitride pulldown (10nm increments)

nl o

n (2

5µA

/ µm

incr

emen

ts)

%Vx0.03

%Vy0.79

%Vother99.19

data pairs10

R^20.51

TPEx26.7

CPEx26.6

CPQx2.0

TPEy39.9

CPEy39.7

CPQy2.7


pLpo

ly (1

nm in

crem

ents

)

NFET Poly MCD vs. M1 nLpoly (median of 15 chips)

Poly MCD (0.5nm increments) Poly MCD (0.5nm increments)

PFET Poly MCD vs. M1 pLpoly (median of 15 chips)

TPEx0.92

CPEx0.90

CPQx5.1

TPEy1.54

CPEy1.50

CPQy5.5

%Vx0.12

%Vy4.78

%Vother95.10

data pairs13

R^20.87

nLpo

ly (1

nm in

crem

ents

)

%Vx0.03

%Vy5.35

%Vother94.63

data pairs13

R^20.59

TPEx1.4

CPEx1.3

CPQx2.3

TPEy1.5

CPEy1.4

CPQy3.1




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current (Ion) correlated to inline scatterometry measurements of the nitride spacer pulldown and the gate poly MCD. In each case, the scatterometry measurement can be used as a predic-tor of the electrical measurement, with associated 3 sigma confidence limits. The ability to predict device performance by measuring spacers inline can lead to improved device perfor-mance and yield.

This work demonstrates that electrical measurements can be a suitable method to verify the quality of scatterometry mea-surements of complex structures. Because of these features, the use of electrical measurements will become more common as a verification of inline metrology of those complex structural parameters where no appropriate high-throughput reference measurement system is available.

Acknowledgements

This paper is based on the original SPIE publication of the same title, which can be found in the Proceedings of SPIE 2007 Metrology, Inspection, and Process Control for Microlithography XXI Confer-ence, Vol. 6518.

The authors would like to thank Chas Archie of IBM for providing clear insight and advice in the development of prediction analysis, Blaze Messer of IBM for collecting and analyzing much of the data, Ron Fiege and Clem Bottini of IBM for collecting spectra, and Ben Himmel of IBM for providing the electrical tester tool matching data. Finally, we thank Jesus Rivas of KLA-Tencor for assisting with the extraction of film optical constants.

References

1. M. Sendelbach and C. Archie, “Scatterometry measurement preci-sion and accuracy below 70nm,” Metrology, Inspection, and Process Control for Microlithography XVII, Daniel J. Herr, Editor, Proceed-ings of SPIE, Vol. 5038, pp. 224–238, 2003.

2. M. Sendelbach, C. Archie, B. Banke, J. Mayer, H. Nii, P. Herrera, and M. Hankinson, “Correlating scatterometry to CD-SEM and electrical gate measurements at the 90nm node using TMU analysis,” Metrology, Inspection, and Process Control for Microlithography XVIII, Richard M. Silver, Editor, Proceedings of SPIE, Vol. 5375, pp. 550–563, 2004.

3. M. Sendelbach, A. Munoz, K. Bandy, D. Prager, and M. Funk, “Integrated scatterometry in high volume manufacturing for polysili-con gate etch control,” in Metrology, Inspection, and Process Control for Microlithography XX, Chas N. Archie, Editor, Proceedings of SPIE Vol. 6152 (SPIE, Bellingham, WA, 2006), Article 61520F.

4. E. Solecky, C. Archie, and B. Banke, “New Comprehensive Metrics and Methodology for Metrology Tool Fleet Matching,” in Metrology, Inspection, and Process Control for Microlithography XIX, Richard M. Silver, Editor, Proceedings of SPIE Vol. 5752 (SPIE, Bellingham, WA, 2005), pp. 248–258.



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