CURRICULUM VITAE

S.SREENATH KASHYAP E-Mail: Kashyap.foru3@gmail.com Mobile: +919000605634

I. PERSONAL PROFILE

Name : S.Sreenath Kashyap

Father’s Name : Siddhavattam Rama Krishna

Date of Birth : 05-11-1989

Nationality : Indian

Permanent Address : 39-349/4, Om Shanti Nagar,

Kadapa-516001, Andhra Pradesh.

Correspondence Address : S.Sreenath Kashyap

39-349/4, Om Shanti Nagar

Kadapa-516001, Andhra Pradesh.

Qualifications : M.Tech in VLSI

Research publications : Published: 01 Paper in National Conference.

Accepted: 01 Paper in International Conference

Seminars attended : 03 (National)

Workshops attended : 03 (National)

Computer knowledge : MS Office, C Programming.

Technical proficiency : VHDL, VERILOG, LIBRO, XILINX

II. ACADEMIC PROFILE

Degree/ Course Institution University / Board Year of Passing

% of Marks

*M.Tech (VLSI Design)

SRM UNIVERSITY. SRM UNIVERSITY. 2012 6.8(CGPA)

B.Tech (ECE)

MALLA REDDY ENGINEERING

COLLEGE HYDERABAD.

JNTU, HYDERABAD. 2010 59.14(%)

INTERMEDIATEVIGNAN JUNIOR

COLLEGE, GUNTUR.BOARD OF

INTERMEDIATE. 2006 79.40(%)

SSCNEW HORIZON

ENGLISH MEDIUM HIGHSCHOOL,KADAPA

BOARD OF SECONDARY EDUCATION

2004 73.66(%)

III. STRENGTHS

Positive Attitude. Ability to Work Alone as well as in Group. Hard working Ability to Learn quickly Adaptability

IV. RESEARCH EXPERTISE

#1.Title of the project : “COMMUNICTION IN MULTIPROCESSOR SYSTEM

USING CO-PROCESSOR AND IMPLEMENTATION ON FPGA”

Supervisor : Mrs.Indra Priyadarshini, Associate Professor in ECE,

Malla Reddy Engineering college, Hyderabad.

Outcome of the Project Work.

The main objective is to design a co-processor to make the communication faster and

efficient in a multi-processor system.

Co-processor is a block through which all the processors are connected and the data

between them is being exchanged through it .

The main block is router block through which data is distributed

The data is distributed in the form of FLITS.

The implementation is done in FPGA Using VHDL language and Verification is done in

XILINX

#2.Title of the project : “HOME SECURITY SYSTEM USING PASSWORD”

Supervisor : Mrs.C.Shilpa, Associate Professor ECE,

Malla Reddy Engineering College, Hyderabad.

Outcome of the Project Work.

The main objective is to design a security system which will detect the motion of the body

from the sensor and make the doors open when the security key is correct.

If the secret code is incorrect even if the person tries to enter the passage then the sensor

detect the moment and alarm is turned on stating that the un-authorized entry is being

done.

#3.Title of the Project : “DESIGN AND CHARACTERISATION OF PARALLEL

ADDERS”

Supervisor : Mrs.N.Saraswathi, Assistant Professor (S.G)

Department of ECE,

SRM University, Chennai.

Outcome of the Project Work.

The main objective of the project is to design the low power high speed adders such that

they are implemented in some DSP application.

The parallel prefix adders namely Kogge stone, Sparse kogge stone, Spanning CLA are

designed and implemented in FFT.

Initially they are designed for 16 bit later extended till 256 bit widths

The Power, Delay measurements are done in LIBRO, compared them with ripple carry

adder.

Finally the Adder Module in FFT is being replaced by the lower power consuming Adder.

VI. RESEARCH PUBLICATIONS

National Conference -01 (Published).International Conference – 01 (Accepted)

V. Project Experience:

1. Worked as a PROJECT TRAINEE at CMC Limited –A division of TATA enterprise, Hyderabad. (1st June 2009– 30th June, 2009).

2. Worked as STUDENT INTERN at Vedic School Of VLSI design – A training Division Of SIMPLI5ING Semiconductors, Hyderabad (4th Feb, 2010 to 19th April 2010).

VI . SEMINARS PARTICIPATED

National seminars

1. Participated in the National Conference on Emerging Trends in Electronics and Communication Technologies, NCECT ‘12 on March 28 th 2012 at Jawaharlal Nehru Technological University, Anantapur.

2. Participated in National Level Technical Fest AKSHARA 2K12 on 16-17 th March 2012 Conducted by IEEE Hyderabad Section at Malla Reddy Engineering College Hyderabad

3. Participated in the IEEE Student congress Held during August 09-10 th, 2008 at MEKASTAR Auditorium, IETE, OU Campus, Hyderabad.

Training Programmes / National workshop

1. National workshop on ANALOG VLSI DESIGN Conducted by Department of ECE SRM University Chennai in Association with CADENCE DESIGN SYSTEMS anf ni2 DESIGNS on 20 th March, 2009.

2. National workshop on MEMS Conducted by Department of ECE VNR vignana jyothi engineering College Hyderabad on 4-5th March, 2009.

3. National Workshop on VLSI semicustom Design with FPGA’S conducted by Department of ECE, CM engineering college Hyderabad. 22-23rd, August 2008.

RESEARCH PUBLICATIONS

National Conference

S.SREENATH KASHYAP (2012) High throughput VLSI Architecture for FFT computation Proceeding of National Conference on Emerging Trends in Electronics & Communication Technologies Department of ECE JNTUCEA,28 th March 2012 pp: 64-70.

Extracurricular activities

Participated in national level taekwondo championship in Lucknow,August 16-18,1998 Participated in national level taekwondo championship in Bhopal Won gold medal in state taekwondo championship on 2-8-1998 conducted by

A.P.Olympic association and Sports authority of Andhra Pradesh Gold medal in A.P. State taekwondo championship held on 14th November, 1999

References:

Dr.S.MALARVIZHI, Prof S.V.Jagadish ChandraHEAD OF THE DEPARTMENT Scientific InvestigatorDepartment of ECE Department of Materials Science, CENIMAT,SRM University Center for Materials Research, I3N Institute forKattankulathur Nanostructures, Nanofabrication &Nanomodelling,Chennai-603203 FCT-UNL, Campus de Caparica, 2829-516

Caparica, PORTUGAL. Mobile: 00351-939716389

Declaration : I here by declare that the above information is authentic to the best of my knowledge.

SREENATH KASHYAP.S