Stackiabatic: Novel Concept for Reducing the Power ...iasir.net/AIJRSTEMpapers/AIJRSTEM16-239.pdf · former is generated due to direct current bias, as in case TTL (Transistor–transistor–logic)

ISSN (Print): 2328-3491, ISSN (Online): 2328-3580, ISSN (CD-ROM): 2328-3629

American International Journal of Research in Science, Technology, Engineering & Mathematics

AIJRSTEM 16-239; © 2016, AIJRSTEM All Rights Reserved Page 125

Available online at http://www.iasir.net

AIJRSTEM is a refereed, indexed, peer-reviewed, multidisciplinary and open access journal published by International Association of Scientific Innovation and Research (IASIR), USA

(An Association Unifying the Sciences, Engineering, and Applied Research)

Stackiabatic: Novel Concept for Reducing the Power Consumption and

Practical Implementation Using NOT & NAND Gates Kapil Mangla, Prof. (Dr.) Anil Kumar

Al-falah School of Engineering & Technology,

Dhauj, Faridabad, Haryana, INDIA.

I. INTRODUCTION Industry over last few decades has seen a tremendous growth in the electronics segments. Market is flooded

with highly sophisticated and technically advanced gadgets. The advances in electronics industry because of

technically advanced ICs (Integrated Circuits) and increase transistor switching speed has resulted in many fold

performance improvement in computer systems. On the hind side, there has been increased consumption of

power to bring this change. A community of scientists / researchers has thus being trying to reduce this

dissipation by improving the circuit design. High performance systems cause high energy consumption, needs

better cooling technology, requires expensive packaging, decrease system reliability and on top of all-increase

the cost of system.

Power depends on the way circuit is designed however it can be divided into static and dynamic power. The

former is generated due to direct current bias, as in case TTL (Transistor–transistor–logic) and ECL (emitter–

coupled– logic) and NMOS (N-type MOS) or due to leakage current. Except for push – pull type logic family

such as CMOS, static power tends to dominate. Because of this CMOS is considered to be most suitable circuit

style for VLSI (very large scale integrated circuit). The driving force behind very large scale integration circuits

(VLSI) for high performance computing related to science and technology has been digital CMOS integrated

circuits. It is speculated that the demand for digital CMOS IC’s will keep increasing because of its important

feature improvement in processing technology, reliable performance and low power.

A major concern has been the dynamic power requirement of the CMOS in large computer and personal

information systems. In this Work, power consumption depends upon the width and length ratio is presented. If

we change the width and length of the device then it’s current and gate capacitance changes. In this work there

is 180nm technology has been used. So that the length is fixed but there is a change in the width. The result is

depends upon different width and length ratio. Current will increase if the width of transistor increases and gate

capacitance also increases if the width of transistor increase and vice versa. The power consumption also

depends upon the current in the circuit and current depends upon the width and length ration.

II. OVERVIEW OF POWER DISSIPATION

As we all know that CMOS work in three regions: Cut-off region, saturated region and non saturated region. So

the current is different in different regions.

In cut-off region:

In linear / non-saturated / active region:

Abstract: For many years, designing of high speed low power circuits with CMOS technology was a difficult

challenge for research community. There are various levels at which design problem related to low power

and increased demand can be addressed; these levels are - software level, architecture level, algorithm

level, circuit level and process technology level. The objective of this paper is to put forth different

approaches that reduce the consumption of power of any random combinational logic by applying

minimization techniques at circuit level. In this paper we have designed NAND & NOT gate using

stackiabatic technique and compared with conventional, adiabatic & stacking techniques. The objective of

this paper is to put different approaches that reduce the consumption of power

Keywords: CMOS Circuit, VLSI, Combinational Circuits, Tanner EDA, Power.

http://www.iasir.net/

Kapil et al., American International Journal of Research in Science, Technology, Engineering & Mathematics, 15(2), June-August, 2016,

pp. 125-132


In Saturation Region:

Because of nearly zero power dissipation static CMOS gates are very power efficient while operating in static

state. Power was the secondary consideration behind speed and area. As transistor counts and clock frequencies

have increased, power consumption has skyrocketed and now is a primary design constraint.

The instantaneous power P(t) drawn from the power supply is proportional to the supply current iDD(t) and the

supply voltage VDD.

III. POWER REDUCTION DUE TO STACKING TECHNIQUE

Stack approach is one way of reducing power leakage which forces a stack effect by breaking down an existing

transistor into two half size transistors. Structure is shown in fig.1. Reverse bias is induced between two

transistors when they are turned off together resulting in sub threshold leakage current reduction. Delay is

increase significantly by dividing transistors which could limit usefulness of the method.

FIG. 1 CMOS CIRCUIT USING STACKING APPROACH

IV. POWER REDUCTION DUE TO ADIABATIC TECHNIQUE

Adiabatic is a term which is often used in thermodynamics to describe a process where there is no exchange of

heat between environment and surrounding. Similarly adiabatic technique for reducing power implies no loss of

heat in the circuit. The signal energies stored in the circuit capacitances are recycled instead of being dissipated

as heat. The adiabatic logic is also known as energy recovery CMOS. There is a conservation of circuit energy

with adiabatic switching approach. Hence this can be useful method to reduce power dissipation of digital

system. Adiabatic switching principle is one of the best Power reduction techniques having many advantages

over other techniques like simple to design, no complexity increases, and great reduction in power dissipation.

Basically adiabatic switching principle states that during the transition from logic 0 to logic 1 we need the power

supply but transition from logic 1 to logic 0 we don’t need the power supply. If at that time we make the power

supply off we can save the power dissipation because power dissipation is directly proportional to the supply

voltage.

This can be done by changing the voltage source either by sinusoidal voltage source or by Pulse and adjusting

the supply voltage in such a way that during the transition from logic 1 to logic 0 the supply voltage comes into


pp. 125-132


off state and in this way the power dissipation is reduced up to much extent because as told earlier the power

dissipation is directly proportional to supply voltage.

V. POWER REDUCTION DUE TO STACKIABATIC TECHNIQUE

Stacking is a new approach for reducing the power consumption in digital CMOS circuits. Stackiabatic is a

novel concept and has practical implementation. It commences with the thought that led to the development of

this technology. The derivation of the term “Stackiabatic” is from a concatenation and shorting of stacking and

adiabatic techniques. In stacking, we break the existing transistor into two half size transistors. This result is to

reduce the threshold leakage by turning off the two transistors when reverse biasing is induced between them. In

CMOS circuits we need power supply when transistors come from 0 to 1and we don’t need power supply when

transistors come from 1 to 0. In that case we make the power supply off and have power dissipation. It is done

by using any sinusoidal, pulse and adjusting power supply. So in stackiabatic we reduce the power dissipation

by threshold leakage and discharge of capacitor.

VI. PROPOSED WORK

Logic gates are elementary (fundamental) building block of a digital circuit. Generally most of the logic gates

have two inputs and one output. It implements Boolean function which implies that it performs logical operation

on one or more inputs and gives single logical output. Types of logic gate are AND, OR, NOT, NOR, NAND,

XOR, XNOR. The objective of this paper is to study the implementation of stackiabatic technique on NOT Gate

/ Inverter and NAND Gate

A. NOT Gate / Inverter

Operation: When Vin is high, in this case PMOS is off and NMOS is ON. There is a study state potential on low

because there is a direct path between ground node and Vout. When Vin is low, in this case PMOS is ON and

NMOS is off. There is a study state potential on high because a path exists between Vout & VDD. The gate

clearly functions as an inverter.

B. NAND Gate

Operation: When A is low and B is also low, in this case both NMOS transistors are off and PMOS transistors

are on. Hence Vout is directly connected to VDD. So that output is high. When A is high and B is LOW, in this

case right PMOS is on & left PMOS is off and upper NMOS is on & lower NMOS is off. Hence ground does

not connect to the output and VDD connected to output. So that output is high. When A is low and B is high, in

this case right PMOS is off & left PMOS is on and upper NMOS is off & lower NMOS is on. Hence ground

does not connect to the output and Vout connected to VDD. So that output is high. When A is high and B is also

high, in this case both NMOS transistors are on and PMOS transistors are off. Hence Vout is directly connected

to VDD. So that output is low.

VII. SIMULATION AND WAVEFORM

NAND & NOT gate simulated circuits using conventional, adiabatic, stacking and stackiabatic techniques.

Fig. 2 Conventional CMOS Inverter

Fig. 3 Waveform for Voltage of Conventional

CMOS Inverter

Fig.4 Waveform for Power of Conventional CMOS

Inverter


pp. 125-132


Fig. 5 Stacking CMOS Inverter

Fig. 6 Waveform for Voltage of Stacking CMOS

Inverter

Fig.7 Waveform for Power of Stacking CMOS

Inverter

Fig. 8 Adiabatic CMOS Inverter

Fig. 9 Waveform for Voltage of Adiabatic CMOS

Inverter

Fig. 10 Waveform for Power of Adiabatic CMOS

Inverter

Fig. 11 Stackiabatic CMOS Inverter

Fig. 12 Waveform for Voltage of Stackiabatic

CMOS Inverter


pp. 125-132


Fig.13 Waveform for Power of Stackiabatic CMOS

Inverter

Fig.14 Conventional CMOS NAND Gate

Fig.15 Waveform for Voltage of Conventional

NAND Gate

Fig.16 Waveform for Power of Conventional

CMOS Inverter

Fig.17 Stacking CMOS NAND Gate

Fig.18 Waveform for Voltage of Stacking NAND

Gate

Fig.19 Waveform for Power of Stacking CMOS

Inverter

Fig.20 Adiabatic CMOS NAND Gate


pp. 125-132


Fig.21 Waveform for Voltage of Adiabatic NAND

Gate

Fig.22 Waveform for Power of Adiabatic CMOS

Inverter

Fig.23 Stackiabatic CMOS NAND Gate

Fig.24 Waveform for Voltage of Stackiabatic

NAND Gate

Fig.25 Waveform for Power of Stackiabatic CMOS

Inverter

VIII. RESULT ANALYSIS

The Simulation of logic gates with and without low power techniques is carried out at 180nm, technology.

CMOS technology parameters are taken for NMOS and PMOS transistors, using Tanner tool. Transient

Analysis is done to get Delay and Average Power results.

TABLE 1 CMOS NOT GATE RESULT

POWER REDUCTION

TECHNIQUE

AVERAGE

POWER

CONSUMPTION (In Microwatt)

AVERAGE

DELAY

(In Nano Second)

Conventional 0.8384 0.1496

Adiabatic 0.1084 98.061

Stacking 0.4603 0.8251

Stackiabatic 0.0692 98.203

TABLE 2 CMOS NAND GATE RESULT

POWER

REDUCTION

TECHNIQUE

AVERAGE POWER

CONSUMPTION

(In Microwatt)

AVERAGE DELAY (In Nano Second)

Conventional 1.5270 24.721

Adiabatic 0.2731 23.554

Stacking 0.8842 24.619

Stackiabatic 0.1920 23.967


pp. 125-132


Fig.26 Comparison of Average power for NOT

Gate using different Techniques

Fig. 27 Comparison of Average Delay for NOT


Fig. 28 Comparison of Average power for NAND


Fig. 29 Comparison of Average Delay for NAND


IX. CONCLUSION Comparison has been done for NAND & NOT gate, delay and power is calculated for Different Techniques.

Designed the NAND & NOT using Conventional, Adiabatic, Stacking & Stackiabatic Techniques and

implemented these techniques for power reduction then we can observe the minimum power consumed in

Stackiabatic Technique. The tool for simulation is TANNER. At 180 nm technology and the practical

observations have been tabled.

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[3] N Whein and M Munch “Minimum power consumption in digital circuits and systems”, university of Kaisersloutern, Germany.

[4] Krashna Nand Mishra”Efficient Carry Generation technique Incorporating Energy Recovering Logic Circuitry For Low Power

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Stackiabatic: Novel Concept for Reducing the Power ...iasir.net/AIJRSTEMpapers/AIJRSTEM16-239.pdf · former is generated due to direct current bias, as in case TTL (Transistor–transistor–logic)