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[email protected]
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To start the Xilinx ISE Project Manager, simply open the Xilinx
folder and then double click theXilinx ISE 9.2iicon as illustrated
below.
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NEXTYou will find a window Tip of the DayClick on OK button
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This will present you with the following windows:
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For this lab, we wish to create a new project, so selectFile
-> New Project. This will bring up the following window:
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And then click on Next Give the Project Name
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Set the parameters as the following.Then click Next on the
coming dialog boxes and finally click Finish.
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Click on Next
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Click on Next
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Click on Finish
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Once, you click theFinishbutton, the following ISE Project
Manager Window will appear:Select Behavioral Simulation
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First Right Click on the deviceNext Select New Source
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Give file nameClick on Next Select VHDL Module
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And then click on Next First give Input ,Output ports
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Click on finish
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First write the codeNext SAVE
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For Test Bench WaveformFirst Right Click on the filenameNext
Select New Source
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then click NEXT on the coming dialog boxes and finally click
Finish.Give the file name for test bench andSelect Test Bench
Waveform
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Click on Next
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Click on Finish
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Disable GSR OptionNext Click on Finish
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Set the input values and then SAVE ,you will find this test
bench file
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NEXT for SimulationClick on Xilinx ISE Simulator-Simulate
Behavioral Model
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For Synthesis Select this option
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For RTL Schematic Select this optionBy Double clicking on this
we get the internal circuit
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This is internal circuit
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For Synthesis Report Select this option
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For Design Summary Select this option
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Programming the FPGAAfter pin assignment, we generate
configuration data to program the FPGA.InSourceswindow, select the
main file of your project (count_mem_verilog.v or
count_mem_vhdl.vhd) and then inProcesseswindow, right click
onGenerate Programming Fileand selectStartup Options.SetFPGA
Start-UpClocktoJTAG
Clock.ClickOK.http://www.ece.uvic.ca/~ceng450l/lab/lab1p1.html
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Turn on the board.Double click onConfigure Device
(iMPACT)inProcesseswindow.
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ClickFinish.Choosecount_mem.bit, clickOpen.Right click
onXilinxicon, selectProgram, clickOK.
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If the FPGA is programmed correctly you should see the following
window.
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Test your design
The clock signal is a 3-Hz, 0-3.3 V square wave generated by
function generator. Check the voltage level of clock signal on the
oscilloscope to make sure that the clock pulse is correct. Wrong
clock signal may damage the board.Resetandensignals are connected
to BTN1 and SW1, respectively.Only for VHDL Users
Some VHDL statements are not synthesizable. This subset of VHDL
can not be converted to hardware and is used only in behavioral
simulation. Here is a non-synthesizable version of counter:
"Counter.vhd". Download it and run the behavioral simulation. Then,
try to synthesis the Count_Mem_VHDL again with the new counter.
Explain the error reported by ISE.
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[email protected]
