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January 2004 1 © 2004 Actel Corporation Static Timing Analysis Using Designer's Timer 1 Introduction Static timing analysis is an important step in analyzing the performance of a design. Timer is Actel's static timing analysis tool incorporated in Designer software. Timer allows both pre-layout and post-layout static timing analysis and constraints setting. Generally, static timing analysis is much faster than timing-driven gate-level simulation and does not require stimulus vector generation. Therefore, unlike dynamic analysis, the quality of the static approach is independent of the quality of stimulus vectors. However, proper functionality of the design cannot be checked in static analysis. An accurate and efficient static timing analysis has many benefits, such as providing quick and efficient information to enhance the design performance and easing the design debugging procedure. This application note presents the most important concepts and techniques of static timing analysis and contains practical examples. Background Actel's Designer software includes the static timing analysis tool called Timer. The timing information is accessible after compiling the design netlist in Actel’s Designer software. However, the final and accurate timing information will be available after place-and-route. Detailed information on Timer is available in the Timer User’s Guide. The Designer software release notes contain Timer updates and are located on Actel's website. This section presents the main features of Timer and their functionality. Fi gure 1 represents the main (or summary) window of Timer. In the Summary section, Timer reports maximum clock frequency, input to register delay, register to output delay , and input t o output port delay for best, worst, and typical cases based on the user preference. 1. The co ntents are ba sed on the Designer release R1-20 02 Serv ice p ack 2. Fi gure 1 Timer Summary GUI Application Note AC196

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