Status of Tilecal upgrade activities at LPC

ATLAS/LPC weekly meeting27 June 2013

François VazeilleRoméo Bonnefoy (Technical coordinator)

· Summary of the LHC and ATLAS plans· Summary of the Tilecal upgrade· LPC activities

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Summary of the LHC and ATLAS plans

Phase 0

Phase I

Phase II

5 (Peak) x 2 (Leveling) = 10 Integrated nominal Luminosity > 3 000 fb-1

= HL-LHC

LHC planning

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ATLAS Phase I

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ATLAS Phase II

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ATLAS/LPC deeply commited

Summary of the Tilecal upgrade

Phase 0 : Laser II, Crack + MBTS Phase I : Gap/Crack Phase II : Electronics FE and BE + Gap/Crack

¨Making of a Demonstrator of the electronics for both FE and BE - Validated at the surface (Building 175) then in the ATLAS test beam. - Inserted in ATLAS in Phases 0 and I. Final design.

Series production (during Phase I) then insertion (LS3).

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2012

2013

2014

2015

2016

2017

2018

2019

2020

2021

2022

Insertion of1st Demonstrator

Insertion of3 additional

Demonstrators

Possibility ofmodifying or adding

Demonstrators

Drawer productionStart

Insertion of production Drawers

Stockholm upgrade meeting June 3, 2013

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LPC activities· Started in 2008 EoI, then LoI (Phase I ) and LoI (Phase II).

Reported in the ATLAS/LPC web site- Presentation of R&D studies http://atlas-clermont.web.cern.ch/atlas-clermont/satlas.html

- LPC Documents (Talks, meeting reports, etc.)https://indico.in2p3.fr/categoryDisplay.py?categId=219

· 6 LPC activities - Laser II - MobiDICK

- Mini-Drawers - High Voltages - PMT Dividers - VFE and FE electronics (Tilecal Option 2)

Reported today

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Mini-Drawers

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Girder ring

Drawer

Alignment from outside

Alignment recovery of PMTs/cells

Drawers holding VFE and FE electronics: - long (1.40 m) and heavy (42 kg) objects (512 Drawers), - associated in pairs of Super-Drawers (256 Super-Drawers), - electronically inter-dependent within a Super-Drawer.

Present ATLAS scheme

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Drawer

The Slider is ″supported″in the rear part of Girder rings

Adjustable contacts

Adjustable contacts

Finger

Slider Basket

· sATLAS scheme

- Easier handling.- Easiest access in a restricted space.- Electronically independent.

Mini-Drawers (half Drawer long).

Alignment recovery

Alignment from inside10

Slider 2

Basket 1

Insertion of a Mini-Drawer inside a Basket,

then in the Slider,then in a LB Module.

Mini-Drawers

Building 17520 June 2013

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Validation of the Mini-Drawer concept from tests at CERN, in various Tilecal module positions (0°, 45°, 90°) in agreement with theoretical calculations. [Tilecal week, 7 October 2011] + last tests at CERN June 20-21

Validation of the Slider concept from tests at CERN, using 3 Tilecal modules at 90° [Tilecal week, 28 September 2012]

+ last tests at CERN June 20-21

Tests at 45°

Slider 2

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Validation of the whole system: LB Module + Finger + Slider + Basket + 4 Mini-Drawers

last tests at CERN June 20-21

95 cm

Possible working in a restricted space13

· Next steps¨ Sharing of the mechanics activities

- Mini-Drawer bodies: Bucharest. - Mechanical links, cooling…: Barcelona.

- Handling tools: Clermont-Ferrand.

¨ Clermont-Ferrand works improvements of the present Mini-Drawers and tools Demonstrator Option 1 “Chicago-Stockholm” tested in September.

- Improved Mini-Drawers. - Slider version 3. - Basket Version 2.

+ latter studies (Special long Basket, Patch Panel…)

See yesterday Mechanics meeting https://indico.in2p3.fr/conferenceDisplay.py?confId=8593

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Supervised by LPC

High Voltages

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Summary of previous progresses

Several options reported by LPC since a long time HV regulation inside/outside Drawers

[Tilecal meetings: February 2008, November 2009, September 2012]

- Re-cycling of HV cards inside a special crate put in the electronics room. - Design of HV bus cards sharing the individual HV’s (with noise killers). - Use of multiconductor cables to supply the HV bus cards.

Clermont-Fd proposition to develop an outside option but ready to provide all the information on the present ATLAS inside option. to Argonne and Lisbon.

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Present status

HV Bus boardsready to equip 3 trains of Mini-Drawers

A cable tray will run3 different cable lengths

towards Drawers 2, 3 and 4(Fixation holes made here)

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Regulationcrate

HVSource Operational DCS

Various cable lengths

- 1 m long.- 4 times 20 m long (175)- 100 m long, to reproduce ATLAS.

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Tests in progress and planning

Clermont-Ferrand tests HV tests in progress, with a PMT Block lighted by a blue LED Noise measurements for different cable lengths: going on.

- Next steps in 175 HV tests by LPC, once the Clermont-Fd tests will be fully efficient. Equipment of Demonstrator 1 “Chicago-Stockholm” by September .

- Made the last week in the building 175 Mini-Drawer handling/connection tests Insertion of the crate in a rack of the electronics room

CERN tests

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PMT Dividers

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Summary of previous progresses

Passive Dividers

Active Dividers

Goal: To keep the Tilecal performances (Linearity, energy resolution) for the measurement of very high energies at the highest luminosities.

Proposed solution: Replacement of present “Passive Dividers” by “Active Dividers” keeping stable the voltage repartition in between every stage Use of active components (Transistors and diodes) in the last 3 stages, in order to balance the current stream induced by Minimum Bias events.

Preliminary results previously shown [Tilecal meeting, 17 June 2011].

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Main results given in the Tilecal Note(The Note ATL-COM-TILECAL-2013-014 is not yet approved)

¨ Pure electronics tests using the upgraded Divider Test Bench Interdynode voltage comparisons without/with injected currents of 10 Passive and 20 Active Dividers. Protocol for the certifications of productions.

¨ Full tests of Dividers behind PMTs Comparisons for a given AC light (Signal) of 20 sets ″PMT-Passive Divider-Active Divider″ in function of the injected DC light (Minimum Bias).

No other BE electronicsthan a scope

Test Bench of batch of 10 Dividers

Passive Active

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Summary of results

- The Passive Dividers fit the ATLAS specifications for Tilecal PMTs, but not fully for Crack scintillators (and so MBTS).

- The Active Dividers fit the sATLAS specifications for both Tilecal and Crack scintillators (and MBTs), within a wide range going well above the expected Luminosities. The linearity (and the energy resolution) will be improved /ATLAS. They could equip all the PMTs.- The Divider Test bench has been upgraded and can welcome Passive/Active Dividers.

- A batch of 350 Active Dividers has been produced for the Crack/MBTS scintillators and the tests are in progress.

You are invited to make a short visit of the test system !

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Last tests to do: radiation tests (Gammas, neutrons)

- 20 Dividers: whole last 3 stages + resistors simulating the other ones.- 16 Transistors alone + 8 Diodes alone (with direct/inverted polarities).- Everything supplied at the right HV and on-line monitored.

Last 3 stagesTransistors

DiodesResistors

PCB to be irradiated

Special PCB to irradiate: active components within a square 7x7 cm2.

Complete Test bench on-line monitoredPower Supply

Mux/DAQ

USBinterface

PCB- Hardware ready.- Software almost ready + working tests to do.- Needs only the connection to a laptop under labview. 24

Front End electronics

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Summary of previous progresses

Demonstrator option 2 A single link to the Back End electronics, with the maximum of functionalities inside a custom-made ASIC IBM 130 nm technology holding: - Current conveyors. - ADCs. - Digital integration for Cs calibration. - Part of CIS calibration (DAC outside).

FATALIC family - Based on 3-gain current conveyor associated to shaping stages - Tested at home, then at CERN. FATALIC 1 (June 2010) FATALIC 2 (December 2010) Tests at CERN (LED, Cosmics') [Tilecal week, 7 October 2011] FATALIC 3 (November 2011) Tests at CERN (Digital int.) [Tilecal week, 28 September 2012]

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ADC: TACTIC project

- ”Classical” pipeline ADC architecture. - 12 bits resolution.- 40 Msamples/second.- Technology IBM 130 nm.- Submitted August 2012, received in February

2013.

Architecture

TACTIC 1 (1.8 x 1.8 mm2)

Tests in progress: static and dynamic tests® The chip is alive.® Progress must made on the Test bench.

Part of Test bench

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Next steps and planning

Signal/noise ratio and number of effective bits from sinwave Fourier analysis.

Collaboration with IPHC Strasbourg on a 3in1 board with FATALIC3 + TACTIC1 bounded directly on the PCB.

In the fall, decision about the following step: either a TACTIC2 or a complete FATALIC 4 chip ?

The major issue will be the funding.

Works in parallel

- Final designs of 3in1 card (with DAC) and Mother Board 2. - Improvement of the digital integrator at the noise level: noises are different at home and at CERN: WHY ? new tests at CERN are foreseen. - Decisions on the peaking time and on the shape (now not symmetrical) simulations in progress, going up to the optimal filtering.

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