Stellaris LM3S9B92 Microcontroller Data Sheet (Rev. O) Sheets/Texas Instruments PDFs...TableofContents RevisionHistory.....42

Stellaris LM3S9B92 Microcontroller

DATA SHEET

Copyr ight 2007-2014Texas Instruments Incorporated

DS-LM3S9B92-15852.2743SPMS180O

TEXAS INSTRUMENTS-PRODUCTION DATA

CopyrightCopyright 2007-2014 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as theproperty of others.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductorproducts and disclaimers thereto appears at the end of this data sheet.

Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

July 03, 20142Texas Instruments-Production Data

http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm

Table of ContentsRevision History ............................................................................................................................. 42About This Document .................................................................................................................... 53Audience .............................................................................................................................................. 53About This Manual ................................................................................................................................ 53Related Documents ............................................................................................................................... 53Documentation Conventions .................................................................................................................. 54

1 Architectural Overview .......................................................................................... 561.1 Overview ...................................................................................................................... 561.2 Target Applications ........................................................................................................ 581.3 Features ....................................................................................................................... 581.3.1 ARM Cortex-M3 Processor Core .................................................................................... 581.3.2 On-Chip Memory ........................................................................................................... 601.3.3 External Peripheral Interface ......................................................................................... 611.3.4 Serial Communications Peripherals ................................................................................ 631.3.5 System Integration ........................................................................................................ 691.3.6 Advanced Motion Control ............................................................................................... 731.3.7 Analog .......................................................................................................................... 751.3.8 JTAG and ARM Serial Wire Debug ................................................................................ 771.3.9 Packaging and Temperature .......................................................................................... 781.4 Hardware Details .......................................................................................................... 78

2 The Cortex-M3 Processor ...................................................................................... 792.1 Block Diagram .............................................................................................................. 802.2 Overview ...................................................................................................................... 812.2.1 System-Level Interface .................................................................................................. 812.2.2 Integrated Configurable Debug ...................................................................................... 812.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 822.2.4 Cortex-M3 System Component Details ........................................................................... 822.3 Programming Model ...................................................................................................... 832.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 832.3.2 Stacks .......................................................................................................................... 832.3.3 Register Map ................................................................................................................ 842.3.4 Register Descriptions .................................................................................................... 852.3.5 Exceptions and Interrupts .............................................................................................. 982.3.6 Data Types ................................................................................................................... 982.4 Memory Model .............................................................................................................. 982.4.1 Memory Regions, Types and Attributes ......................................................................... 1002.4.2 Memory System Ordering of Memory Accesses ............................................................ 1012.4.3 Behavior of Memory Accesses ..................................................................................... 1012.4.4 Software Ordering of Memory Accesses ....................................................................... 1022.4.5 Bit-Banding ................................................................................................................. 1032.4.6 Data Storage .............................................................................................................. 1052.4.7 Synchronization Primitives ........................................................................................... 1062.5 Exception Model ......................................................................................................... 1072.5.1 Exception States ......................................................................................................... 1082.5.2 Exception Types .......................................................................................................... 108

3July 03, 2014Texas Instruments-Production Data


2.5.3 Exception Handlers ..................................................................................................... 1112.5.4 Vector Table ................................................................................................................ 1112.5.5 Exception Priorities ...................................................................................................... 1122.5.6 Interrupt Priority Grouping ............................................................................................ 1132.5.7 Exception Entry and Return ......................................................................................... 1132.6 Fault Handling ............................................................................................................. 1152.6.1 Fault Types ................................................................................................................. 1162.6.2 Fault Escalation and Hard Faults .................................................................................. 1162.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1172.6.4 Lockup ....................................................................................................................... 1172.7 Power Management .................................................................................................... 1172.7.1 Entering Sleep Modes ................................................................................................. 1182.7.2 Wake Up from Sleep Mode .......................................................................................... 1182.8 Instruction Set Summary .............................................................................................. 119

3 Cortex-M3 Peripherals ......................................................................................... 1223.1 Functional Description ................................................................................................. 1223.1.1 System Timer (SysTick) ............................................................................................... 1223.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1233.1.3 System Control Block (SCB) ........................................................................................ 1253.1.4 Memory Protection Unit (MPU) ..................................................................................... 1253.2 Register Map .............................................................................................................. 1303.3 System Timer (SysTick) Register Descriptions .............................................................. 1323.4 NVIC Register Descriptions .......................................................................................... 1363.5 System Control Block (SCB) Register Descriptions ........................................................ 1493.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 178

4 JTAG Interface ...................................................................................................... 1884.1 Block Diagram ............................................................................................................ 1894.2 Signal Description ....................................................................................................... 1894.3 Functional Description ................................................................................................. 1904.3.1 JTAG Interface Pins ..................................................................................................... 1904.3.2 JTAG TAP Controller ................................................................................................... 1924.3.3 Shift Registers ............................................................................................................ 1924.3.4 Operational Considerations .......................................................................................... 1934.4 Initialization and Configuration ..................................................................................... 1954.5 Register Descriptions .................................................................................................. 1964.5.1 Instruction Register (IR) ............................................................................................... 1964.5.2 Data Registers ............................................................................................................ 198

5 System Control ..................................................................................................... 2005.1 Signal Description ....................................................................................................... 2005.2 Functional Description ................................................................................................. 2005.2.1 Device Identification .................................................................................................... 2015.2.2 Reset Control .............................................................................................................. 2015.2.3 Non-Maskable Interrupt ............................................................................................... 2065.2.4 Power Control ............................................................................................................. 2065.2.5 Clock Control .............................................................................................................. 2075.2.6 System Control ........................................................................................................... 2135.3 Initialization and Configuration ..................................................................................... 2155.4 Register Map .............................................................................................................. 215


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5.5 Register Descriptions .................................................................................................. 217

6 Internal Memory ................................................................................................... 3086.1 Block Diagram ............................................................................................................ 3086.2 Functional Description ................................................................................................. 3086.2.1 SRAM ........................................................................................................................ 3096.2.2 ROM .......................................................................................................................... 3096.2.3 Flash Memory ............................................................................................................. 3116.3 Register Map .............................................................................................................. 3166.4 Flash Memory Register Descriptions (Flash Control Offset) ............................................ 3176.5 Memory Register Descriptions (System Control Offset) .................................................. 329

7 Micro Direct Memory Access (DMA) ................................................................ 3457.1 Block Diagram ............................................................................................................ 3467.2 Functional Description ................................................................................................. 3467.2.1 Channel Assignments .................................................................................................. 3477.2.2 Priority ........................................................................................................................ 3487.2.3 Arbitration Size ............................................................................................................ 3487.2.4 Request Types ............................................................................................................ 3497.2.5 Channel Configuration ................................................................................................. 3507.2.6 Transfer Modes ........................................................................................................... 3517.2.7 Transfer Size and Increment ........................................................................................ 3607.2.8 Peripheral Interface ..................................................................................................... 3607.2.9 Software Request ........................................................................................................ 3607.2.10 Interrupts and Errors .................................................................................................... 3617.3 Initialization and Configuration ..................................................................................... 3617.3.1 Module Initialization ..................................................................................................... 3617.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 3617.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 3637.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 3647.3.5 Configuring Channel Assignments ................................................................................ 3677.4 Register Map .............................................................................................................. 3677.5 DMA Channel Control Structure ................................................................................. 3687.6 DMA Register Descriptions ........................................................................................ 375

8 General-Purpose Input/Outputs (GPIOs) ........................................................... 4048.1 Signal Description ....................................................................................................... 4048.2 Functional Description ................................................................................................. 4098.2.1 Data Control ............................................................................................................... 4108.2.2 Interrupt Control .......................................................................................................... 4118.2.3 Mode Control .............................................................................................................. 4128.2.4 Commit Control ........................................................................................................... 4128.2.5 Pad Control ................................................................................................................. 4138.2.6 Identification ............................................................................................................... 4138.3 Initialization and Configuration ..................................................................................... 4138.4 Register Map .............................................................................................................. 4148.5 Register Descriptions .................................................................................................. 416

9 External Peripheral Interface (EPI) ..................................................................... 4599.1 EPI Block Diagram ...................................................................................................... 4609.2 Signal Description ....................................................................................................... 461



9.3 Functional Description ................................................................................................. 4639.3.1 Non-Blocking Reads .................................................................................................... 4649.3.2 DMA Operation ........................................................................................................... 4659.4 Initialization and Configuration ..................................................................................... 4659.4.1 SDRAM Mode ............................................................................................................. 4669.4.2 Host Bus Mode ........................................................................................................... 4709.4.3 General-Purpose Mode ............................................................................................... 4819.5 Register Map .............................................................................................................. 4899.6 Register Descriptions .................................................................................................. 490

10 General-Purpose Timers ...................................................................................... 53210.1 Block Diagram ............................................................................................................ 53310.2 Signal Description ....................................................................................................... 53310.3 Functional Description ................................................................................................. 53610.3.1 GPTM Reset Conditions .............................................................................................. 53710.3.2 Timer Modes ............................................................................................................... 53710.3.3 DMA Operation ........................................................................................................... 54310.3.4 Accessing Concatenated Register Values ..................................................................... 54410.4 Initialization and Configuration ..................................................................................... 54410.4.1 One-Shot/Periodic Timer Mode .................................................................................... 54410.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 54510.4.3 Input Edge-Count Mode ............................................................................................... 54510.4.4 Input Edge Timing Mode .............................................................................................. 54610.4.5 PWM Mode ................................................................................................................. 54710.5 Register Map .............................................................................................................. 54710.6 Register Descriptions .................................................................................................. 548

11 Watchdog Timers ................................................................................................. 57911.1 Block Diagram ............................................................................................................ 58011.2 Functional Description ................................................................................................. 58011.2.1 Register Access Timing ............................................................................................... 58111.3 Initialization and Configuration ..................................................................................... 58111.4 Register Map .............................................................................................................. 58111.5 Register Descriptions .................................................................................................. 582

12 Analog-to-Digital Converter (ADC) ..................................................................... 60412.1 Block Diagram ............................................................................................................ 60512.2 Signal Description ....................................................................................................... 60612.3 Functional Description ................................................................................................. 60812.3.1 Sample Sequencers .................................................................................................... 60812.3.2 Module Control ............................................................................................................ 60912.3.3 Hardware Sample Averaging Circuit ............................................................................. 61112.3.4 Analog-to-Digital Converter .......................................................................................... 61212.3.5 Differential Sampling ................................................................................................... 61512.3.6 Internal Temperature Sensor ........................................................................................ 61812.3.7 Digital Comparator Unit ............................................................................................... 61812.4 Initialization and Configuration ..................................................................................... 62312.4.1 Module Initialization ..................................................................................................... 62312.4.2 Sample Sequencer Configuration ................................................................................. 62412.5 Register Map .............................................................................................................. 62412.6 Register Descriptions .................................................................................................. 626


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13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 68413.1 Block Diagram ............................................................................................................ 68513.2 Signal Description ....................................................................................................... 68513.3 Functional Description ................................................................................................. 68713.3.1 Transmit/Receive Logic ............................................................................................... 68813.3.2 Baud-Rate Generation ................................................................................................. 68813.3.3 Data Transmission ...................................................................................................... 68913.3.4 Serial IR (SIR) ............................................................................................................. 68913.3.5 ISO 7816 Support ....................................................................................................... 69013.3.6 Modem Handshake Support ......................................................................................... 69113.3.7 LIN Support ................................................................................................................ 69213.3.8 FIFO Operation ........................................................................................................... 69313.3.9 Interrupts .................................................................................................................... 69413.3.10 Loopback Operation .................................................................................................... 69513.3.11 DMA Operation ........................................................................................................... 69513.4 Initialization and Configuration ..................................................................................... 69513.5 Register Map .............................................................................................................. 69613.6 Register Descriptions .................................................................................................. 698

14 Synchronous Serial Interface (SSI) .................................................................... 74814.1 Block Diagram ............................................................................................................ 74914.2 Signal Description ....................................................................................................... 74914.3 Functional Description ................................................................................................. 75014.3.1 Bit Rate Generation ..................................................................................................... 75114.3.2 FIFO Operation ........................................................................................................... 75114.3.3 Interrupts .................................................................................................................... 75114.3.4 Frame Formats ........................................................................................................... 75214.3.5 DMA Operation ........................................................................................................... 75914.4 Initialization and Configuration ..................................................................................... 76014.5 Register Map .............................................................................................................. 76114.6 Register Descriptions .................................................................................................. 762

15 Inter-Integrated Circuit (I2C) Interface ................................................................ 79015.1 Block Diagram ............................................................................................................ 79115.2 Signal Description ....................................................................................................... 79115.3 Functional Description ................................................................................................. 79215.3.1 I2C Bus Functional Overview ........................................................................................ 79215.3.2 Available Speed Modes ............................................................................................... 79415.3.3 Interrupts .................................................................................................................... 79515.3.4 Loopback Operation .................................................................................................... 79615.3.5 Command Sequence Flow Charts ................................................................................ 79715.4 Initialization and Configuration ..................................................................................... 80415.5 Register Map .............................................................................................................. 80515.6 Register Descriptions (I2C Master) ............................................................................... 80615.7 Register Descriptions (I2C Slave) ................................................................................. 819

16 Inter-Integrated Circuit Sound (I2S) Interface .................................................... 82816.1 Block Diagram ............................................................................................................ 82916.2 Signal Description ....................................................................................................... 82916.3 Functional Description ................................................................................................. 830



16.3.1 Transmit ..................................................................................................................... 83216.3.2 Receive ...................................................................................................................... 83616.4 Initialization and Configuration ..................................................................................... 83816.5 Register Map .............................................................................................................. 83916.6 Register Descriptions .................................................................................................. 840

17 Controller Area Network (CAN) Module ............................................................. 86517.1 Block Diagram ............................................................................................................ 86617.2 Signal Description ....................................................................................................... 86617.3 Functional Description ................................................................................................. 86717.3.1 Initialization ................................................................................................................. 86817.3.2 Operation ................................................................................................................... 86917.3.3 Transmitting Message Objects ..................................................................................... 87017.3.4 Configuring a Transmit Message Object ........................................................................ 87017.3.5 Updating a Transmit Message Object ........................................................................... 87117.3.6 Accepting Received Message Objects .......................................................................... 87217.3.7 Receiving a Data Frame .............................................................................................. 87217.3.8 Receiving a Remote Frame .......................................................................................... 87217.3.9 Receive/Transmit Priority ............................................................................................. 87317.3.10 Configuring a Receive Message Object ........................................................................ 87317.3.11 Handling of Received Message Objects ........................................................................ 87417.3.12 Handling of Interrupts .................................................................................................. 87617.3.13 Test Mode ................................................................................................................... 87717.3.14 Bit Timing Configuration Error Considerations ............................................................... 87917.3.15 Bit Time and Bit Rate ................................................................................................... 87917.3.16 Calculating the Bit Timing Parameters .......................................................................... 88117.4 Register Map .............................................................................................................. 88417.5 CAN Register Descriptions .......................................................................................... 885

18 Ethernet Controller .............................................................................................. 91618.1 Block Diagram ............................................................................................................ 91718.2 Signal Description ....................................................................................................... 91818.3 Functional Description ................................................................................................. 91918.3.1 MAC Operation ........................................................................................................... 91918.3.2 Internal MII Operation .................................................................................................. 92218.3.3 PHY Operation ............................................................................................................ 92218.3.4 Interrupts .................................................................................................................... 92518.3.5 DMA Operation ........................................................................................................... 92518.4 Initialization and Configuration ..................................................................................... 92618.4.1 Hardware Configuration ............................................................................................... 92618.4.2 Software Configuration ................................................................................................ 92718.5 Register Map .............................................................................................................. 92718.6 Ethernet MAC Register Descriptions ............................................................................. 92918.7 MII Management Register Descriptions ......................................................................... 954

19 Universal Serial Bus (USB) Controller ............................................................... 97519.1 Block Diagram ............................................................................................................ 97619.2 Signal Description ....................................................................................................... 97619.3 Functional Description ................................................................................................. 97819.3.1 Operation as a Device ................................................................................................. 97819.3.2 Operation as a Host .................................................................................................... 983


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19.3.3 OTG Mode .................................................................................................................. 98719.3.4 DMA Operation ........................................................................................................... 98919.4 Initialization and Configuration ..................................................................................... 99019.4.1 Pin Configuration ......................................................................................................... 99019.4.2 Endpoint Configuration ................................................................................................ 99119.5 Register Map .............................................................................................................. 99119.6 Register Descriptions ................................................................................................. 1002

20 Analog Comparators .......................................................................................... 111420.1 Block Diagram ........................................................................................................... 111520.2 Signal Description ..................................................................................................... 111520.3 Functional Description ............................................................................................... 111620.3.1 Internal Reference Programming ................................................................................ 111720.4 Initialization and Configuration .................................................................................... 111820.5 Register Map ............................................................................................................ 111920.6 Register Descriptions ................................................................................................. 1120

21 Pulse Width Modulator (PWM) .......................................................................... 112821.1 Block Diagram ........................................................................................................... 112921.2 Signal Description ..................................................................................................... 113021.3 Functional Description ............................................................................................... 113321.3.1 PWM Timer ............................................................................................................... 113321.3.2 PWM Comparators .................................................................................................... 113321.3.3 PWM Signal Generator .............................................................................................. 113521.3.4 Dead-Band Generator ............................................................................................... 113521.3.5 Interrupt/ADC-Trigger Selector ................................................................................... 113621.3.6 Synchronization Methods .......................................................................................... 113621.3.7 Fault Conditions ........................................................................................................ 113721.3.8 Output Control Block .................................................................................................. 113821.4 Initialization and Configuration .................................................................................... 113821.5 Register Map ............................................................................................................ 113921.6 Register Descriptions ................................................................................................. 1142

22 Quadrature Encoder Interface (QEI) ................................................................. 120522.1 Block Diagram ........................................................................................................... 120522.2 Signal Description ..................................................................................................... 120622.3 Functional Description ............................................................................................... 120722.4 Initialization and Configuration .................................................................................... 120922.5 Register Map ............................................................................................................ 121022.6 Register Descriptions ................................................................................................. 1211

23 Pin Diagram ........................................................................................................ 122824 Signal Tables ...................................................................................................... 123024.1 100-Pin LQFP Package Pin Tables ............................................................................. 123124.1.1 Signals by Pin Number .............................................................................................. 123124.1.2 Signals by Signal Name ............................................................................................. 124324.1.3 Signals by Function, Except for GPIO ......................................................................... 125324.1.4 GPIO Pins and Alternate Functions ............................................................................ 126224.1.5 Possible Pin Assignments for Alternate Functions ....................................................... 126524.2 108-Ball BGA Package Pin Tables .............................................................................. 126824.2.1 Signals by Pin Number .............................................................................................. 1268



24.2.2 Signals by Signal Name ............................................................................................. 128024.2.3 Signals by Function, Except for GPIO ......................................................................... 129124.2.4 GPIO Pins and Alternate Functions ............................................................................ 130024.2.5 Possible Pin Assignments for Alternate Functions ....................................................... 130324.3 Connections for Unused Signals ................................................................................. 1306

25 Operating Characteristics ................................................................................. 130826 Electrical Characteristics .................................................................................. 130926.1 Maximum Ratings ...................................................................................................... 130926.2 Recommended Operating Conditions ......................................................................... 130926.3 Load Conditions ........................................................................................................ 131026.4 JTAG and Boundary Scan .......................................................................................... 131026.5 Power and Brown-Out ............................................................................................... 131226.6 Reset ........................................................................................................................ 131326.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 131426.8 Clocks ...................................................................................................................... 131426.8.1 PLL Specifications ..................................................................................................... 131426.8.2 PIOSC Specifications ................................................................................................ 131526.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 131526.8.4 Main Oscillator Specifications ..................................................................................... 131626.8.5 System Clock Specification with ADC Operation .......................................................... 131726.8.6 System Clock Specification with USB Operation .......................................................... 131726.9 Sleep Modes ............................................................................................................. 131726.10 Flash Memory ........................................................................................................... 131726.11 Input/Output Characteristics ....................................................................................... 131826.12 External Peripheral Interface (EPI) .............................................................................. 131826.13 Analog-to-Digital Converter (ADC) .............................................................................. 132426.14 Synchronous Serial Interface (SSI) ............................................................................. 132526.15 Inter-Integrated Circuit (I2C) Interface ......................................................................... 132726.16 Inter-Integrated Circuit Sound (I2S) Interface ............................................................... 132826.17 Ethernet Controller .................................................................................................... 132926.18 Universal Serial Bus (USB) Controller ......................................................................... 133226.19 Analog Comparator ................................................................................................... 133226.20 Current Consumption ................................................................................................. 133326.20.1 Nominal Power Consumption ..................................................................................... 133326.20.2 Maximum Current Consumption ................................................................................. 1333

A Register Quick Reference ................................................................................. 1335B Ordering and Contact Information ................................................................... 1390B.1 Ordering Information .................................................................................................. 1390B.2 Part Markings ............................................................................................................ 1390B.3 Kits ........................................................................................................................... 1390B.4 Support Information ................................................................................................... 1391

C Package Information .......................................................................................... 1392C.1 100-Pin LQFP Package ............................................................................................. 1392C.1.1 Package Dimensions ................................................................................................. 1392C.1.2 Tray Dimensions ....................................................................................................... 1394C.1.3 Tape and Reel Dimensions ........................................................................................ 1394C.2 108-Ball BGA Package .............................................................................................. 1396


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C.2.1 Package Dimensions ................................................................................................. 1396C.2.2 Tray Dimensions ....................................................................................................... 1398C.2.3 Tape and Reel Dimensions ........................................................................................ 1399



List of FiguresFigure 1-1. Stellaris LM3S9B92 Microcontroller High-Level Block Diagram ............................... 57Figure 2-1. CPU Block Diagram ............................................................................................. 81Figure 2-2. TPIU Block Diagram ............................................................................................ 82Figure 2-3. Cortex-M3 Register Set ........................................................................................ 84Figure 2-4. Bit-Band Mapping .............................................................................................. 105Figure 2-5. Data Storage ..................................................................................................... 106Figure 2-6. Vector Table ...................................................................................................... 112Figure 2-7. Exception Stack Frame ...................................................................................... 114Figure 3-1. SRD Use Example ............................................................................................. 128Figure 4-1. JTAG Module Block Diagram .............................................................................. 189Figure 4-2. Test Access Port State Machine ......................................................................... 192Figure 4-3. IDCODE Register Format ................................................................................... 198Figure 4-4. BYPASS Register Format ................................................................................... 199Figure 4-5. Boundary Scan Register Format ......................................................................... 199Figure 5-1. Basic RST Configuration .................................................................................... 203Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 203Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 204Figure 5-4. Power Architecture ............................................................................................ 207Figure 5-5. Main Clock Tree ................................................................................................ 209Figure 6-1. Internal Memory Block Diagram .......................................................................... 308Figure 7-1. DMA Block Diagram ......................................................................................... 346Figure 7-2. Example of Ping-Pong DMA Transaction ........................................................... 353Figure 7-3. Memory Scatter-Gather, Setup and Configuration ................................................ 355Figure 7-4. Memory Scatter-Gather, DMA Copy Sequence .................................................. 356Figure 7-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 358Figure 7-6. Peripheral Scatter-Gather, DMA Copy Sequence ............................................... 359Figure 8-1. Digital I/O Pads ................................................................................................. 409Figure 8-2. Analog/Digital I/O Pads ...................................................................................... 410Figure 8-3. GPIODATA Write Example ................................................................................. 411Figure 8-4. GPIODATA Read Example ................................................................................. 411Figure 9-1. EPI Block Diagram ............................................................................................. 461Figure 9-2. SDRAM Non-Blocking Read Cycle ...................................................................... 469Figure 9-3. SDRAM Normal Read Cycle ............................................................................... 469Figure 9-4. SDRAM Write Cycle ........................................................................................... 470Figure 9-5. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 476Figure 9-6. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 478Figure 9-7. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 479Figure 9-8. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 479Figure 9-9. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual

CSn .................................................................................................................. 480Figure 9-10. Continuous Read Mode Accesses ...................................................................... 480Figure 9-11. Write Followed by Read to External FIFO ............................................................ 481Figure 9-12. Two-Entry FIFO ................................................................................................. 481Figure 9-13. Single-Cycle Write Access, FRM50=0, FRMCNT=0, WRCYC=0 ........................... 485


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Figure 9-14. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, RDCYC=1,WRCYC=1 ........................................................................................................ 485

Figure 9-15. Read Accesses, FRM50=0, FRMCNT=0, RDCYC=1 ............................................ 486Figure 9-16. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 486Figure 9-17. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 486Figure 9-18. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 487Figure 9-19. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 487Figure 9-20. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 487Figure 9-21. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 487Figure 9-22. iRDY Signal Operation, FRM50=0, FRMCNT=0, and RD2CYC=1 ......................... 488Figure 9-23. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 489Figure 9-24. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 489Figure 10-1. GPTM Module Block Diagram ............................................................................ 533Figure 10-2. Timer Daisy Chain ............................................................................................. 539Figure 10-3. Input Edge-Count Mode Example ....................................................................... 541Figure 10-4. 16-Bit Input Edge-Time Mode Example ............................................................... 542Figure 10-5. 16-Bit PWM Mode Example ................................................................................ 543Figure 11-1. WDT Module Block Diagram .............................................................................. 580Figure 12-1. Implementation of Two ADC Blocks .................................................................... 605Figure 12-2. ADC Module Block Diagram ............................................................................... 606Figure 12-3. ADC Sample Phases ......................................................................................... 610Figure 12-4. Doubling the ADC Sample Rate .......................................................................... 611Figure 12-5. Skewed Sampling .............................................................................................. 611Figure 12-6. Sample Averaging Example ............................................................................... 612Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 613Figure 12-8. Internal Voltage Conversion Result ..................................................................... 614Figure 12-9. External Voltage Conversion Result .................................................................... 615Figure 12-10. Differential Sampling Range, VIN_ODD = 1.5 V ...................................................... 616Figure 12-11. Differential Sampling Range, VIN_ODD = 0.75 V .................................................... 617Figure 12-12. Differential Sampling Range, VIN_ODD = 2.25 V .................................................... 617Figure 12-13. Internal Temperature Sensor Characteristic ......................................................... 618Figure 12-14. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 621Figure 12-15. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 622Figure 12-16. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 623Figure 13-1. UART Module Block Diagram ............................................................................. 685Figure 13-2. UART Character Frame ..................................................................................... 688Figure 13-3. IrDA Data Modulation ......................................................................................... 690Figure 13-4. LIN Message ..................................................................................................... 692Figure 13-5. LIN Synchronization Field ................................................................................... 693Figure 14-1. SSI Module Block Diagram ................................................................................. 749Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 753Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 753Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 754Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 754Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 755Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 756Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 756Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 757



Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 758Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 759Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 759Figure 15-1. I2C Block Diagram ............................................................................................. 791Figure 15-2. I2C Bus Configuration ........................................................................................ 792Figure 15-3. START and STOP Conditions ............................................................................. 793Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 793Figure 15-5. R/S Bit in First Byte ............................................................................................ 794Figure 15-6. Data Validity During Bit Transfer on the I2C Bus ................................................... 794Figure 15-7. Master Single TRANSMIT .................................................................................. 798Figure 15-8. Master Single RECEIVE ..................................................................................... 799Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 800Figure 15-10. Master RECEIVE with Repeated START ............................................................. 801Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated

START .............................................................................................................. 802Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated

START .............................................................................................................. 803Figure 15-13. Slave Command Sequence ................................................................................ 804Figure 16-1. I2S Block Diagram ............................................................................................. 829Figure 16-2. I2S Data Transfer ............................................................................................... 832Figure 16-3. Left-Justified Data Transfer ................................................................................ 832Figure 16-4. Right-Justified Data Transfer .............................................................................. 832Figure 17-1. CAN Controller Block Diagram ............................................................................ 866Figure 17-2. CAN Data/Remote Frame .................................................................................. 868Figure 17-3. Message Objects in a FIFO Buffer ...................................................................... 876Figure 17-4. CAN Bit Time .................................................................................................... 880Figure 18-1. Ethernet Controller ............................................................................................. 917Figure 18-2. Ethernet Controller Block Diagram ...................................................................... 917Figure 18-3. Ethernet Frame ................................................................................................. 919Figure 18-4. Interface to an Ethernet Jack .............................................................................. 926Figure 19-1. USB Module Block Diagram ............................................................................... 976Figure 20-1. Analog Comparator Module Block Diagram ....................................................... 1115Figure 20-2. Structure of Comparator Unit ............................................................................ 1117Figure 20-3. Comparator Internal Reference Structure .......................................................... 1117Figure 21-1. PWM Module Diagram ..................................................................................... 1130Figure 21-2. PWM Generator Block Diagram ........................................................................ 1130Figure 21-3. PWM Count-Down Mode .................................................................................. 1134Figure 21-4. PWM Count-Up/Down Mode ............................................................................. 1134Figure 21-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1135Figure 21-6. PWM Dead-Band Generator ............................................................................. 1136Figure 22-1. QEI Block Diagram .......................................................................................... 1206Figure 22-2. Quadrature Encoder and Velocity Predivider Operation ...................................... 1208Figure 23-1. 100-Pin LQFP Package Pin Diagram ................................................................ 1228Figure 23-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................. 1229Figure 26-1. Load Conditions ............................................................................................... 1310Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1311Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1311Figure 26-4. Power-On Reset Timing ................................................................................... 1312


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Figure 26-5. Brown-Out Reset Timing .................................................................................. 1312Figure 26-6. Power-On Reset and Voltage Parameters ......................................................... 1313Figure 26-7. External Reset Timing (RST) ............................................................................ 1313Figure 26-8. Software Reset Timing ..................................................................................... 1313Figure 26-9. Watchdog Reset Timing ................................................................................... 1314Figure 26-10. MOSC Failure Reset Timing ............................................................................. 1314Figure 26-11. SDRAM Initialization and Load Mode Register Timing ........................................ 1319Figure 26-12. SDRAM Read Timing ....................................................................................... 1319Figure 26-13. SDRAM Write Timing ....................................................................................... 1320Figure 26-14. Host-Bus 8/16 Mode Read Timing ..................................................................... 1321Figure 26-15. Host-Bus 8/16 Mode Write Timing ..................................................................... 1321Figure 26-16. Host-Bus 8/16 Mode Muxed Read Timing .......................................................... 1322Figure 26-17. Host-Bus 8/16 Mode Muxed Write Timing .......................................................... 1322Figure 26-18. General-Purpose Mode Read and Write Timing ................................................. 1323Figure 26-19. General-Purpose Mode iRDY Timing ................................................................. 1323Figure 26-20. ADC Input Equivalency Diagram ....................................................................... 1325Figure 26-21. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1326Figure 26-22. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............... 1326Figure 26-23. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................... 1327Figure 26-24. I2C Timing ....................................................................................................... 1328Figure 26-25. I2S Master Mode Transmit Timing ..................................................................... 1328Figure 26-26. I2S Master Mode Receive Timing ...................................................................... 1329Figure 26-27. I2S Slave Mode Transmit Timing ....................................................................... 1329Figure 26-28. I2S Slave Mode Receive Timing ........................................................................ 1329Figure 26-29. External XTLP Oscillator Characteristics ........................................................... 1332Figure C-1. Stellaris LM3S9B92 100-Pin LQFP Package Dimensions ................................... 1392Figure C-2. 100-Pin LQFP Tray Dimensions ........................................................................ 1394Figure C-3. 100-Pin LQFP Tape and Reel Dimensions ......................................................... 1395Figure C-4. Stellaris LM3S9B92 108-Ball BGA Package Dimensions .................................... 1396Figure C-5. 108-Ball BGA Tray Dimensions ......................................................................... 1398Figure C-6. 108-Ball BGA Tape and Reel Dimensions .......................................................... 1399



List of TablesTable 1. Revision History .................................................................................................. 42Table 2. Documentation Conventions ................................................................................ 54Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 84Table 2-2. Processor Register Map ....................................................................................... 85Table 2-3. PSR Register Combinations ................................................................................. 90Table 2-4. Memory Map ....................................................................................................... 98Table 2-5. Memory Access Behavior ................................................................................... 101Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 103Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 103Table 2-8. Exception Types ................................................................................................ 109Table 2-9. Interrupts .......................................................................................................... 110Table 2-10. Exception Return Behavior ................................................................................. 115Table 2-11. Faults ............................................................................................................... 116Table 2-12. Fault Status and Fault Address Registers ............................................................ 117Table 2-13. Cortex-M3 Instruction Summary ......................................................................... 119Table 3-1. Core Peripheral Register Regions ....................................................................... 122Table 3-2. Memory Attributes Summary .............................................................................. 125Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 128Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 129Table 3-5. AP Bit Field Encoding ........................................................................................ 129Table 3-6. Memory Region Attributes for Stellaris Microcontrollers ........................................ 129Table 3-7. Peripherals Register Map ................................................................................... 130Table 3-8. Interrupt Priority Levels ...................................................................................... 157Table 3-9. Example SIZE Field Values ................................................................................ 185Table 4-1. JTAG_SWD_SWO Signals (100LQFP) ................................................................ 189Table 4-2. JTAG_SWD_SWO Signals (108BGA) ................................................................. 190Table 4-3. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 191Table 4-4. JTAG Instruction Register Commands ................................................................. 196Table 5-1. System Control & Clocks Signals (100LQFP) ...................................................... 200Table 5-2. System Control & Clocks Signals (108BGA) ........................................................ 200Table 5-3. Reset Sources ................................................................................................... 201Table 5-4. Clock Source Options ........................................................................................ 208Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field ............................... 210Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 210Table 5-7. Examples of Possible System Clock Frequencies with DIV400=1 ......................... 211Table 5-8. System Control Register Map ............................................................................. 215Table 5-9. RCC2 Fields that Override RCC Fields ............................................................... 237Table 6-1. Flash Memory Protection Policy Combinations .................................................... 312Table 6-2. User-Programmable Flash Memory Resident Registers ....................................... 316Table 6-3. Flash Register Map ............................................................................................ 316Table 7-1. DMA Channel Assignments .............................................................................. 347Table 7-2. Request Type Support ....................................................................................... 349Table 7-3. Control Structure Memory Map ........................................................................... 350Table 7-4. Channel Control Structure .................................................................................. 350Table 7-5. DMA Read Example: 8-Bit Peripheral ................................................................ 360Table 7-6. DMA Interrupt Assignments .............................................................................. 361


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Table 7-7. Channel Control Structure Offsets for Channel 30 ................................................ 362Table 7-8. Channel Control Word Configuration for Memory Transfer Example ...................... 362Table 7-9. Channel Control Structure Offsets for Channel 7 .................................................. 363Table 7-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 364Table 7-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 365Table 7-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 366Table 7-13. DMA Register Map .......................................................................................... 367Table 8-1. GPIO Pins With Non-Zero Reset Values .............................................................. 405Table 8-2. GPIO Pins and Alternate Functions (100LQFP) ................................................... 405Table 8-3. GPIO Pins and Alternate Functions (108BGA) ..................................................... 407Table 8-4. GPIO Pad Configuration Examples ..................................................................... 413Table 8-5. GPIO Interrupt Configuration Example ................................................................ 414Table 8-6. GPIO Pins With Non-Zero Reset Values .............................................................. 415Table 8-7. GPIO Register Map ........................................................................................... 415Table 8-8. GPIO Pins With Non-Zero Reset Values .............................................................. 427Table 8-9. GPIO Pins With Non-Zero Reset Values .............................................................. 433Table 8-10. GPIO Pins With Non-Zero Reset Values .............................................................. 435Table 8-11. GPIO Pins With Non-Zero Reset Values .............................................................. 438Table 8-12. GPIO Pins With Non-Zero Reset Values .............................................................. 445Table 9-1. External Peripheral Interface Signals (100LQFP) ................................................. 461Table 9-2. External Peripheral Interface Signals (108BGA) ................................................... 462Table 9-3. EPI SDRAM Signal Connections ......................................................................... 467Table 9-4. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 471Table 9-5. EPI Host-Bus 8 Signal Connections .................................................................... 472Table 9-6. EPI Host-Bus 16 Signal Connections .................................................................. 474Table 9-7. EPI General Purpose Signal Connections ........................................................... 483Table 9-8. External Peripheral Interface (EPI) Register Map ................................................. 489Table 10-1. Available CCP Pins ............................................................................................ 533Table 10-2. General-Purpose Timers Signals (100LQFP) ....................................................... 534Table 10-3. General-Purpose Timers Signals (108BGA) ......................................................... 535Table 10-4. General-Purpose Timer Capabilities .................................................................... 536Table 10-5. Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 537Table 10-6. 16-Bit Timer With Prescaler Configurations ......................................................... 538Table 10-7. Counter Values When the Timer is Enabled in RTC Mode .................................... 539Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 540Table 10-9. Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 541Table 10-10. Counter Values When the Timer is Enabled in PWM Mode ................................... 542Table 10-11. Timers Register Map .......................................................................................... 547Table 11-1. Watchdog Timers Register Map .......................................................................... 582Table 12-1. ADC Signals (100LQFP) .................................................................................... 606Table 12-2. ADC Signals (108BGA) ...................................................................................... 607Table 12-3. Samples and FIFO Depth of Sequencers ............................................................ 608Table 12-4. Differential Sampling Pairs ................................................................................. 615Table 12-5. ADC Register Map ............................................................................................. 624Table 13-1. UART Signals (100LQFP) .................................................................................. 686Table 13-2. UART Signals (108BGA) .................................................................................... 686Table 13-3. Flow Control Mode ............................................................................................. 692



Table 13-4. UART Register Map ........................................................................................... 697Table 14-1. SSI Signals (100LQFP) ...................................................................................... 750Table 14-2. SSI Signals (108BGA) ........................................................................................ 750Table 14-3. SSI Register Map .............................................................................................. 761Table 15-1. I2C Signals (100LQFP) ...................................................................................... 791Table 15-2. I2C Signals (108BGA) ........................................................................................ 791Table 15-3. Examples of I2C Master Timer Period versus Speed Mode ................................... 795Table 15-4. Inter-Integrated Circuit (I2C) Interface Register Map ............................................. 805Table 15-5. Write Field Decoding for I2CMCS[3:0] Field ......................................................... 811Table 16-1. I2S Signals (100LQFP) ...................................................................................... 830Table 16-2. I2S Signals (108BGA) ........................................................................................ 830Table 16-3. I2S Transmit FIFO Interface ................................................................................ 833Table 16-4. Crystal Frequency (Values from 3.5795 MHz to 5 MHz) ........................................ 834Table 16-5. Crystal Frequency (Values from 5.12 MHz to 8.192 MHz) ..................................... 834Table 16-6. Crystal Frequency (Values from 10 MHz to 14.3181 MHz) .................................... 835Table 16-7. Crystal Frequency (Values from 16 MHz to 16.384 MHz) ...................................... 835Table 16-8. I2S Receive FIFO Interface ................................................................................. 837Table 16-9. Audio Formats Configuration .............................................................................. 839Table 16-10. Inter-Integrated Circuit Sound (I2S) Interface Register Map ................................... 840Table 17-1. Controller Area Network Signals (100LQFP) ........................................................ 867Table 17-2. Controller Area Network Signals (108BGA) ......................................................... 867Table 17-3. Message Object Configurations .......................................................................... 873Table 17-4. CAN Protocol Ranges ........................................................................................ 880Table 17-5. CANBIT Register Values .................................................................................... 880Table 17-6. CAN Register Map ............................................................................................. 884Table 18-1. Ethernet Signals (100LQFP) ............................................................................... 918Table 18-2. Ethernet Signals (108BGA) ................................................................................ 918Table 18-3. TX & RX FIFO Organization ............................................................................... 921Table 18-4. Ethernet Register Map ....................................................................................... 928Table 19-1. USB Signals (100LQFP) .................................................................................... 977Table 19-2. USB Signals (108BGA) ...................................................................................... 977Table 19-3. Remainder (MAXLOAD/4) .................................................................................. 989Table 19-4. Actual Bytes Read ............................................................................................. 989Table 19-5. Packet Sizes That Clear RXRDY ........................................................................ 990Table 19-6. Universal Serial Bus (USB) Controller Register Map ............................................ 991Table 20-1. Analog Comparators Signals (100LQFP) ........................................................... 1115Table 20-2. Analog Comparators Signals (108BGA) ............................................................. 1116Table 20-3. Internal Reference Voltage and ACREFCTL Field Values ................................... 1118Table 20-4. Analog Comparators Register Map ................................................................... 1119Table 21-1. PWM Signals (100LQFP) ................................................................................. 1131Table 21-2. PWM Signals (108BGA) ................................................................................... 1132Table 21-3. PWM Register Map .......................................................................................... 1139Table 22-1. QEI Signals (100LQFP) .................................................................................... 1206Table 22-2. QEI Signals (108BGA) ..................................................................................... 1207Table 22-3. QEI Register Map ............................................................................................ 1210Table 24-1. GPIO Pins With Default Alternate Functions ...................................................... 1230Table 24-2. Signals by Pin Number ..................................................................................... 1231Table 24-3. Signals by Signal Name ................................................................................... 1243


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Table 24-4. Signals by Function, Except for GPIO ............................................................... 1253Table 24-5. GPIO Pins and Alternate Functions ................................................................... 1262Table 24-6. Possible Pin Assignments for Alternate Functions .............................................. 1265Table 24-7. Signals by Pin Number ..................................................................................... 1268Table 24-8. Signals by Signal Name ................................................................................... 1280Table 24-9. Signals by Function, Except for GPIO ............................................................... 1291Table 24-10. GPIO Pins and Alternate Functions ................................................................... 1300Table 24-11. Possible Pin Assignments for Alternate Functions .............................................. 1303Table 24-12. Connections for Unused Signals (100-Pin LQFP) ............................................... 1306Table 24-13. Connections for Unused Signals (108-Ball BGA) ................................................ 1307Table 25-1. Temperature Characteristics ............................................................................. 1308Table 25-2. Thermal Characteristics ................................................................................... 1308Table 25-3. ESD Absolute Maximum Ratings ...................................................................... 1308Table 26-1. Maximum Ratings .............................................................