Stratix Handbook

8/3/2019 Stratix Handbook

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101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com

Stratix Device Handbook, Volume 1

S5V1-3.4
http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.altera.com/http://www.altera.com/


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Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device des-

ignations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks andservice marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al-tera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrantsperformance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the ap-plication or use of any information, product, or service described herein except as expressly agreed to in writing by AlteraCorporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published in-formation and before placing orders for products or services.

ii Altera Corporation


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Altera Corporation iii

Contents

Chapter Revision Dates .......................................................................... vii

About This Handbook .............................................................................. ixHow to Find Information ........................................................................................................................ ixHow to Contact Altera ............................................................................................................................. ixTypographic Conventions ........................................................................................................................ x

Section I. Stratix Device Family Data SheetRevision History ............................................................................................................................ Part I1

Chapter 1. IntroductionIntroduction ............................................................................................................................................ 11Features ................................................................................................................................................... 12

Chapter 2. Stratix ArchitectureFunctional Description .......................................................................................................................... 21Logic Array Blocks ................................................................................................................................ 23

LAB Interconnects ............................................................................................................................ 24LAB Control Signals ......................................................................................................................... 25

Logic Elements ....................................................................................................................................... 26LUT Chain & Register Chain .......................................................................................................... 28addnsub Signal ................................................................................................................................. 28LE Operating Modes ........................................................................................................................ 28Clear & Preset Logic Control ........................................................................................................ 213

MultiTrack Interconnect ........................................................................................................ ............. 214TriMatrix Memory ............................................................................................................................... 221

Memory Modes ............................................................................................................................... 222Clear Signals .................................................................................................................................... 224Parity Bit Support ........................................................................................................................... 224Shift Register Support .................................................................................................................... 225

Memory Block Size ......................................................................................................................... 226Independent Clock Mode .............................................................................................................. 244Input/Output Clock Mode ........................................................................................................... 246Read/Write Clock Mode ............................................................................................................... 249Single-Port Mode ............................................................................................................................ 251Multiplier Block .............................................................................................................................. 257Adder/Output Blocks ................................................................................................................... 261Modes of Operation ....................................................................................................................... 264


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iv Altera Corporation

Contents Stratix Device Handbook, Volume 1

DSP Block Interface ........................................................................................................................ 270PLLs & Clock Networks ..................................................................................................................... 273

Global & Hierarchical Clocking ................................................................................................... 273Enhanced & Fast PLLs ................................................................................................................... 281Enhanced PLLs ............................................................................................................................... 287

Fast PLLs ........................................................................................................................................ 2100I/O Structure ...................................................................................................................................... 2104Double-Data Rate I/O Pins ......................................................................................................... 2111External RAM Interfacing ........................................................................................................... 2115Programmable Drive Strength ................................................................................................... 2119Open-Drain Output ...................................................................................................................... 2120Slew-Rate Control ........................................................................................................................ 2120Bus Hold ........................................................................................................................................ 2121Programmable Pull-Up Resistor ................................................................................................ 2122Advanced I/O Standard Support .............................................................................................. 2122Differential On-Chip Termination ............................................................................................. 2127MultiVolt I/O Interface ............................................................................................................... 2129

High-Speed Differential I/O Support ............................................................................................ 2130Dedicated Circuitry ...................................................................................................................... 2137Byte Alignment ............................................................................................................................. 2140

Power Sequencing & Hot Socketing ............................................................................................... 2140

Chapter 3. Configuration & TestingIEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 31SignalTap II Embedded Logic Analyzer ............................................................................................ 35Configuration ......................................................................................................................................... 35

Operating Modes .............................................................................................................................. 35Configuring Stratix FPGAs with JRunner .................................................................................... 37

Configuration Schemes ................................................................................................................... 37Partial Reconfiguration .................................................................................................................... 37Remote Update Configuration Modes .......................................................................................... 38

Stratix Automated Single Event Upset (SEU) Detection ................................................................ 312Custom-Built Circuitry .................................................................................................................. 313Software Interface ........................................................................................................................... 313

Temperature Sensing Diode ............................................................................................................... 313

Chapter 4. DC & Switching CharacteristicsOperating Conditions ........................................................................................................................... 41Power Consumption ........................................................................................................................... 417

Timing Model ....................................................................................................................................... 419Preliminary & Final Timing .......................................................................................................... 419Performance .................................................................................................................................... 420Internal Timing Parameters .......................................................................................................... 422External Timing Parameters ......................................................................................................... 433Stratix External I/O Timing .......................................................................................................... 436I/O Timing Measurement Methodology .................................................................................... 460External I/O Delay Parameters .................................................................................................... 466


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Altera Corporation v

Contents Contents

Maximum Input & Output Clock Rates ...................................................................................... 476High-Speed I/O Specification ........................................................................................................... 487PLL Specifications ................................................................................................................................ 494DLL Specifications ............................................................................................................................. 4102

Chapter 5. Reference & Ordering InformationSoftware .................................................................................................................................................. 51Device Pin-Outs ..................................................................................................................................... 51Ordering Information ........................................................................................................................... 51

Index


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vi Altera Corporation

Contents Stratix Device Handbook, Volume 1


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Altera Corporation vii

Chapter Revision Dates

The chapters in this book, Stratix Device Handbook, Volume 1, were revised on the following dates.Where chapters or groups of chapters are available separately, part numbers are listed.

Chapter 1. IntroductionRevised: July 2005Part number: S51001-3.2

Chapter 2. Stratix ArchitectureRevised: July 2005Part number: S51002-3.2

Chapter 3. Configuration & TestingRevised: July 2005Part number: S51003-1.3

Chapter 4. DC & Switching CharacteristicsRevised: January 2006Part number: S51004-3.4

Chapter 5. Reference & Ordering InformationRevised: September 2004

Part number: S51005-2.1
http://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdfhttp://../datasheets/stratix/dsstratix_intro.pdf


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Chapter Revision Dates Stratix Device Handbook, Volume 1


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Altera Corporation ix

About This Handbook

This handbook provides comprehensive information about the AlteraStratix family of devices.

How to Find

Information

You can find more information in the following ways:

The Adobe Acrobat Find feature, which searches the text of a PDFdocument. Click the binoculars toolbar icon to open the Find dialogbox.

Acrobat bookmarks, which serve as an additional table of contents inPDF documents.

Thumbnail icons, which provide miniature previews of each page,provide a link to the pages.

Numerous links, shown in green text, which allow you to jump torelated information.

How to Contact

Altera

For the most up-to-date information about Altera products, go to theAltera world-wide web site at www.altera.com. For technical support on

this product, go to www.altera.com/mysupport. For additionalinformation about Altera products, consult the sources shown below.

Information Type USA & Canada All Other Locations

Technical support www.altera.com/mysupport/ www.altera.com/mysupport/

(800) 800-EPLD (3753)

(7:00 a.m. to 5:00 p.m. Pacific Time)

+1 408-544-8767

7:00 a.m. to 5:00 p.m. (GMT -8:00)

Pacific Time

Product literature www.altera.com www.altera.com

Altera literature services [email protected] [email protected]

Non-technical customer

service

(800) 767-3753 + 1 408-544-7000

7:00 a.m. to 5:00 p.m. (GMT -8:00)

Pacific Time

FTP site ftp.altera.com ftp.altera.com
http://www.altera.com/http://www.altera.com/mysupporthttp://www.altera.com/mysupport/http://www.altera.com/mysupport/http://www.altera.com/http://www.altera.com/mailto:[email protected]:[email protected]://ftp.altera.com/ftp://ftp.altera.com/http://www.altera.com/mysupportftp://ftp.altera.com/ftp://ftp.altera.com/mailto:[email protected]:[email protected]://www.altera.com/http://www.altera.com/http://www.altera.com/mysupport/http://www.altera.com/mysupport/http://www.altera.com/


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x Altera Corporation

Typographic Conventions Stratix Device Handbook, Volume 1

Typographic

Conventions

This document uses the typographic conventions shown below.

Visual Cue Meaning

Bold Type with Initial

Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are

shown in bold, initial capital letters. Example: Save As dialog box.

bold type External timing parameters, directory names, project names, disk drive names,

filenames, filename extensions, and software utility names are shown in bold

type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.

Italic Type with Initial Capital

Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75:

High-Speed Board Designs.

Italic type Internal timing parameters and variables are shown in italic type.

Examples: tPIA, n+ 1.

Variable names are enclosed in angle brackets (< >) and shown in italic type.Example: , .pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples:

Delete key, the Options menu.

Subheading Title References to sections within a document and titles of on-line help topics are

shown in quotation marks. Example: Typographic Conventions.

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1,

tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.

Anything that must be typed exactly as it appears is shown in Courier type. For

example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an

actual file, such as a Report File, references to parts of files (e.g., the AHDL

keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in

Courier.

1., 2., 3., and

a., b., c., etc.

Numbered steps are used in a list of items when the sequence of the items is

important, such as the steps listed in a procedure.

Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a par ticular topic.


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Altera Corporation Section I1

Section I. Stratix DeviceFamily Data Sheet

This section provides the data sheet specifications for Stratix devices.They contain feature definitions of the internal architecture,configuration and JTAG boundary-scan testing information, DCoperating conditions, AC timing parameters, a reference to powerconsumption, and ordering information for Stratix devices.

This section contains the following chapters:

Chapter 1, Introduction

Chapter 2, Stratix Architecture

Chapter 3, Configuration & Testing

Chapter 4, DC & Switching Characteristics

Chapter 5, Reference & Ordering Information

Revision History The table below shows the revision history for Chapters 1 through 5.

Chapter Date/Version Changes Made

1 July 2005, v3.2 Minor content changes.

September 2004, v3.1 Updated Table 16 on page 15.

April 2004, v3.0 Main section page numbers changed on first page.

Changed PCI-X to PCI-X 1.0 in Features on page 12.

Global change from SignalTap to SignalTap II.

The DSP blocks in Features on page 12 provide dedicated

implementation of multipliers that are now faster than 300 MHz.

January 2004, v2.2 Updated -5 speed grade device information in Table 1-6.

October 2003, v2.1 Add -8 speed grade device information.

July 2003, v2.0 Format changes throughout chapter.


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Section I2 Altera Corporation

Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1

2 July 2005 v3.2 Added Clear Signals section.

Updated Power Sequencing & Hot Socketing section.

Format changes.

September 2004, v3.1

Updated fast regional clock networks description on page 273. Deleted the word preliminary from the specification for the maximum

time to relock is 100 s on page 290.

Added information about differential SSTL and HSTL outputs in

External Clock Outputs on page 292.

Updated notes in Figure 255 on page 293.

Added information about mcounter to Clock Multiplication &

Division on page 2101.

Updated Note 1 in Table 258 on page 2101.

Updated description of Clock Multiplication & Division on

page 288.

Updated Table 222 on page 2102.

Added references to AN 349 and AN 329 to External RAM

Interfacing on page 2115. Table 225 on page 2116: updated the table, updated Notes 3 and

4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.


Added information about PCI Compliance to page 2120.

Table 232 on page 2126: updated the table and deleted Note 1.

Updated reference to device pin-outs now being available on the web

on page 2130.

Added Notes 4 and 5 to Table 236 on page 2130.



April 2004, v3.0 Added note 3 to rows 11 and 12 in Table 218.

Deleted Stratix and Stratix GX Device PLL Availability table. Added I/O standards row in Table 228 that support max and min

strength.

Row clk[1,3,8,10] was removed from Table 230.

Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,

LVDS, and HyperTransport technology rows in Table 232.

Removed the Left and Right I/O Banks row in Table 234.

Changed RCLK values in Figures 250 and 251.

External RAM Interfacing section replaced.

November 2003, v2.2 Added 672-pin BGA package information in Table 237.

Removed support for series and parallel on-chip termination.

Termination Technology renamed differential on-chip termination.

Updated the number of channels per PLL in Tables 2-38 through 2-42.

Updated Figures 265 and 267.

October 2003, v2.1 Updated DDR I information.

Updated Table 222.

Added Tables 225, 229, 230, and 272.

Updated Figures 259, 265, and 267.

Updated the Lock Detect section.



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Stratix Device Family Data Sheet

2 July 2003, v2.0 Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK

connections.

Updated ranges for EPLL post-scale and pre-scale dividers on page

2-85.

Updated PLL Reconfiguration frequency from 25 to 22 MHz on page

2-87.

New requirement to assert are set signal each PLL when it has to re-

acquire lock on either a new clock after loss of lock (page 2-96).

Updated max input frequency for CLK[1,3,8,10] from 462 to 500,

Table 2-24.

Renamed impedance matching to series termination throughout.

Updated naming convention for DQS pins on page 2-112 to match pin

tables.

Added DDR SDRAM Performance Specification on page 2-117.

Added external reference resistor values for terminator technology

(page 2-136).

Added Terminator Technology Specification on pages 2-137 and 2-138.

Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for

high speed differential channels at full speed.

Wire bond package performance specification for high speed

channels was increased to 624 Mbps from 462 Mbps throughout

chapter.

3 July 2005, v1.3 Updated Operating Modes section.

Updated Temperature Sensing Diode section.

UpdatedIEEE Std. 1149.1 (JTAG) Boundary-Scan Support section.

Updated Configuration section.

January 2005, v1.2 Updated limits for JTAG chain of devices.

September 2004, v1.1 Added new section, Stratix Automated Single Event Upset (SEU)

Detection on page 312.

Updated description of Custom-Built Circuitry on page 313.

April 2003, v1.0 No new changes in Stratix Device Handbookv2.0.

4 January 2006, v3.4 Added Table 4135.

July 2005, v3.3 Updated Tables 46 and 430.

Updated Tables 4103 through 4108.

Updated Tables 4114 through 4124.

Updated Table 4129.

Added Table 4130.



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4 January 2005, 3.2 Updated rise and fall input values.

September 2004, v3.1 Updated Note 3 in Table 48 on page 44.


Updated Table 420 on page 412 through Table 423 onpage 413. Added rows VIL(AC) and VIH(AC) to each table.

Updated Table 426 on page 414 through Table 429 on

page 415.


Updated description of External Timing Parameters on page 433.


Added signals tOUTCO, TXZ, and TZX to Figure 44 on page 433.

Added rows tM512CLKENSU and tM512CLKENH to Table 440 on

page 424.

Added rows tM4CLKENSU and tM4CLKENH to Table 441 on page 424.


Added rows tMRAMCLKENSU and tMRAMCLKENH to Table 442 on

page 425.





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4 Table 448 on page 430: added rows tM512CLKSENSU and tM512CLKENH,

and updated symbol names.

Updated power-up current (ICCINT) required to power a Stratix

device on page 417.


page 427.

Table 449 on page 431: added rows tM4KCLKENSU, tM4KCLKENH,

tM4KBESU, and tM4KBEH, deleted rows tM4KRADDRASU and tM4KRADDRH, and

updated symbol names.

Table 450 on page 431: added rows tMRAMCLKENSU, tMRAMCLKENH,

tMRAMBESU, and tMRAMBEH, deleted rows tMRAMADDRASU and

tMRAMRADDRH, and updated symbol names.

Table 452 on page 434: updated table, deleted Conditions

column, and added rows tXZ and tZX.


column, and added rows tXZ and tZX.

Table 453 on page 434: updated table and added rows tXZPLL and

tZXPLL.



column, and added rows tXZPLL and tZXPLL.


Deleted Note 2 from Table 455 on page 436 through Table 466 on

page 441.


page 456. Added rows TXZ, TZX, TXZPLL, and TZXPLL. Added Note 4 to Table 4101 on page 462.


page 450. Added new section I/O Timing Measurement Methodology on

page 460.


page 450.


page 456.

Added Note 4 to Table 4101 on page 462.

Table 4102 on page 464: updated table and added Note 4.

Updated description of External I/O Delay Parameters on

page 466.

Added Note 1 to Table 4109 on page 473 and Table 4110 on

page 474.


page 474.

Deleted Note 2 from Table 4103 on page 466 through Table 4106

on page 469.

Added new paragraph about output adder delayson page 468. Updated Table 4110 on page 474.

Added Note 1 to Table 4111 through Table 4113 on page 475.



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4 Updated Table 4123 on page 485 through Table 4126 on

page 492.


Table 4125 on page 488: moved to correct order in chapter, and

updated table. Updated Table 4126 on page 492.



April 2004, v3.0 Table 4129 on page 496: updated table and added Note 10.

Updated Table 4131 and Table 4132 on page 4100.



Updated Table 4124 on page 487. through Table 4126 on

page 492.

Added Note 10 to Table 4129 on page 496.

Moved Table 4127 on page 494 to correct order in the chapter.

Updated Table 4131 on page 4100 through Table 4132 onpage 4100.

Deleted tXZ and tZX from Figure 44.

Waveform was added to Figure 46.

The minimum and maximum duty cycle values in Note 3 ofTable 48

were moved to a new Table 49.

Changes were made to values in SSTL-3 Class I and II rows in

Table 417.

Note 1 was added to Table 434.

Added tSU_R and tSU_C rows inTable 438.

Changed Table 455 title from EP1S10 Column Pin Fast Regional

Clock External I/O Timing Parameters to EP1S10 External I/O

Timing on Column Pins Using Fast Regional Clock Networks. Changed values in Tables 446, 448 to 451, 4128, and 4131.

Added tARESET row in Tables 4127 to 4132.

Deleted -5 Speed Grade column in Tables 4117to 4119 and 4122

to 4123.

Fixed differential waveform in Figure 41.

Added Definition of I/O Skew section.

Added tSU and tCO_C rows and made changes to values in tPRE and

tCLKHL rows in Table 446.

Values changed in the tSU and tH rows in Table 447.

Values changed in the tM4KCLKHL row in Table 449.

Values changed in the tMRAMCLKHL row in Table 450.

Added Table 451 to Internal Timing Parameters section. The timing information is preliminary in Tables 455 through 496.

Table 4111 was separated into 3 tables: Tables 4111 to 4113.

November 2003, v2.2 Updated Tables 4127 through 4129.



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4 October 2003, v2.1 Added -8 speed grade information.

Updated performance information in Table 436.

Updated timing information in Tables 455 through 496.

Updated delay information in Tables 4103 through 4108.

Updated programmable delay information in Tables 4100 and4103.

July 2003, v2.0 Updated clock rates in Tables 4114 through 4123.

Updated speed grade information in the introduction on page 4-1.

Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD

are specified.

Added note 6 to Table 4-32.

Updated Stratix Performance Table 4-35.

Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4-

93. The Stratix timing models are final for all devices.

Updated Stratix IOE programmable delay chains in Tables 4-100 to 4-

101.

Added single-ended I/O standard output pin delay adders for loadingin Table 4-102.

Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107.

Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-

115.

Updated EPLL specification and fast PLL specification in Tables 4-

116 to 4-120.

5 September 2004, v2.1 Updated reference to device pin-outs on page 51 to indicate that

device pin-outs are no longer included in this manual and are now

available on the Altera web site.

April 2003, v1.0 No new changes in Stratix Device Handbook v2.0.



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Altera Corporation 11

July 2005

1. Introduction

Introduction The Stratix family of FPGAs is based on a 1.5-V, 0.13-m, all-layer copperSRAM process, with densities of up to 79,040 logic elements (LEs) and upto 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signalprocessing (DSP) blocks with up to 176 (9-bit 9-bit) embeddedmultipliers, optimized for DSP applications that enable efficientimplementation of high-performance filters and multipliers. Stratixdevices support various I/O standards and also offer a complete clockmanagement solution with its hierarchical clock structure with up to420-MHz performance and up to 12 phase-locked loops (PLLs).

The following shows the main sections in the Stratix Device Family DataSheet:

Section Page

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214TriMatrix Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 252PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2104High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2130Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2140

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 31SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 35Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 313

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419

Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

S51001-3.2


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12 Altera Corporation

Stratix Device Handbook, Volume 1 July 2005

Features

Features The Stratix family offers the following features:

10,570 to 79,040 LEs; see Table 11 Up to 7,427,520 RAM bits (928,440 bytes) available without reducing

logic resources

TriMatrixTM

memory consisting of three RAM block sizes toimplement true dual-port memory and first-in first-out (FIFO)buffers

High-speed DSP blocks provide dedicated implementation ofmultipliers (faster than 300 MHz), multiply-accumulate functions,and finite impulse response (FIR) filters

Up to 16 global clocks with 22 clocking resources per device region Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device

provide spread spectrum, programmable bandwidth, clock switch-over, real-time PLL reconfiguration, and advanced multiplicationand phase shifting

Support for numerous single-ended and differential I/O standards High-speed differential I/O support on up to 116 channels with up

to 80 channels optimized for 840 megabits per second (Mbps) Support for high-speed networking and communications bus

standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTMtechnology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),and SFI-4

Differential on-chip termination support for LVDS Support for high-speed external memory, including zero bus

turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM),and single data rate (SDR) SDRAM

Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-gradedevices, support for 33-MHz PCI (64 and 32 bit) in -8 and fasterspeed-grade devices

Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices Support for multiple intellectual property megafunctions from

Altera MegaCore functions and Altera Megafunction PartnersProgram (AMPPSM) megafunctions

Support for remote configuration updates


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July 2005 Stratix Device Handbook, Volume 1

Introduction

Table 11. Stratix Device Features EP1S10, EP1S20, EP1S25, EP1S30

Feature EP1S10 EP1S20 EP1S25 EP1S30

LEs 10,570 18,460 25,660 32,470

M512 RAM blocks (32 18 bits) 94 194 224 295M4K RAM blocks (128 36 bits) 60 82 138 171

M-RAM blocks (4K 144 bits) 1 2 2 4

Total RAM bits 920,448 1,669,248 1,944,576 3,317,184

DSP blocks 6 10 10 12

Embedded multipliers (1) 48 80 80 96

PLLs 6 6 6 10

Maximum user I/O pins 426 586 706 726

Table 12. Stratix Device Features EP1S40, EP1S60, EP1S80

Feature EP1S40 EP1S60 EP1S80

LEs 41,250 57,120 79,040

M512 RAM blocks (32 18 bits) 384 574 767

M4K RAM blocks (128 36 bits) 183 292 364

M-RAM blocks (4K 144 bits) 4 6 9

Total RAM bits 3,423,744 5,215,104 7,427,520

DSP blocks 14 18 22

Embedded multipliers (1) 112 144 176

PLLs 12 12 12

Maximum user I/O pins 822 1,022 1,238

Note to Tables 11 and 12:(1) This parameter lists the total number of 9 9-bit multipliers for each device. For the total number of 18 18-bit

multipliers per device, divide the total number of 9 9-bit multipliers by 2. For the total number of 36 36-bit

multipliers per device, divide the total number of 9 9-bit multipliers by 8.


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Features

Stratix devices are available in space-saving FineLine BGA and ball-gridarray (BGA) packages (see Tables 13 through 15). All Stratix devicessupport vertical migration within the same package (for example, youcan migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672-pin BGA package). Vertical migration means that you can migrate to

devices whose dedicated pins, configuration pins, and power pins are thesame for a given package across device densities. For I/O pin migrationacross densities, you must cross-reference the available I/O pins usingthe device pin-outs for all planned densities of a given package type to

identify which I/O pins are migrational. The Quartus II software canautomatically cross reference and place all pins except differential pinsfor migration when given a device migration list. You must use the pin-outs for each device to verify the differential placement migration. Afuture version of the Quartus II software will support differential pinmigration.

Table 13. Stratix Package Options & I/O Pin Counts

Device672-Pin

BGA

956-Pin

BGA

484-Pin

FineLine

BGA

672-Pin

FineLine

BGA

780-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,508-Pin

FineLine

BGA

EP1S10 345 335 345 426

EP1S20 426 361 426 586

EP1S25 473 473 597 706

EP1S30 683 597 726

EP1S40 683 615 773 822

EP1S60 683 773 1,022

EP1S80 683 773 1,203

Note to Table 13:(1) All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n)

that can be used for data inputs.

Table 14. Stratix BGA Package Sizes

Dimension 672 Pin 956 Pin

Pitch (mm) 1.27 1.27Area (mm2) 1,225 1,600

Length width (mm mm) 35 35 40 40


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Introduction

Stratix devices are available in up to four speed grades, -5, -6, -7, and -8,with -5 being the fastest. Table 16 shows Stratix device speed-gradeofferings.

Table 15. Stratix FineLine BGA Package Sizes

Dimension 484 Pin 672 Pin 780 Pin 1,020 Pin 1,508 Pin

Pitch (mm) 1.00 1.00 1.00 1.00 1.00

Area (mm2

) 529 729 841 1,089 1,600Length width

(mm mm)

23 23 27 27 29 29 33 33 40 40

Table 16. Stratix Device Speed Grades

Device 672-PinBGA

956-PinBGA

484-Pin

FineLine

BGA

672-Pin

FineLine

BGA

780-Pin

FineLine

BGA

1,020-Pin

FineLine

BGA

1,508-Pin

FineLine

BGA

EP1S10 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7

EP1S20 -6, -7 -5, -6, -7 -6, -7 -5, -6, -7

EP1S25 -6, -7 -6, -7, -8 -5, -6, -7 -5, -6, -7

EP1S30 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7

EP1S40 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7 -5, -6, -7

EP1S60 -6, -7 -5, -6, -7 -6, -7

EP1S80 -6, -7 -5, -6, -7 -5, -6, -7


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Features


25/862


July 2005

2. Stratix Architecture

Functional

Description

Stratix devices contain a two-dimensional row- and column-basedarchitecture to implement custom logic. A series of column and rowinterconnects of varying length and speed provide signal interconnectsbetween logic array blocks (LABs), memory block structures, and DSPblocks.

The logic array consists of LABs, with 10 logic elements (LEs) in eachLAB. An LE is a small unit of logic providing efficient implementation ofuser logic functions. LABs are grouped into rows and columns across thedevice.

M512 RAM blocks are simple dual-port memory blocks with 512 bits plusparity (576 bits). These blocks provide dedicated simple dual-port orsingle-port memory up to 18-bits wide at up to 318 MHz. M512 blocks aregrouped into columns across the device in between certain LABs.

M4K RAM blocks are true dual-port memory blocks with 4K bits plusparity (4,608 bits). These blocks provide dedicated true dual-port, simpledual-port, or single-port memory up to 36-bits wide at up to 291 MHz.These blocks are grouped into columns across the device in betweencertain LABs.

M-RAM blocks are true dual-port memory blocks with 512K bits plusparity (589,824 bits). These blocks provide dedicated true dual-port,simple dual-port, or single-port memory up to 144-bits wide at up to269 MHz. Several M-RAM blocks are located individually or in pairswithin the devices logic array.

Digital signal processing (DSP) blocks can implement up to either eightfull-precision 9 9-bit multipliers, four full-precision 18 18-bitmultipliers, or one full-precision 36 36-bit multiplier with add orsubtract features. These blocks also contain 18-bit input shift registers fordigital signal processing applications, including FIR and infinite impulse

response (IIR) filters. DSP blocks are grouped into two columns in eachdevice.

Each Stratix device I/O pin is fed by an I/O element (IOE) located at theend of LAB rows and columns around the periphery of the device. I/Opins support numerous single-ended and differential I/O standards.Each IOE contains a bidirectional I/O buffer and six registers forregistering input, output, and output-enable signals. When used with

S51002-3.2


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Functional Description

dedicated clocks, these registers provide exceptional performance andinterface support with external memory devices such as DDR SDRAM,FCRAM, ZBT, and QDR SRAM devices.

High-speed serial interface channels support transfers at up to 840 Mbps

using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/Ostandards.

Figure 21 shows an overview of the Stratix device.

Figure 21. Stratix Block Diagram

M512 RAM Blocks forDual-Port Memory, ShiftRegisters, & FIFO Buffers

DSP Blocks forMultiplication and FullImplementation of FIR Filters

M4K RAM Blocksfor True Dual-PortMemory & Other EmbeddedMemory Functions

IOEs Support DDR, PCI, GTL+, SSTL-3,SSTL-2, HSTL, LVDS, LVPECL, PCML,HyperTransport & other I/O Standards

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

IOEs

LABs

LABs

IOEs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

IOEs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs LABs

LABs

IOEs IOEs

LABs

LABs LABs

LABs LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

LABs

DSPBlock

M-RAM Block


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Stratix Architecture

The number of M512 RAM, M4K RAM, and DSP blocks varies by devicealong with row and column numbers and M-RAM blocks. Table 21 liststhe resources available in Stratix devices.

Logic Array

Blocks

Each LAB consists of 10 LEs, LE carry chains, LAB control signals, localinterconnect, LUT chain, and register chain connection lines. The localinterconnect transfers signals between LEs in the same LAB. LUT chainconnections transfer the output of one LEs LUT to the adjacent LE for fastsequential LUT connections within the same LAB. Register chainconnections transfer the output of one LEs register to the adjacent LEs

register within an LAB. The Quartus II Compiler places associated logicwithin an LAB or adjacent LABs, allowing the use of local, LUT chain,

and register chain connections for performance and area efficiency.Figure 22 shows the Stratix LAB.

Table 21. Stratix Device Resources

DeviceM512 RAM

Columns/Blocks

M4K RAM

Columns/Blocks

M-RAM

Blocks

DSP Block

Columns/Blocks

LAB

ColumnsLAB Rows

EP1S10 4 / 94 2 / 60 1 2 / 6 40 30

EP1S20 6 / 194 2 / 82 2 2 / 10 52 41

EP1S25 6 / 224 3 / 138 2 2 / 10 62 46

EP1S30 7 / 295 3 / 171 4 2 / 12 67 57

EP1S40 8 / 384 3 / 183 4 2 / 14 77 61

EP1S60 10 / 574 4 / 292 6 2 / 18 90 73

EP1S80 11 / 767 4 / 364 9 2 / 22 101 91


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Logic Array Blocks

Figure 22. Stratix LAB Structure

LAB Interconnects

The LAB local interconnect can drive LEs within the same LAB. The LABlocal interconnect is driven by column and row interconnects and LEoutputs within the same LAB. Neighboring LABs, M512 RAM blocks,M4K RAM blocks, or DSP blocks from the left and right can also drive anLABs local interconnect through the direct link connection. The directlink connection feature minimizes the use of row and columninterconnects, providing higher performance and flexibility. Each LE candrive 30 other LEs through fast local and direct link interconnects.Figure 23 shows the direct link connection.

Direct linkinterconnect fromadjacent block

Direct linkinterconnect toadjacent block

Row Interconnects ofVariable Speed & Length

Column Interconnects ofVariable Speed & Length

Three-Sided ArchitectureLocalInterconnect is Driven from Either Side byColumns & LABs, & from Above by Rows

Local Interconnect LAB

Direct linkinterconnect fromadjacent block

Direct linkinterconnect toadjacent block


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Figure 23. Direct Link Connection

LAB Control Signals

Each LAB contains dedicated logic for driving control signals to its LEs.The control signals include two clocks, two clock enables, twoasynchronous clears, synchronous clear, asynchronous preset/load,synchronous load, and add/subtract control signals. This gives a

maximum of 10 control signals at a time. Although synchronous load andclear signals are generally used when implementing counters, they canalso be used with other functions.

Each LAB can use two clocks and two clock enable signals. Each LABsclock and clock enable signals are linked. For example, any LE in aparticular LAB using the labclk1 signal will also use labclkena1. Ifthe LAB uses both the rising and falling edges of a clock, it also uses bothLAB-wide clock signals. De-asserting the clock enable signal will turn offthe LAB-wide clock.

Each LAB can use two asynchronous clear signals and an asynchronous

load/preset signal. The asynchronous load acts as a preset when theasynchronous load data input is tied high.

LAB

Direct link

interconnectto right

Direct link interconnect fromright LAB, TriMatrix memoryblock, DSP block, or IOE output

Direct link interconnect fromleft LAB, TriMatrix memory

block, DSP block, or IOE output

LocalInterconnect

Direct linkinterconnect

to left


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Logic Elements

With the LAB-wide addnsub control signal, a single LE can implement aone-bit adder and subtractor. This saves LE resources and improvesperformance for logic functions such as DSP correlators and signedmultipliers that alternate between addition and subtraction dependingon data.

The LAB row clocks [7..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnects inherent low skewallows clock and control signal distribution in addition to data. Figure 24shows the LAB control signal generation circuit.

Figure 24. LAB-Wide Control Signals

Logic Elements The smallest unit of logic in the Stratix architecture, the LE, is compactand provides advanced features with efficient logic utilization. Each LEcontains a four-input LUT, which is a function generator that canimplement any function of four variables. In addition, each LE contains aprogrammable register and carry chain with carry select capability. Asingle LE also supports dynamic single bit addition or subtraction modeselectable by an LAB-wide control signal. Each LE drives all types ofinterconnects: local, row, column, LUT chain, register chain, and directlink interconnects. See Figure 25.

labclkena1

labclk2labclk1

labclkena2

asyncload

or labpre

syncload

Dedicated

Row LAB

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnectlabclr1

labclr2

synclr

addnsub

8


31/862




Figure 25. Stratix LE

Each LEs programmable register can be configured for D, T, JK, or SRoperation. Each register has data, true asynchronous load data, clock,clock enable, clear, and asynchronous load/preset inputs. Global signals,general-purpose I/O pins, or any internal logic can drive the registersclock and clear control signals. Either general-purpose I/O pins orinternal logic can drive the clock enable, preset, asynchronous load, andasynchronous data. The asynchronous load data input comes from thedata3 input of the LE. For combinatorial functions, the register isbypassed and the output of the LUT drives directly to the outputs of theLE.

Each LE has three outputs that drive the local, row, and column routingresources. The LUT or register output can drive these three outputsindependently. Two LE outputs drive column or row and direct linkrouting connections and one drives local interconnect resources. Thisallows the LUT to drive one output while the register drives anotheroutput. This feature, called register packing, improves device utilizationbecause the device can use the register and the LUT for unrelated

labclk1

labclk2

labclr2

labpre/aload

Carry-In1

Carry-In0

LAB Carry-In

Clock &Clock Enable

Select

LAB Carry-Out

Carry-Out1

Carry-Out0

Look-UpTable(LUT)

CarryChain

Row, column,

and direct link

routing

Row, column,

and direct link

routing

ProgrammableRegister

PRN/ALD

CLRN

D Q

ENA

Register Bypass

PackedRegister Select

Chip-WideReset

labclkena1

labclkena2

SynchronousLoad andClear Logic

LAB-wideSynchronous

Load LAB-wideSynchronous

Clear

Asynchronous

Clear/Preset/Load Logic

data1

data2data3

data4

LUT chain

routing to next LE

labclr1

Local Routing

Register chain

output

ADATA

addnsub

RegisterFeedback

Register chainrouting from

previous LE


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Logic Elements

functions. Another special packing mode allows the register output tofeed back into the LUT of the same LE so that the register is packed withits own fan-out LUT. This provides another mechanism for improvedfitting. The LE can also drive out registered and unregistered versions ofthe LUT output.

LUT Chain & Register Chain

In addition to the three general routing outputs, the LEs within an LABhave LUT chain and register chain outputs. LUT chain connections allowLUTs within the same LAB to cascade together for wide input functions.Register chain outputs allow registers within the same LAB to cascadetogether. The register chain output allows an LAB to use LUTs for a singlecombinatorial function and the registers to be used for an unrelated shiftregister implementation. These resources speed up connections betweenLABs while saving local interconnect resources. See MultiTrackInterconnect on page 214 for more information on LUT chain andregister chain connections.

addnsub Signal

The LEs dynamic adder/subtractor feature saves logic resources byusing one set of LEs to implement both an adder and a subtractor. Thisfeature is controlled by the LAB-wide control signal addnsub. Theaddnsub signal sets the LAB to perform either A + B or A B. The LUTcomputes addition, and subtraction is computed by adding the twoscomplement of the intended subtractor. The LAB-wide signal converts totwos complement by inverting the B bits within the LAB and setting

carry-in = 1 to add one to the least significant bit (LSB). The LSB of anadder/subtractor must be placed in the first LE of the LAB, where theLAB-wide addnsub signal automatically sets the carry-in to 1. TheQuartus II Compiler automatically places and uses the adder/subtractorfeature when using adder/subtractor parameterized functions.

LE Operating Modes

The Stratix LE can operate in one of the following modes:

Normal mode

Dynamic arithmetic mode

Each mode uses LE resources differently. In each mode, eight availableinputs to the LEthe four data inputs from the LAB local interconnect;carry-in0 and carry-in1 from the previous LE; the LAB carry-infrom the previous carry-chain LAB; and the register chain connectionare directed to different destinations to implement the desired logicfunction. LAB-wide signals provide clock, asynchronous clear,


33/862




asynchronous preset load, synchronous clear, synchronous load, andclock enable control for the register. These LAB-wide signals are availablein all LE modes. The addnsub control signal is allowed in arithmeticmode.

The Quartus II software, in conjunction with parameterized functionssuch as library of parameterized modules (LPM) functions, automaticallychooses the appropriate mode for common functions such as counters,adders, subtractors, and arithmetic functions. If required, you can alsocreate special-purpose functions that specify which LE operating mode touse for optimal performance.

Normal Mode

The normal mode is suitable for general logic applications andcombinatorial functions. In normal mode, four data inputs from the LABlocal interconnect are inputs to a four-input LUT (see Figure 26). TheQuartus II Compiler automatically selects the carry-in or the data3signal as one of the inputs to the LUT. Each LE can use LUT chainconnections to drive its combinatorial output directly to the next LE in theLAB. Asynchronous load data for the register comes from the data3input of the LE. LEs in normal mode support packed registers.

Figure 26. LE in Normal Mode

Note toFigure 26:(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.

data1

4-InputLUT

data2

data3

cin (from cout

of previous LE)

data4

addnsub (LAB Wide)

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

aload

(LAB Wide)

ALD/PRE

CLRN

D

Q

ENA

ADATA

sclear

(LAB Wide)

sload

(LAB Wide)

Register chain

connection

LUT chain

connection

Register

chain output

Row, column, and

direct link routing

Row, column, and

direct link routing

Local routing

Register Feedback

(1)


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Logic Elements

Dynamic Arithmetic Mode

The dynamic arithmetic mode is ideal for implementing adders, counters,accumulators, wide parity functions, and comparators. An LE in dynamicarithmetic mode uses four 2-input LUTs configurable as a dynamicadder/subtractor. The first two 2-input LUTs compute two summationsbased on a possible carry-in of 1 or 0; the other two LUTs generate carryoutputs for the two chains of the carry select circuitry. As shown inFigure 27, the LAB carry-in signal selects either the carry-in0 orcarry-in1 chain. The selected chains logic level in turn determineswhich parallel sum is generated as a combinatorial or registered output.For example, when implementing an adder, the sum output is theselection of two possible calculated sums:data1 + data2 + carry-in0or data1 + data2 + carry-in1. The other two LUTs use the data1 anddata2 signals to generate two possible carry-out signalsone for a carryof 1 and the other for a carry of 0. The carry-in0 signal acts as the carryselect for thecarry-out0 output andcarry-in1 acts as the carry select

for the carry-out1 output. LEs in arithmetic mode can drive outregistered and unregistered versions of the LUT output.

The dynamic arithmetic mode also offers clock enable, counter enable,synchronous up/down control, synchronous clear, synchronous load,and dynamic adder/subtractor options. The LAB local interconnect datainputs generate the counter enable and synchronous up/down controlsignals. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II softwareautomatically places any registers that are not used by the counter intoother LABs. The addnsub LAB-wide signal controls whether the LE actsas an adder or subtractor.


35/862




Figure 27. LE in Dynamic Arithmetic Mode

Note toFigure 27:(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.

Carry-Select Chain

The carry-select chain provides a very fast carry-select function betweenLEs in arithmetic mode. The carry-select chain uses the redundant carrycalculation to increase the speed of carry functions. The LE is configuredto calculate outputs for a possible carry-in of 1 and carry-in of 0 inparallel. The carry-in0 and carry-in1 signals from a lower-order bitfeed forward into the higher-order bit via the parallel carry chain and feedinto both the LUT and the next portion of the carry chain. Carry-selectchains can begin in any LE within an LAB.

The speed advantage of the carry-select chain is in the parallel pre-computation of carry chains. Since the LAB carry-in selects the

precomputed carry chain, not every LE is in the critical path. Only thepropagation delay between LAB carry-in generation (LE 5 and LE 10) arenow part of the critical path. This feature allows the Stratix architecture toimplement high-speed counters, adders, multipliers, parity functions,and comparators of arbitrary width.

data1 LUTdata2data3

addnsub

(LAB Wide)

clock (LAB Wide)

ena (LAB Wide)

aclr (LAB Wide)

ALD/PRE

CLRN

D

Q

ENA

ADATA

Register chainconnection

LUT

LUT

LUT

Carry-Out1Carry-Out0

LAB Carry-In

Carry-In0

Carry-In1

(1)

sclear(LAB Wide)

sload(LAB Wide)

LUT chainconnection

Registerchain output

Row, column, anddirect link routing

Row, column, anddirect link routing

Local routing

aload(LAB Wide)

Register Feedback


36/862



Logic Elements

Figure 28 shows the carry-select circuitry in an LAB for a 10-bit fulladder. One portion of the LUT generates the sum of two bits using theinput signals and the appropriate carry-in bit; the sum is routed to theoutput of the LE. The register can be bypassed for simple adders or usedfor accumulator functions. Another portion of the LUT generates carry-

out bits. An LAB-wide carry in bit selects which chain is used for theaddition of given inputs. The carry-in signal for each chain, carry-in0or carry-in1, selects the carry-out to carry forward to the carry-insignal of the next-higher-order bit. The final carry-out signal is routed toan LE, where it is fed to local, row, or column interconnects.

The Quartus II Compiler automatically creates carry chain logic duringdesign processing, or you can create it manually during design entry.Parameterized functions such as LPM functions automatically takeadvantage of carry chains for the appropriate functions.

The Quartus II Compiler creates carry chains longer than 10 LEs by

linking LABs together automatically. For enhanced fitting, a long carrychain runs vertically allowing fast horizontal connections to TriMatrixmemory and DSP blocks. A carry chain can continue as far as a fullcolumn.


37/862




Figure 28. Carry Select Chain

Clear & Preset Logic ControlLAB-wide signals control the logic for the registers clear and presetsignals. The LE directly supports an asynchronous clear and presetfunction. The register preset is achieved through the asynchronous loadof a logic high. The direct asynchronous preset does not require a NOT-gate push-back technique. Stratix devices support simultaneous preset/

LE4

LE3

LE2

LE1A1B1

A2B2

A3B3

A4B4

Sum1

Sum2

Sum3

Sum4

LE10

LE9

LE8

LE7A7B7

A8B8

A9B9

A10B10

Sum7

LE6A6B6

Sum6

LE5A5B5

Sum5

Sum8

Sum9

Sum10

0 1

0 1LAB Carry-In

LAB Carry-Out

LUT

LUT

LUT

LUT

data1

LAB Carry-In

data2

Carry-In0

Carry-In1

Carry-Out0 Carry-Out1

Sum


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MultiTrack Interconnect

asynchronous load, and clear signals. An asynchronous clear signal takesprecedence if both signals are asserted simultaneously. Each LABsupports up to two clears and one preset signal.

In addition to the clear and preset ports, Stratix devices provide a chip-

wide reset pin (DEV_CLRn) that resets all registers in the device. Anoption set before compilation in the Quartus II software controls this pin.This chip-wide reset overrides all other control signals.

MultiTrack

Interconnect

In the Stratix architecture, connections between LEs, TriMatrix memory,DSP blocks, and device I/O pins are provided by the MultiTrackinterconnect structure with DirectDriveTM technology. The MultiTrackinterconnect consists of continuous, performance-optimized routing linesof different lengths and speeds used for inter- and intra-design blockconnectivity. The Quartus II Compiler automatically places critical designpaths on faster interconnects to improve design performance.

DirectDrive technology is a deterministic routing technology that ensuresidentical routing resource usage for any function regardless of placementwithin the device. The MultiTrack interconnect and DirectDrivetechnology simplify the integration stage of block-based designing byeliminating the re-optimization cycles that typically follow designchanges and additions.

The MultiTrack interconnect consists of row and column interconnectsthat span fixed distances. A routing structure with fixed length resourcesfor all devices allows predictable and repeatable performance when

migrating through different device densities. Dedicated rowinterconnects route signals to and from LABs, DSP blocks, and TriMatrixmemory within the same row. These row resources include:

Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the

device.

The direct link interconnect allows an LAB, DSP block, or TriMatrixmemory block to drive into the local interconnect of its left and right

neighbors and then back into itself. Only one side of a M-RAM blockinterfaces with direct link and row interconnects. This provides fastcommunication between adjacent LABs and/or blocks without using rowinterconnect resources.

The R4 interconnects span four LABs, three LABs and one M512 RAMblock, two LABs and one M4K RAM block, or two LABs and one DSPblock to the right or left of a source LAB. These resources are used for fast


39/862




row connections in a four-LAB region. Every LAB has its own set of R4interconnects to drive either left or right. Figure 29 shows R4interconnect connections from an LAB. R4 interconnects can drive and bedriven by DSP blocks and RAM blocks and horizontal IOEs. For LABinterfacing, a primary LAB or LAB neighbor can drive a given R4

interconnect. For R4 interconnects that drive to the right, the primaryLAB and right neighbor can drive on to the interconnect. For R4interconnects that drive to the left, the primary LAB and its left neighborcan drive on to the interconnect. R4 interconnects can drive other R4interconnects to extend the range of LABs they can drive. R4interconnects can also drive C4 and C16 interconnects for connectionsfrom one row to another. Additionally, R4 interconnects can drive R24interconnects.

Figure 29. R4 Interconnect Connections

Notes toFigure 29:(1) C4 interconnects can drive R4 interconnects.

(2) This pattern is repeated for every LAB in the LAB row.

The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSPblocks to the right or left from a source LAB. These resources are used for

fast row connections in an eight-LAB region. Every LAB has its own setof R8 interconnects to drive either left or right. R8 interconnectconnections between LABs in a row are similar to the R4 connectionsshown in Figure 29, with the exception that they connect to eight LABsto the right or left, not four. Like R4 interconnects, R8 interconnects candrive and be driven by all types of architecture blocks. R8 interconnects

PrimaryLAB (2)

R4 InterconnectDriving Left

Adjacent LAB canDrive onto Another

LAB's R4 Interconnect

C4, C8, and C16Column Interconnects (1)

R4 InterconnectDriving Right

LABNeighbor

LABNeighbor


40/862




can drive other R8 interconnects to extend their range as well as C8interconnects for row-to-row connections. One R8 interconnect is fasterthan two R4 interconnects connected together.

R24 row interconnects span 24 LABs and provide the fastest resource for

long row connections between LABs, TriMatrix memory, DSP blocks, andIOEs. The R24 row interconnects can cross M-RAM blocks. R24 rowinterconnects drive to other row or column interconnects at every fourthLAB and do not drive directly to LAB local interconnects. R24 rowinterconnects drive LAB local interconnects via R4 and C4 interconnects.R24 interconnects can drive R24, R4, C16, and C4 interconnects.

The column interconnect operates similarly to the row interconnect andvertically routes signals to and from LABs, TriMatrix memory, DSPblocks, and IOEs. Each column of LABs is served by a dedicated columninterconnect, which vertically routes signals to and from LABs, TriMatrixmemory and DSP blocks, and horizontal IOEs. These column resources

include:

LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down

direction C8 interconnects traversing a distance of eight blocks in up and

down direction C16 column interconnects for high-speed vertical routing through

the device

Stratix devices include an enhanced interconnect structure within LABsfor routing LE output to LE input connections faster using LUT chainconnections and register chain connections. The LUT chain connectionallows the combinatorial output of an LE to directly drive the fast inputof the LE right below it, bypassing the local interconnect. These resourcescan be used as a high-speed connection for wide fan-in functions fromLE 1 to LE 10 in the same LAB. The register chain connection allows theregister output of one LE to connect directly to the register input of thenext LE in the LAB for fast shift registers. The Quartus II Compilerautomatically takes advantage of these resources to improve utilizationand performance. Figure 210 shows the LUT chain and register chaininterconnects.


41/862




Figure 210. LUT Chain & Register Chain Interconnects

The C4 interconnects span four LABs, M512, or M4K blocks up or downfrom a source LAB. Every LAB has its own set of C4 interconnects to driveeither up or down. Figure 211 shows the C4 interconnect connectionsfrom an LAB in a column. The C4 interconnects can drive and be drivenby all types of architecture blocks, including DSP blocks, TriMatrixmemory blocks, and vertical IOEs. For LAB interconnection, a primaryLAB or its LAB neighbor can drive a given C4 interconnect.C4 interconnects can drive each other to extend their range as well asdrive row interconnects for column-to-column connections.

LE 1

LE 2

LE 3

LE 4

LE 5

LE 6

LE 7

LE 8

LE 9

LE 10

LUT ChainRouting to

Adjacent LE

LocalInterconnect

Register ChainRouting to AdjacentLE's Register Input

Local InterconnectRouting Among LEsin the LAB


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Figure 211. C4 Interconnect ConnectionsNote (1)

Note toFigure 211:(1) Each C4 interconnect can drive either up or down four rows.

C4 InterconnectDrives Local and R4Interconnectsup to Four Rows

Adjacent LAB candrive onto neighboringLAB's C4 interconnect

C4 InterconnectDriving Up

C4 InterconnectDriving Down

LAB

RowInterconnect

Local

Interconnect


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C8 interconnects span eight LABs, M512, or M4K blocks up or down froma source LAB. Every LAB has its own set of C8 interconnects to driveeither up or down. C8 interconnect connections between the LABs in acolumn are similar to the C4 connections shown in Figure 211 with theexception that they connect to eight LABs above and below. The C8

interconnects can drive and be driven by all types of architecture blockssimilar to C4 interconnects. C8 interconnects can drive each other toextend their range as well as R8 interconnects for column-to-columnconnections. C8 interconnects are faster than two C4 interconnects.

C16 column interconnects span a length of 16 LABs and provide thefastest resource for long column connections between LABs, TriMatrixmemory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and column interconnects at everyfourth LAB. C16 interconnects drive LAB local interconnects via C4 andR4 interconnects and do not drive LAB local interconnects directly.

All embedded blocks communicate with the logic array similar to LAB-to-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks)connects to row and column interconnects and has local interconnectregions driven by row and column interconnects. These blocks also havedirect link interconnects for fast connections to and from a neighboringLAB. All blocks are fed by the row LAB clocks, labclk[7..0].


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Table 22 shows the Stratix devices routing scheme.

Table 22. Stratix Device Routing Scheme

Source

Destination

LUTChain

RegisterChain

LocalInterconnect

DirectLinkInterconnect

R4Interconnect

R8Interconnect

R24Interconnect

C4Interconnect

C8Interconnect

C16Interconnect

LE

M512RAMB

lock

M4KRAMB

lock

M-RAMB

lock

DSPBlocks

ColumnIOE

Row

IOE

LUT Chain v

Register Chain v

Local

Interconnectv v v v v v v

Direct Link

Interconnectv

R4 Interconnect v v v v v

R8 Interconnect v v v

R24

Interconnectv v v v

C4 Interconnect v v v

C8 Interconnect v v v

C16

Interconnectv v v v

LE v v v v v v v v

M512 RAM

Blockv v v v v v

M4K RAM Block v v v v v v

M-RAM Block v v

DSP Blocks v v v v v v

Column IOE v v v v

Row IOE v v v v v v


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TriMatrix

Memory

TriMatrix memory consists of three types of RAM blocks: M512, M4K,and M-RAM blocks. Although these memory blocks are different, theycan all implement various types of memory with or without parity,including true dual-port, simple dual-port, and single-port RAM, ROM,and FIFO buffers. Table 23 shows the size and features of the different

RAM blocks.

Table 23. TriMatrix Memory Features (Part 1 of 2)

Memory FeatureM512 RAM Block

(32 18 Bits)

M4K RAM Block

(128 36 Bits)

M-RAM Block

(4K 144 Bits)

Maximum

performance

(1) (1) (1)

True dual-port

memoryv v

Simple dual-portmemory v v v

Single-port memory v v v

Shift register v v

ROM v v (2)

FIFO buffer v v v

Byte enable v v

Parity bits v v v

Mixed clock mode v v v

Memory initialization v v

Simple dual-port

memory mixed width

supportv v v

True dual-port

memory mixed width

supportv v

Power-up conditions Outputs cleared Outputs cleared Outputs

unknown

Register clears Input and output

registers

Input and output

registers

Output registers

Mixed-port read-

during-write

Unknown

output/old data

Unknown

output/old data

Unknown output


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TriMatrix Memory

1 Violating the setup or hold time on the address registers couldcorrupt the memory contents. This applies to both read andwrite operations.

Memory Modes

TriMatrix memory blocks include input registers that synchronize writes

and output registers to pipeline designs and improve systemperformance. M4K and M-RAM memory blocks offer a true dual-portmode to support any combination of two-port operations: two reads, twowrites, or one read and one write at two different clock frequencies.Figure 212 shows true dual-port memory.

Figure 212. True Dual-Port Memory Configuration

Configurations 512 1

256 2

128 4

64 8

64 9

32 16

32 18

4K 1

2K 2

1K 4

512 8

512 9

256 16

256 18

128 32

128 36

64K 8

64K 9

32K 16

32K 18

16K 32

16K 36

8K 64

8K 72

4K 128

4K 144

Notes to Table 23:(1) See Table 436 for maximum performance information.

(2) The M-RAM block does not support memory initializations. However, the

M-RAM block can emulate a ROM function using a dual-port RAM bock. The

Stratix device must write to the dual-port memory once and then disable the

write-enable ports afterwards.

Table 23. TriMatrix Memory Features (Part 2 of 2)

Memory FeatureM512 RAM Block

(32 18 Bits)

M4K RAM Block

(128 36 Bits)

M-RAM Block

(4K 144 Bits)

dataA[ ]

addressA[ ]

wrenA

clockA

clockenA

qA[ ]

aclrA

dataB[ ]

addressB[ ]

wrenB

clockB

clockenB

qB[ ]

aclrB

A B


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In addition to true dual-port memory, the memory blocks support simpledual-port and single-port RAM. Simple dual-port memory supports asimultaneous read and write and can either read old data before the writeoccurs or just read the dont care bits. Single-port memory supports non-simultaneous reads and writes, but the q[]port will output the data once

it has been written to the memory (if the outputs are not registered) orafter the next rising edge of the clock (if the outputs are registered). Formore information, see Chapter 2, TriMatrix Embedded Memory Blocks inStratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2.Figure 213 shows these different RAM memory port configurations forTriMatrix memory.

Figure 213. Simple Dual-Port & Single-Port Memory Configurations

Note toFigure 213:(1) Two single-port memory blocks can be implemented in a single M4K block as long

as each of the two independent block sizes is equal to or less than half of the M4K

block size.

The memory blocks also enable mixed-width data ports for reading andwriting to the RAM ports in dual-port RAM configuration. For example,the memory block can be written in 1 mode at port A and read out in 16mode from port B.

data[ ]wraddress[ ]

wren

inclock

inclocken

inaclr

rdaddress[ ]rden

q[ ]

outclock

outclocken

outaclr

data[ ]address[ ]

wren

inclock

inclocken

inaclr

q[ ]

outclock

outclocken

outaclr

Single-Port Memory (1)

Simple Dual-Port Memory
http://../app_notes/ch_3_vol_2.pdfhttp://../app_notes/ch_3_vol_2.pdfhttp://handbook_stratix_v2_cover.pdf/http://handbook_stratix_v2_cover.pdf/http://../app_notes/ch_3_vol_2.pdfhttp://../app_notes/ch_3_vol_2.pdf


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TriMatrix Memory

TriMatrix memory architecture can implement pipelined RAM byregistering both the input and output signals to the RAM block. AllTriMatrix memory block inputs are registered providing synchronouswrite cycles. In synchronous operation, the memory block generates itsown self-timed strobe write enable (WREN) signal derived from the global

or regional clock. In contrast, a circuit using asynchronous RAM mustgenerate the RAM WREN signal while ensuring its data and addresssignals meet setup and hold time specifications relative to the WRENsignal. The output registers can be bypassed. Flow-through reading ispossible in the simple dual-port mode of M512 and M4K RAM blocks byclocking the read enable and read address registers on the negative clockedge and bypassing the output registers.

Two single-port memory blocks can be implemented in a single M4Kblock as long as each of the two independent block sizes is equal to or lessthan half of the M4K block size.

The Quartus II software automatically implements larger memory bycombining multiple TriMatrix memory blocks. For example, two256 16-bit RAM blocks can be combined to form a 256 32-bit RAMblock. Memory performance does not degrade for memory blocks usingthe maximum number of words available in one memory block. Logicalmemory blocks using less than the maximum number of words usephysical blocks in parallel, eliminating any external control logic thatwould increase delays. To create a larger high-speed memory block, theQuartus II software automatically combines memory blocks with LEcontrol logic.

Clear Signals

When applied to input registers, the asynchronous clear signal for theTriMatrix embedded memory immediately clears the input registers.However, the output of the memory block does not show the effects untilthe next clock edge. When applied to output registers, the asynchronousclear signal clears the output registers and the effects are seenimmediately.

Parity Bit Support

The memory blocks support a parity bit for each byte. The parity bit,along with internal LE logic, can implement parity checking for errordetection to ensure data integrity. You can also use parity-size data wordsto store user-specified control bits. In the M4K and M-RAM blocks, byteenables are also available for data input masking during write operations.


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Shift Register Support

You can configure embedded memory blocks to implement shift registersfor DSP applications such as pseudo-random number generators, multi-channel filtering, auto-correlation, and cross-correlation functions. Theseand other DSP applications require local data storage, traditionallyimplemented with standard flip-flops, which can quickly consume manylogic cells and routing resources for large shift registers. A more efficientalternative is to use embedded memory as a shift register block, whichsaves logic cell and routing resources and provides a more efficientimplementation with the dedicated circuitry.

The size of a w m n shift register is determined by the input datawidth (w), the length of the taps (m), and the number of taps (n). The sizeof a w m n shift register must be less than or equal to the maximumnumber of memory bits in the respective block: 576 bits for the M512RAM block and 4,608 bits for the M4K RAM block. The total number of

shift register outputs (number of taps n width w) must be less than themaximum data width of the RAM block (18 for M512 blocks, 36 for M4Kblocks). To create larger shift registers, the memory blocks are cascadedtogether.

Data is written into each address location at the falling edge of the clockand read from the address at the rising edge of the clock. The shift registermode logic automatically controls the positive and negative edgeclocking to shift the data in one clock cycle. Figure 214 shows theTriMatrix memory block in the shift register mode.


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TriMatrix Memory

Figure 214. Shift Register Memory Configuration

Memory Block Size

TriMatrix memory provides three different memory sizes for efficientapplication support. The large number of M512 blocks are ideal fordesigns with many shallow first-in first-out (FIFO) buffers. M4K blocksprovide additional resources for channelized functions that do notrequire large amounts of storage. The M-RAM blocks provide a largesingle block of RAM ideal for data packet storage. The different-sized

blocks allow Stratix devices to efficiently support variable-sized memoryin designs.

The Quartus II software automatically partitions the user-definedmemory into the embedded memory blocks using the most efficient sizecombinations. You can also manually assign the memory to a specificblock size or a mixture of block sizes.

m-Bit Shift Register

w w

Documents

Stratix Handbook